CD74HC75 [TI]
Dual 2-Bit Bistable Transparent Latch; 双路2位双稳态透明锁存器
| 型号： | CD74HC75 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 2-Bit Bistable Transparent Latch |
| 文件： | 总8页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC75,
CD74HCT75
Data sheet acquired from Harris Semiconductor
SCHS135
Dual 2-Bit Bistable
Transparent Latch
March 1998
at V
= 5V
Features
CC
• HCT Types
• True and Complementary Outputs
• Buffered Inputs and Outputs
- 4.5V to 5.5V Operation
[ /Title
(CD74
HC75,
CD74
HCT75
)
/Sub-
ject
(Dual
2-Bit
Bistabl
e
- Direct LSTTL Input Logic Compatibility,
• Fanout (Over Temperature Range)
V = 0.8V (Max), V = 2V (Min)
IL IH
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The Harris CD74HC75 and CD74HCT75 are dual 2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs (1E and 2E) which are
active LOW. When the Enable input is HIGH data enters the
latch and appears at the Q output. When the Enable input
(1E and 2E) is LOW the output is not affected.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
Ordering Information
IL
IH
Pinout
CD74HC75, CD74HCT75
(PDIP, SOIC)
TOP VIEW
1Q0
1D0
1D1
2E
1
2
3
4
5
6
7
8
16 1Q0
15 1Q1
14 1Q1
13 1E
V
12 GND
11 2Q0
10 2Q0
CC
2D0
2D1
2Q1
9
2Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1666.1
Copyright © Harris Corporation 1998
1
CD74HC75, CD74HCT75
Functional Diagram
16 (10)
1 (11)
14 (8)
15 (9)
Q0
2 (6)
D0
Q0
Q1
Q1
1 OF 2
LATCHES
3 (7)
D1
E
13 (4)
TRUTH TABLE
INPUTS
OUTPUTS
D
L
E
Q
L
Q
H
H
H
L
H
X
H
L
Q0
Q0
NOTE:
H = High Level
L
X
= Low Level
= Don’t Care
Q0 = The level of Q before the transition of E.
LATCH 0
2 (6)
16 (10)
Q0
D0
D
Q
LE
LE
1 (11)
Q0
13 (4)
E
LE
LE
P
N
P
N
14 (8)
Q1
Q
LE
D
LE
Q
3 (7)
D1
LE
Q
LE
15 (9)
Q1
LATCH 1
5
V
CC
12
GND
FIGURE 1. LOGIC DIAGRAM
FIGURE 2. LATCH DETAIL
2
CD74HC75, CD74HCT75
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
I
I
CC
115
o
DC Drain Current, per Output, I
O
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
o
o
DC Output Diode Current, I
OK
For V < -0.5V or V > V
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Output Source or Sink Current per Output Pin, I
O
(SOIC - Lead Tips Only)
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
4.5
3.15
-
-
3.15
-
-
3.15
6
2
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
1.9
1.9
OH
IH
V
IL
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or
0.02
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
IH
V
IL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
-
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD74HC75, CD74HCT75
DC Electrical Specifications (Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
4
-
40
-
80
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
V
V
or
IH
4.5
4.4
4.4
4.4
OH
V
IL
CMOS Loads
High Level Output
Voltage
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
TTL Loads
Low Level Output
Voltage CMOS Loads
V
V
V
or
IH
-4
4.5
4.5
-
-
-
-
0.1
-
-
0.1
-
-
0.1
0.4
V
V
OL
IL
Low Level Output
Voltage
TTL Loads
0.02
4
0.26
0.33
Input Leakage
Current
I
V
and
GND
5.5
5.5
-
±0.1
-
±1
-
±1
µA
I
CC
Quiescent Device
Current
I
V
or
0
-
-
-
-
4
-
-
40
-
-
80
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 4)
V
4.5 to
5.5
100
360
450
490
CC
- 2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
D0, D1
UNIT LOADS
0.8
1.2
1E, 2E
NOTE: Unit Load is ∆I
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
CC
o
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Pulse Width Enable Input
t
-
-
2
80
16
14
60
12
10
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
75
15
13
-
-
-
-
-
-
120
24
20
90
18
15
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
W
4.5
6
Setup Time D to Enable
t
2
SU
4.5
6
4
CD74HC75, CD74HCT75
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
3
MAX
MIN
3
MAX
UNITS
ns
Hold Time Enable to D
t
-
2
4.5
6
3
3
3
-
-
-
-
-
-
-
-
-
-
-
-
H
3
3
ns
3
3
ns
HCT TYPES
Pulse Width Enable Input
t
-
-
-
4.5
4.5
4.5
16
12
3
-
-
-
-
-
-
20
15
3
-
-
-
24
18
3
-
-
-
ns
ns
ns
W
Setup Time D to Enable
Hold Time Enable to D
t
SU
t
H
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
MIN TYP MAX
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,
Data to Q
t
t
t
t
, t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
110
22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
165
33
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 50pF
L
C = 15pF
9
-
L
C = 50pF
6
19
130
26
-
24
165
33
-
28
195
39
-
L
Propagation Delay,
Data to Q
, t
PLH PHL
C = 50pF
2
-
L
C = 50pF
4.5
5
-
L
C = 15pF
10
-
L
C = 50pF
6
22
130
26
-
28
165
33
-
33
195
39
-
L
Propagation Delay,
Enable to Q
, t
PLH PHL
C = 50pF
2
-
L
C = 50pF
4.5
5
-
L
C = 15pF
10
-
L
C = 50pF
6
22
130
26
-
28
165
33
-
33
195
39
-
L
Propagation Delay,
Enable to Q
, t
PLH PHL
C = 50pF
2
-
L
C = 50pF
4.5
5
-
L
C = 15pF
11
-
L
C = 50pF
6
22
75
15
13
10
-
28
95
19
16
10
-
33
110
22
19
10
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
2
-
L
C = 50pF
4.5
6
-
L
C = 50pF
L
-
C
-
-
-
-
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
46
PD
HCT TYPES
Propagation Delay,
Data to Q
t
t
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
11
-
28
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
42
-
ns
ns
ns
ns
ns
ns
PLH PHL
L
C = 15pF
L
Propagation Delay,
Data to Q
, t
PLH PHL
C = 50pF
4.5
5
28
-
35
-
42
-
L
C = 15pF
11
-
L
Propagation Delay,
Enable to Q
, t
PLH PHL
C = 50pF
4.5
5
28
-
35
-
42
-
L
C = 15pF
11
L
5
CD74HC75, CD74HCT75
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Propagation Delay,
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
38
-
MIN
MAX
45
-
UNITS
ns
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
12
-
30
-
-
-
-
-
-
-
-
-
-
-
PLH PHL
L
Enable to Q
C = 15pF
ns
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
ns
C
-
-
-
pF
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
46
pF
PD
NOTES:
5. C
is used to determine the dynamic power consumption, per latch.
2
PD
6. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V
= supply voltage.
D
CC
i
L
i
L
CC
Test Circuits and Waveforms
I
t
+ t
WH
=
WL
I
t C = 6ns
fC
L
r
L
t
+ t
=
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
0.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
CD74HC75, CD74HCT75
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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