CD74HC93 [TI]
High Speed CMOS Logic 4-Bit Binary Ripple Counter; 高速CMOS逻辑4位二进制异步计数器
| 型号： | CD74HC93 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 4-Bit Binary Ripple Counter |
| 文件： | 总7页 (文件大小：50K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC93,
CD74HCT93
Data sheet acquired from Harris Semiconductor
SCHS138
High Speed CMOS Logic
August 1997
4-Bit Binary Ripple Counter
Features
Description
• Can Be Configured to Divide By 2, 8, and 16
• Asynchronous Master Reset
The Harris CD74HC93 and CD74HCT93 are high speed
silicon-gate CMOS devices and are pin-compatible with low
power Schottky TTL (LSTTL). These 4-bit binary ripple
counters consist of four master-slave flip-flops internally
connected to provide a divide-by-two-section and a divid- by-
eight-section. Each section has a separate clock input (CP0
and CP1) to innate state changes of the counter on the HIGH
to LOW clock transition. Sate changes of the Qn outputs do
not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding
spikes and should not be used for clocks or strobes.
[ /Title
(CD74
HC93,
CD74
HCT93
)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
/Sub-
ject
• Significant Power Reduction Compared to LSTTL
Logic ICs
A gated AND asynchronous master reset (MR1 and MR2 is
provided which overrides both clocks and resets (clears) all
flip-flops.
(High
Speed
CMOS
Logic
4-Bit
Binary
Ripple
Counte
r)
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
Because the output from the divide by two section is not
internally connected to the succeeding stages, the device
may be operated in various counting modes.
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
In a 4-bit ripple counter the output Q0 must be connected
externally to input CP1. The input count pulses are applied
to clock input CP0. Simultaneous frequency divisions of 2, 4,
8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs
as shown in the function table. As a 3-bit ripple counter the
input count pulses are applied to input CP1.
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
Simultaneous frequency divisions of 2, 4, and 8 are available
CD74HC93, CD74HCT93
(PDIP, SOIC)
at the Q , Q , Q outputs. Independent use of the first flip-
1
2
3
flop is available if the reset function coincides with the reset
TOP VIEW
of the 3-bit ripple-through counter.
CP1
1
2
3
4
5
6
7
14 CPO
13 NC
Ordering Information
MR1
MR2
NC
TEMP. RANGE
PKG.
NO.
12
Q
0
o
PART NUMBER
CD74HC93E
CD74HCT93E
CD74HC93M
CD74HCT93M
NOTES:
( C)
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
11 Q
3
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E14.3
V
10 GND
CC
E14.3
NC
NC
9
8
Q
1
2
Q
M14.15
M14.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1849.1
Copyright © Harris Corporation 1997
1
CD74HC93, CD74HCT93
TRUTH TABLE
OUTPUTS
COUNT
Q
Q
Q
Q
3
0
1
2
0
1
L
L
L
L
H
L
L
H
H
L
L
L
L
L
2
3
H
L
L
L
4
H
H
H
H
L
L
5
H
L
L
L
6
H
H
L
L
7
H
L
L
8
H
H
H
H
H
H
H
H
9
H
L
L
L
10
11
12
13
14
15
H
H
L
L
H
L
L
H
H
H
H
H
L
L
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level
MODE SELECTION
RESET OUTPUTS
OUTPUTS
MR1
H
MR2
H
Q
Q
Q
Q
3
0
1
2
L
L
L
L
L
H
Count
Count
Count
Count
H
L
L
L
NOTE: H = High Voltage Level, L = Low Voltage Level
2
CD74HC93, CD74HCT93
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
3
CD74HC93, CD74HCT93
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
CP0, CP1
UNIT LOADS
0.6
0.4
MR1, MR2
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
TEST CONDITIONS
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Clock Frequency
f
2
6
-
-
-
-
-
-
5
24
28
100
20
17
-
-
-
-
-
-
4
20
24
120
24
20
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
6
2
Clock Pulse Width
CP0, CP1
t
w
4.5
6
ns
ns
4
CD74HC93, CD74HCT93
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
TEST CONDITIONS
PARAMETER
SYMBOL
V
(V)
MIN
80
16
14
50
10
9
MAX
MIN
100
20
MAX
MIN
120
24
MAX
UNITS
ns
CC
Reset Pulse Width
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
4.5
ns
6
2
17
20
ns
Reset Removal Time
t
65
75
ns
REM
4.5
6
13
15
ns
11
13
ns
HCT TYPES
Maximum Clock Frequency
f
4.5
4.5
30
16
-
-
24
20
-
-
20
24
-
-
mHz
ns
MAX
Clock Pulse Width
CP0, CP1
t
W
Reset Pulse Width
t
4.5
4.5
16
10
-
-
20
13
-
-
24
15
-
-
ns
ns
W
Reset Removal Time
t
REM
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay Time
CP0 to Q0
t
, t
PLH PHL
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
155
31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
190
38
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C = 50pF
L
C = 15pF
10
-
L
C = 50pF
6
21
135
27
26
170
34
29
230
46
39
305
61
-
32
205
41
35
280
56
48
370
74
-
L
CP1 to Q1
CP1 to Q2
CP1 to Q3
t
t
t
, t
PLH PHL
C = 50pF
2
L
C = 50pF
4.5
6
L
C = 50pF
23
L
, t
PLH PHL
C = 50pF
2
185
37
L
C = 50pF
4.5
6
L
C = 50pF
31
L
, t
PLH PHL
C = 50pF
2
245
49
L
C = 50pF
4.5
5
L
C = 15pF
21
-
-
L
C = 50pF
6
42
52
195
39
63
235
47
-
L
MR1, MR2 to Qn
t
, t
PLH PHL
C = 50pF
2
155
31
L
C = 50pF
4.5
5
L
C = 15pF
13
L
C = 50pF
6
26
75
15
13
10
-
33
95
19
16
10
10
40
110
22
19
10
19
L
Output Transition Time
t
, t
TLH THL
C = 50pF
2
-
-
L
4.5
6
-
Input Capacitance
C
C = 50pF
L
-
-
IN
Power Dissipation Capacitance
C
-
-
25
PD
5
CD74HC93, CD74HCT93
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
V
CC
PARAMETER
HCT TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay Time
CP0 to Q0
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
34
-
-
-
-
-
-
-
-
-
-
-
-
-
-
43
-
-
-
-
-
-
-
-
-
-
-
-
-
-
51
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C = 15pF
L
CP1 to Q1
t
t
t
t
, t
PLH PHL
C = 50pF
4.5
5
34
-
43
-
51
-
L
C = 15pF
-
L
CP1 to Q2
, t
PLH PHL
C = 50pF
4.5
5
-
46
-
58
-
69
-
L
C = 15pF
-
L
CP1 to Q3
, t
PLH PHL
C = 50pF
4.5
5
-
58
-
73
-
87
-
L
C = 15pF
24
-
L
MR1, MR2 to Qn
, t
PLH PHL
C = 50pF
4.5
5
33
-
41
-
50
-
L
C = 15pF
13
-
L
Output Transition Time
Input Capacitance
t
, t
C = 50pF
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
L
C
C = 50pF
L
-
IN
Power Dissipation Capacitance
C
-
-
25
PD
Test Circuits and Waveforms
t C
t C
t C
f
t C
r
L
f
L
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
H(H)
t
t
H(L)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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