CD74HCT137E [TI]
High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches; 高速CMOS逻辑， 3至8线译码器多路解复用器与地址锁存器
| 型号： | CD74HCT137E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches |
| 文件： | 总10页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC137, CD74HCT137,
CD74HC237, CD74HCT237
Data sheet acquired from Harris Semiconductor
SCHS146
High Speed CMOS Logic, 3-to-8 Line Decoder
Demultiplexer with Address Latches
March 1998
Features
• Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
[ /Title
(CD74
HC137
,
- Active High for CD74HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
CD74
HCT13
7,
• Typical Propagation Delay of 13ns at V
o
= 5V,
CC
15pF, T = 25 C (CD74HC237)
A
• Fanout (Over Temperature Range)
CD74
HC237
,
CD74
HCT23
7)
/Sub-
ject
(High
Speed
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%, of V
IL IH
CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
(PDIP, SOIC)
TOP VIEW
A
A
A
1
2
3
4
5
6
7
8
16 V
15 Y
14 Y
13 Y
12 Y
11 Y
10 Y
0
1
3
CC
0
1
LE
2
OE
1
0
7
3
OE
Y
4
5
9
Y
GND
6
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1886.1
Copyright © Harris Corporation 1998
1
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Description
The Harris CD74HC137, CD74HC237 and CD74HCT137,
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE) sig-
nal to isolate the outputs from select-input changes. A “Low”
LE makes the output transparent to the input and the circuit
functions as a one-of-eight decoder. Two Output Enable
inputs (OE and OE ) are provided to simplify cascading
1
0
and to facilitate demultiplexing. The demultiplexing function
is accomplished by using the A , A , A inputs to select the
0
1
2
desired output and using one of the other Output Enable
inputs as the data input while holding the other Output
Enable input in its active state. In the CD74HC137 and
CD74HCT137 the selected output is a “Low”; in the
CD74HC237 and CD74HCT237 the selected output is a
“High”.
Ordering Information
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
E16.3
CD74HC137E
CD74HCT137E
CD74HC237E
CD74HC237M
CD74HCT237E
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC M16.15
16 Ld PDIP E16.3
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
2
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Functional Diagram
HC/HCT HC/HCT
237 137
1
2
3
15
14
13
12
11
10
9
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3-BIT
LATCH
1 OF 8
DECODER
4
LE
5
OE
1
6
7
OE
0
GND = 8
= 16
V
CC
CD74HC137, CD74HCT137 TRUTH TABLE
INPUTS
OE
OUTPUTS
LE
X
X
L
OE
X
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
7
0
1
2
1
0
0
1
2
3
4
5
6
H
X
L
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
H
H
H
H
L
X
L
X
L
X
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
X
H
H
H
H
L
L
H
L
H
H
H
L
H
H
X
H
H
L
H
X
H
H
Depends upon the address previously applied while LE was at a logic low.
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD74HC237, CD74HCT237 TRUTH TABLE
INPUTS
OE
OUTPUTS
LE
X
X
L
OE
X
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
7
0
1
2
1
0
0
1
2
3
4
5
6
H
X
L
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
X
L
X
L
X
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
X
L
L
H
L
L
H
H
X
L
H
X
H
Depends upon the address previously applied while LE was at a logic low.
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
3
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Functional Block Diagram
A
0
15
14
LE
Y
Y
Y
Y
Y
0
1
2
3
4
5
6
7
1
A
p
n
0
A
0
LE
LE
p
n
13
12
LE
A
1
2
A
A
A1 LATCH
1
A
11
0
10
Y
A
A
2
3
A2 LATCH
LE
2
2
9
Y
Y
7
4
5
LE
LE
OE
1
0
6
OE
4
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
5
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
(Note)
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1.5
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
A to LE Setup Time
SYMBOL
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
t
2
4.5
6
50
10
9
-
-
-
-
-
-
-
-
-
-
-
-
65
13
11
40
8
-
-
-
-
-
-
75
15
13
45
9
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
n
SU
A
to LE Hold Time
t
2
30
6
n
H
4.5
6
5
7
8
6
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
LE Pulse Width
SYMBOL
(V)
MIN
50
10
9
TYP
MAX
MIN
65
13
1
MAX
MIN
75
MAX
UNITS
ns
t
2
-
-
-
-
-
-
-
-
-
-
-
-
W
4.5
6
15
ns
13
ns
HCT TYPES
An to LE Setup Time
t
4.5
10
-
-
13
-
15
-
ns
SU
An to LE Hold Time
CD74HCT137
t
t
H
4.5
4.5
4.5
7
5
-
-
-
-
-
-
9
5
-
-
-
11
5
-
-
-
ns
ns
ns
CD74HCT237
H
LE Pulse Width
t
10
13
15
W
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
t
C = 50pF
2
-
-
180
-
225
-
270
ns
PLH, PHL
L
CD74HC137, CD74HCT137
An to any Y
4.5
6
-
-
-
-
-
-
36
31
-
-
-
45
38
-
-
-
54
46
ns
ns
ns
Propagation Delay
t
t
C = 50pF
2
160
200
240
PLH, PHL
L
CD74HC237, CD74HCT237
An to any Y
4.5
6
-
-
-
-
32
27
-
-
40
34
-
-
48
41
ns
ns
Address to Output
CD74HC137
t
, t
PLH PHL
C
C
= 15pF
= 15pF
5
5
5
-
-
-
-
-
-
-
-
-
-
15
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
CD74HC237
t , t
PLH PHL
-
-
-
L
OE to any Y or Y
t
t
C = 50pF
2
145
29
25
145
29
25
190
38
32
180
36
31
180
36
31
240
48
41
220
44
38
220
44
38
285
57
48
0
PLH, PHL
L
4.5
6
-
-
OE to any Y or Y
1
t
, t
TLH THL
C = 50pF
2
-
L
4.5
6
-
-
LE to any Y or Y
t
, t
TLH THL
C
= 50pF
2
-
L
4.5
6
-
-
Power Dissipation
Capacitance, (Notes 4, 5)
CD74HC137
CD74HC237
C
C
C
C
= 15pF
= 15pF
5
5
-
-
-
-
-
-
19
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
ns
ns
ns
pF
PD
L
-
-
PD
L
Output Transition Time
t
, t
TLH THL
C = 50pF
L
2
75
15
13
10
95
19
16
10
110
22
19
10
4.5
6
-
-
Input Capacitance
C
-
-
-
I
7
CD74HC137, CD74HCT137, CD74HC237, CD74HCT237
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
PARAMETER
HCT TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
An to any Y or Y
Address to Output
t
t
t
t
, t
C
C
C
C
= 50pF
= 15pF
= 50pF
= 50pF
4.5
5
-
-
-
-
-
-
-
-
-
16
-
38
-
-
48
-
-
-
-
-
-
-
-
57
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
L
L
L
L
, t
PLH PHL
-
-
-
-
-
-
-
-
OE to any Y (HC137)
, t
PLH PHL
4.5
4.5
4.5
4.5
4.5
4.5
35
33
37
35
44
42
44
41
46
44
55
53
53
60
56
53
66
63
0
OE to any Y (HC237)
, t
PLH PHL
-
0
OE to any Y (HC137)
t
t
, t
TLH THL
C = 50pF
-
1
L
OE to any Y (HC237)
1
, t
TLH THL
C = 50pF
L
-
LE to any Y (HC137)
LE to any Y (HC237)
t
, t
CL = 50pF
-
TLH THL
t
t
, t
TLH THL
C = 50pF
-
L
Power Dissipation
Capacitance, (Notes 4, 5)
CD74HC137
CD74HC237
C
C
C
= 15pF
5
5
-
-
19
23
-
-
-
-
-
-
-
pF
pF
ns
pF
PD
L
C = 15pF
-
-
-
PD
L
Output Transition Time
Input Capacitance
NOTES:
, t
TLH THL
C = 50pF
L
4.5
-
15
10
19
10
22
10
C
-
-
-
-
-
I
4. C
PD
is used to determine the dynamic power consumption, per gate.
2
5. P = V
CC
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
L
i
L
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
8
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
9
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
CD74HCT137M96E4
Decoder/Driver, HCT Series, Inverted Output, CMOS, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
ROCHESTER
©2020 ICPDF网 联系我们和版权申明