CD74HCT14 [TI]
High Speed CMOS Logic Hex Inverting Schmitt Trigger; 高速CMOS逻辑六角反相施密特触发器
| 型号： | CD74HCT14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Hex Inverting Schmitt Trigger |
| 文件： | 总7页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC14,
CD74HCT14
Data sheet acquired from Harris Semiconductor
SCHS129
High Speed CMOS Logic
Hex Inverting Schmitt Trigger
January 1998
at V
= 5V
Features
CC
• HCT Types
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
- 4.5V to 5.5V Operation
[ /Title
(CD74H
C14,
CD74H
CT14)
/Subject
(High
Speed
CMOS
Logic
- Direct LSTTL Input Logic Compatibility,
• Fanout (Over Temperature Range)
V = 0.8V (Max), V = 2V (Min)
IL IH
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The Harris CD74HC14, CD74HCT14 each contain 6
inverting Schmitt Triggers in one package.
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HC Types
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
( C)
PACKAGE
- 2V to 6V Operation
Hex
Invert-
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD54HCT14F
-55 to 125
14 Ld CERDIP F14.3
Pinout
CD54HC14, CD54HCT14, CD74HC14, CD74HCT14
(PDIP, CERDIP, SOIC)
TOP VIEW
1A
1Y
1
2
3
4
5
6
7
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
2A
2Y
3A
3Y
9
8
4A
4Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1781.1
Copyright © Harris Corporation 1998
1
CD74HC14, CD74HCT14
Functional Diagram
2
1
1A
1Y
2Y
3Y
4Y
5Y
6Y
4
3
2A
6
5
3A
8
9
4A
11
10
12
5A
13
6A
GND = 7
V
= 14
CC
TRUTH TABLE
INPUT (A)
OUTPUT (Y)
L
H
L
H
NOTE:
H= High Level
L = Low Level
Logic Diagram
nA
nY
2
CD74HC14, CD74HCT14
V
H
V
O
V
= V + - V -
T T
H
V
I
V - V +
T
T
V +
V -
T
T
V
CC
V
V
H
I
GND
V
CC
V
O
GND
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP
3
CD74HC14, CD74HCT14
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
JC
90
130
120
-
55
-
IK
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
O
O
CC
o
DC Drain Current, per Output, I
O
o
o
For -0.5V < V < V
+0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
(SOIC - Lead Tips Only)
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time, t , t
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
25 C
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Input Switch Points
V +
-
-
-
-
2
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
-
1.5
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
-
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
-
1.5
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
-
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
-
1.5
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T
4.5
6
2
V -
-
-
T
4.5
6
V
2
H
4.5
6
High Level Output
Voltage CMOS Loads
V
V - or
-0.02
2
OH
T
V +
T
-0.02
-0.02
-
4.5
6
-
-
-
-
-
-
High Level Output
Voltage TTL Loads
-
-
-
-
-4
4.5
6
3.98
5.48
-
3.84
5.34
-
3.7
5.2
-
-5.2
-
-
-
4
CD74HC14, CD74HCT14
DC Electrical Specifications (Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V) (mA)
I
V
(V)
MIN
MAX
0.1
MIN
MAX
0.1
0.1
0.1
-
MIN
MAX
0.1
0.1
0.1
-
UNITS
I
O
CC
LowLevelOutputVoltage
CMOS Loads
V
V
V
or
IH
0.02
0.02
0.02
-
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
OL
IL
4.5
0.1
6
-
0.1
V
Low Level Output Voltage
TTL Loads
-
V
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
V
5.2
-
V
Input Leakage Current
I
V
or
6
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
-
6
-
2
-
20
-
40
µA
CC
CC
HCT TYPES
Input Switch Points
V +
-
4.5
5.5
4.5
5.5
4.5
5.5
4.5
1.2
1.4
0.5
0.6
0.4
0.4
4.4
1.9
2.1
1.2
1.4
1.4
1.5
-
1.2
1.4
0.5
0.6
0.4
0.4
4.4
1.9
2.1
1.2
1.4
1.4
1.5
-
1.2
1.4
0.5
0.6
0.4
0.4
4.4
1.9
2.1
1.2
1.4
1.4
1.5
-
V
V
V
V
V
V
V
T
V -
T
V
H
High Level Output
Voltage CMOS Loads
V
V
or
IH
-0.02
-4
OH
V
IL
High Level Output
Voltage TTL Loads
4.5
4.5
4.5
5.5
3.98
-
3.84
-
3.7
-
V
V
LowLevelOutputVoltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
-
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
OL
V
IL
Low Level Output Voltage
TTL Loads
0.26
±0.1
V
Input Leakage Current
I
V
-
µA
I
CC
and
GND
Quiescent Device
Current
I
V
GND
or
0
-
5.5
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
Additional Quiescent
Device Current Per Input (Note 4)
∆I
CC
V
4.5 to
5.5
360
450
490
CC
- 2.1
Pin: 1 Unit Load
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
nA
UNIT LOADS
0.6
NOTE: Unit Load is ∆I
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
CC
o
5
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,
A to Y
t
, t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
135
27
-
-
-
-
-
-
-
-
-
-
170
34
-
-
-
205
41
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 50pF
L
C = 15pF
11
-
-
L
C = 50pF
6
23
75
15
13
10
-
29
95
19
16
10
-
-
35
110
22
19
10
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
18
-
4.5
6
-
-
-
C
-
-
-
-
-
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
20
-
PD
HCT TYPES
Propagation Delay,
A to Y
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
16
-
38
-
-
-
-
-
-
48
-
-
-
-
-
-
57
-
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
20
PD
NOTES:
5. C
is used to determine the dynamic power consumption, per inverter.
2
PD
6. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
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