CD74HCT154E [TI]
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer; 高速CMOS逻辑4至16线路解码器/多路解复用器
| 型号： | CD74HCT154E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer |
| 文件： | 总6页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC154,
CD74HCT154
Data sheet acquired from Harris Semiconductor
SCHS152
High Speed CMOS Logic
September 1997
4-to-16 Line Decoder/Demultiplexer
Features
Description
• Two Enable Inputs to Facilitate Demultiplexing and
Cascading Functions
The Harris CD74HC154 and CD74HCT154 are 4-to-16 line
decoders/demultiplexers with two enable inputs, E1 and E2.
A High on either enable input forces the output into the High
state. The demultiplexing function is performed by using the
four input lines, A0 to A3, to select the output lines Y0 to
Y15, and using one enable as the data input while holding
the other enable low.
[ /Title
(CD74
HC154
,
CD74
HCT15
4)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PKG.
/Sub-
ject
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E24.6
E24.6
E24.3
E24.3
• HC Types
CD74HC154E
CD74HCT154E
CD74HC154EN
CD74HC154EN
CD74HC154M
CD74HCT154M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
24 Ld PDIP
24 Ld PDIP
24 Ld PDIP
24 Ld PDIP
- 2V to 6V Operation
(High
Speed
CMOS
Logic
4-to-16
Line
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
CC
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
24 Ld SOIC M24.3
24 Ld SOIC M24.3
V = 0.8V (Max), V = 2V (Min)
IL IH
Decod
er/Dem
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or d ie for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC154, CD74HCT154
(PDIP, SOIC)
TOP VIEW
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
2
3
4
5
6
7
8
9
24
V
CC
23 A0
22 A1
21 A2
20 A3
19 E2
18 E1
17 Y15
16 Y14
15 Y13
14 Y12
13 Y11
Y9 10
Y10 11
GND 12
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1657.1
Copyright © Harris Corporation 1997
1
CD74HC154, CD74HCT154
Functional Diagram
1
Y0
2
Y1
3
Y2
4
Y3
5
Y4
6
Y5
7
Y6
23
22
21
20
8
A0
A1
A2
A3
Y7
9
Y8
10
11
13
14
15
16
17
Y9
Y10
Y11
Y12
Y13
Y14
Y15
18
19
E1
E2
GND = 12
= 24
V
CC
TRUTH TABLE
INPUTS
OUTPUTS
E1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
E2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
A3
L
A2
L
A1
L
A0
L
Y0
L
Y1
Y2
H
H
L
Y3
H
H
H
L
Y4
H
H
H
H
L
Y5
H
H
H
H
H
L
Y6
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
L
Y8
H
H
H
H
H
H
H
H
L
Y9 Y10 Y11 Y12 Y13 Y14 Y15
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
H
L
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
H
X
X
X
H
H
H
H
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2
CD74HC154, CD74HCT154
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package (.300). . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package (.600). . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
60
75
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC154, CD74HCT154
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
A0 - A3
UNIT LOADS
1.4
E1, E2
1.3
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay (Figure 1)
Address to Output
t
t
C = 50pF
2
-
-
-
175
35
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
C =15pF
14
-
L
C = 50pF
6
30
175
35
-
37
220
44
-
45
265
53
-
L
E1 to Output
t
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
14
-
L
C = 50pF
6
30
37
45
L
4
CD74HC154, CD74HCT154
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
PARAMETER
E2 to Output
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
t
C = 50pF
2
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
C =15pF
14
-
L
C = 50pF
6
30
75
15
13
10
-
37
95
19
16
10
-
45
110
22
19
10
-
L
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
Input Capacitance
C
-
-
-
-
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
5
88
PD
HCT TYPES
Propagation Delay (Figure 2)
Address to Output
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
-
-
44
-
-
-
-
-
-
-
-
-
53
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C =15pF
14
-
L
E1 to Output
E2 to Output
t
, t
PLH PHL
C = 50pF
4.5
5
34
-
43
-
51
-
L
C =15pF
14
L
t
, t
PLH PHL
C = 50pF
4.5
5
34
-
43
-
51
-
L
C =15pF
14
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
5
84
PD
NOTES:
4. C
is used to determine the dynamic power consumption, per gate.
2
PD
5. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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