CD74HCT238E
更新时间：2024-09-18 02:33:23
品牌：TI
描述：High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting
概述
数据手册
替代型号CD74HCT238E 概述
High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting 高速CMOS逻辑3至8线路解码器/多路解复用器反相和非反相 逻辑控制器
CD74HCT238E 数据手册
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PDF下载CD74HC138, CD74HCT138,
CD74HC238, CD74HCT238
Data sheet acquired from Harris Semiconductor
SCHS147A
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
October 1997 - Revised February 1999
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at V
= 5V,
CC
o
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74
HCT23
8)
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
/Sub-
ject
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
(High
Speed
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW
A0
A1
1
2
3
4
5
6
7
8
16 V
CC
15 Y0 (Y0)
14 Y1 (Y1)
13 Y2 (Y2)
12 Y3 (Y3)
11 Y4 (Y4)
10 Y5 (Y5)
A2
E1
E2
E3
(Y7) Y7
GND
9
Y6 (Y6)
Signal names in parentheses are for ’HC238 and ’HCT238.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 1999, Texas Instruments Incorporated
1
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
Ordering Information
Description
The Harris CD74HC138, CD74HC238 and CD74HCT138,
CD74HCT238 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic. Both circuits
have three binary select inputs (A0, A1 and A2). If the device
is enabled, these inputs determine which one of the eight
normally high outputs of the HC/HCT138 series will go low
or which of the normally low outputs of the HC/HCT238
series will go high.
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
CD74HCT138E
CD74HC238E
CD74HCT238E
CD74HC138M
CD74HCT138M
CD74HC238M
CD74HCT238M
CD74HC138SM
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
16 Ld PDIP
E16.3
E16.3
E16.3
16 Ld SOIC M16.15
16 Ld SOIC M16.15
16 Ld SOIC M16.15
16 Ld SOIC M16.15
16 Ld SSOP M16.209
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s 8 outputs can drive 10 low power Schottky TTL
equivalent loads.
Ordering Information
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CD74HC138E
-55 to 125
16 Ld PDIP
E16.3
Functional Diagram
HC/HCT HC/HCT
238
138
1
15
14
13
12
11
10
9
A0
A1
A2
Y0
Y0
2
3
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
7
TRUTH TABLE CD74HC138, CD74HCT138
INPUTS
ENABLE
ADDRESS
OUTPUTS
Y3 Y4
E3
X
E2
X
X
H
L
E1
H
X
X
L
A2
X
X
X
L
A1
X
X
X
L
A0
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
Y6
H
H
H
H
H
H
H
Y7
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
X
H
H
H
H
L
L
L
L
H
L
H
H
H
L
L
L
H
H
H
H
L
L
L
H
H
2
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
TRUTH TABLE CD74HC138, CD74HCT138
INPUTS
ENABLE
ADDRESS
OUTPUTS
Y3 Y4
E3
H
E2
L
E1
L
A2
H
A1
L
A0
L
Y0
H
Y1
H
Y2
H
Y5
H
L
Y6
H
H
L
Y7
H
H
H
L
H
L
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
TRUTH TABLE CD74HC238, CD74HCT238
INPUTS
ENABLE
ADDRESS
OUTPUTS
Y3 Y4
E3
X
E2
X
X
H
L
E1
A2
X
X
X
L
A1
X
X
X
L
A0
X
X
X
L
Y0
L
Y1
L
Y2
L
Y5
L
Y6
L
Y7
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
L
L
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
3
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
155
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
4
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A2
E1, E2
1.5
1.25
1
E3
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Address to Output
t
t
C = 50pF
2
-
-
-
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
PLH, PHL
L
4.5
5
-
-
-
C = 15pF
13
-
L
C = 50pF
6
26
33
38
L
5
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Enable to Output
HC/HCT138
t
t
C = 50pF
2
-
-
-
150
30
26
75
15
13
-
-
-
-
-
-
-
-
190
38
33
95
19
16
-
-
-
-
-
-
-
-
265
53
45
110
22
19
-
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
6
-
-
-
-
-
-
-
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
2
-
L
4.5
6
-
-
Power Dissipation
C
C = 15pF
L
5
67
PD
Capacitance, (Notes 5, 6)
Input Capacitance
C
-
-
-
-
10
-
10
-
10
pF
IN
HCT TYPES
Propagation Delay
Address to Output
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
-
14
-
35
-
-
-
-
44
-
-
-
-
53
-
ns
ns
ns
L
C = 15pF
L
Enable to Output
HC/HCT138
t , t
PLH PHL
C = 50pF
4.5
35
44
53
L
Enable to Output
HC/HCT238
t
t
C = 15pF
4.5
4.5
5
-
-
-
-
-
-
40
15
-
-
-
-
-
50
19
-
-
-
-
-
60
22
-
ns
ns
pF
pF
PLH, PHL
L
Output Transition Time
(Figure 2)
t
, t C = 50pF
TLH THL L
Power Dissipation
Capacitance, (Notes 5, 6)
C
C = 15pF
L
67
-
PD
Input Capacitance
NOTES:
C
-
-
10
10
10
IN
5. C
PD
is used to determine the dynamic power consumption, per gate.
2
6. P = V
CC
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
CD74HCT238E CAD模型
引脚图
封装焊盘图
CD74HCT238E 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CD74HCT238EE4 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 完全替代 |
|
| 5962-9856401QEA | TI | BCD 转 7 段解码器/驱动器 | J | 16 | -55 to 125 | 完全替代 |
|
CD74HCT238E 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CD74HCT238EE4 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 获取价格 |
|
| CD74HCT238EN | ETC | Logic IC | 获取价格 |
|
| CD74HCT238EX | RENESAS | IC,DECODER/DEMUX,3-TO-8-LINE,HCT-CMOS,DIP,16PIN,PLASTIC | 获取价格 |
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| CD74HCT238F | ETC | Logic IC | 获取价格 |
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| CD74HCT238H | ETC | 3-To-8-Line Demultiplexer | 获取价格 |
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| CD74HCT238M | TI | High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting | 获取价格 |
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| CD74HCT238M96 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 获取价格 |
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| CD74HCT238M96E4 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 获取价格 |
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| CD74HCT238M96G4 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 获取价格 |
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| CD74HCT238ME4 | TI | High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting | 获取价格 |
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