CD74HCT245M96 [TI]
High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting; 高速CMOS逻辑八路总线收发器，三态，非反相
| 型号： | CD74HCT245M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting |
| 文件： | 总12页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC245, CD74HC245,
CD54HCT245, CD74HCT245
Data sheet acquired from Harris Semiconductor
SCHS119A
High-Speed CMOS Logic Octal-Bus Transceiver,
Three-State, Non-Inverting
November 1997 - Revised May 2003
Features
Description
• Buffered Inputs
The CD54HC245, CD54HCT245, and CD74HC245,
CD74HCT245 are high-speed octal three-state bidirectional
• Three-State Outputs
• Bus Line Driving Capability
[ /Title
(CD54
HC245
,
transceivers
intended
for
two-way
asynchronous
communication between data buses. They have high drive
current outputs which enable high-speed operation while
driving large bus capacitances. They provide the low power
consumption of standard CMOS circuits with speeds and
drive capabilities comparable to that of LSTTL circuits.
• Typical Propagation Delay (A to B, B to A) 9ns at V
o
CC
= 5V, C = 15pF, T = 25 C
L
A
CD54
HCT24
5,
CD74
HC245
,
CD74
HCT24
5)
/Sub-
ject
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
The CD54HC245, CD54HCT245, CD74HC245 and
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74HCT245 allow data transmission of the B bus or from
the B bus to the A bus. The logic level at the direction input
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
(DIR) determines the direction. The output enable input
(OE), when high, puts the I/O ports in the high-impedance
state.
• Significant Power Reduction Compared to LSTTL
Logic ICs
The HC/HCT245 is similar in operation to the HC/HCT640
and the HC/HCT643.
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
TEMP.
o
CC
(High
Speed
PART NUMBER
CD54HC245F3A
CD54HCT245F3A
CD74HC245E
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC245M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
CD74HC245M96
CD74HCT245E
CD74HCT245M
CD74HCT245M96
Pinout
CD54HC245, CD54HCT245
(CERDIP)
CD74HC245, CD74HCT245
(PDIP, SOIC)
20 Ld SOIC
20 Ld SOIC
TOP VIEW
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
1
2
3
4
5
6
7
8
9
V
DIR
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12
B6
GND 10
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Functional Diagram
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
1
DIR
OE
19
TRUTH TABLE
CONTROL INPUTS
OE
L
DIR
L
OPERATION
B Data to A Bus
A Data to B Bus
Isolation
L
H
H
X
H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (Isolation) modes all I/O
terminals should be terminated with 10kΩ to 1MΩ resistors.
2
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . . θ ( C/W)
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
DC Input Diode Current, I
For V < -0.5V or V > V
69
58
IK
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
(SOIC - Lead Tips Only)
O
CC
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Three-State Leakage
Current
I
V
or V
V
=
or
6
-
-
±0.5
-
±5
-
±10
µA
OZ
IL
IH
O
V
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
6
-
-
-
-
-
-
±0.1
8
-
-
-
±1
80
±5
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
±10
CC
CC
GND
Three-State Leakage
Current
I
V
or V
V =
O
±0.5
OZ
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
An or Bn
0.4
1.5
0.9
OE
DIR
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
4
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Data to Output
t
, t
PHL PLH
C
= 50pF
L
2
-
-
-
110
22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
165
33
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
9
-
L
L
L
6
-
19
150
30
-
24
190
38
-
28
225
45
-
Output Disable to Output
Output Enable to Output
t
t
t
2
-
-
PHL, PLH
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
12
-
L
L
L
6
-
26
150
30
-
33
190
38
-
38
225
45
-
t
2
-
-
PHL, PLH
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
12
-
L
L
L
6
-
26
60
12
10
10
20
33
75
15
13
10
20
38
90
18
15
10
20
Output Transition Time
Input Capacitance
t
, t
THL TLH
2
-
-
4.5
6
-
-
-
-
C
C
= 50pF
-
-
10
-
-
IN
L
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
53
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay
Data to Output
t
t
t
t
C
C
C
C
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 50pF
-
4.5
5
-
-
-
10
-
26
-
-
-
-
-
-
-
-
-
-
33
-
-
-
-
-
-
-
-
-
-
39
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PHL, PLH
L
L
L
L
L
L
L
L
Output Disable to Output
Output Enable to Output
t
4.5
5
-
30
-
38
-
45
-
PHL, PLH
-
12
-
t
4.5
5
-
32
-
40
-
48
-
PHL, PLH
-
13
-
Output Transition Time
Input Capacitance
t
, t
THL TLH
4.5
-
-
12
10
20
15
10
20
18
10
20
C
10
-
-
IN
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
55
-
-
-
-
-
pF
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per channel.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
5
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
PZL
t
PZL
t
t
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
CD54HC245F
CD54HC245F3A
CD54HCT245F
CD54HCT245F3A
CD74HC245E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
20
20
20
20
20
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
1
J
1
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC245EE4
CD74HC245M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
N
20
20
20
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC245M96
CD74HC245M96E4
CD74HC245ME4
CD74HCT245E
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT245EE4
CD74HCT245M
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT245M96
CD74HCT245M96E4
CD74HCT245ME4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
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Addendum-Page 2
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相关型号：
CD74HCT251E96
HCT SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16
RENESAS
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