CD74HCT297 [TI]
High-Speed CMOS Logic Digital Phase-Locked-Loop; 高速CMOS逻辑数字锁相环回路
| 型号： | CD74HCT297 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Digital Phase-Locked-Loop |
| 文件： | 总11页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC297,
CD74HCT297
Data sheet acquired from Harris Semiconductor
SCHS177
High-Speed CMOS Logic
Digital Phase-Locked-Loop
November 1997
Features
Description
• Digital Design Avoids Analog Compensation Errors
• Easily Cascadable for Higher Order Loops
The Harris CD74HC297 and CD74HCT297 are high-speed
silicon gate CMOS devices that are pin-compatible with low
power Schottky TTL (LSTTL).
[ /Title
(CD74
HC297
,
CD74
HCT29
7)
• Useful Frequency Range
These devices are designed to provide a simple, cost-effec-
tive solution to high-accuracy, digital, phase-locked-loop appli-
cations. They contain all the necessary circuits, with the
exception of the divide-by-N counter, to build first-order
phase-locked-loops.
- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)
• Dynamically Variable Bandwidth
• Very Narrow Bandwidth Attainable
• Power-On Reset
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
have a 50% duty factor to obtain the maximum lock-range.
/Sub-
ject
• Output Capability
- Standard. . . . . . . . . . . . . . . . . . . . XORPD
, ECPD
OUT
OUT
OUT
(High-
Speed
CMOS
Logic
Digi-
tal
Proper partitioning of the loop function, with many of the build-
ing blocks external to the package, makes it easy for the
designer to incorporate ripple cancellation (see Figure 2) or to
cascade to higher order phase-locked-loops.
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The length of the up/down K-counter is digitally programmable
according to the K-counter function table. With A, B, C and D
all LOW, the K-counter is disabled. With A HIGH and B, C and
D LOW, the K-counter is only three stages long, which widens
the bandwidth or capture range and shortens the lock time of
the loop. When A, B, C and D are all programmed HIGH, the
K-counter becomes seventeen stages long, which narrows
the bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A to
D inputs can maximize the overall performance of the digital
phase-locked-loop.
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Phase-
Locked
• CD74HC297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V
- High Noise ImmunityN = 30%, N = 30% of V at 5V
IL IH CC
• CD74HCT297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility
The CD74HC297 and CD74HCT297 can perform the classic
first order phase-locked-loop function without using analog
components. The accuracy of the digital phase-locked-loop
V
= 0.8V (Max), V = 2V (Min)
IH
IL
- CMOS Input Compatibility I ≤ 1µA at V , V
OL OH
I
(DPLL) is not affected by V
depends solely on accuracies of the K-clock and loop propa-
gation delays.
and temperature variations but
CC
Ordering Information
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
CD74HC297E
CD74HCT297E
NOTES:
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
E16.3
E16.3
Pinout
CD74HC297, CD74HCT297 (PDIP)
TOP VIEW
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
B
A
1
2
3
4
5
6
7
8
16 V
15 C
14 D
CC
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
EN
CTR
K
13 φA
2
CP
I/D
12 ECPD
OUT
CP
D/U
11 XORPD
OUT
10 φB
I/D
OUT
9
φA
1
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1852.1
Copyright © Harris Corporation 1997
1
CD74HC297, CD74HCT297
The phase detector generates an error signal waveform that,
Functional Diagram
at zero phase error, is a 50% duty factor square wave. At the
limits of linear operation, the phase detector output will be
either HIGH or LOW all of the time depending on the direction
of the phase error (φIN - φOUT). Within these limits the phase
detector output varies linearly with the input phase error
D
C
B
A
14 15
1
2
4
6
3
CARRY
K
CP
7
BORROW
MODULO-K
COUNTER
I/D
D/U
CTR
OUT
I/D
according to the gain K , which is expressed in terms of
d
CKT
EN
phase detector output per cycle or phase error. The phase
detector output can be defined to vary between ±1 according
to the relation:
5
9
I/D
CP
φA
11
12
1
XORPD
OUT
%HIGH - %LOW
--------------------------------------------
phase detector output =
10
13
100
J
Q
φB
ECPD
OUT
F/F
K
φA
The output of the phase detector will be K φ , where the
d e
2
phase error φ = φIN - φOUT.
e
FUNCTION TABLE
EXCLUSIVE-OR PHASE DETECTOR
EXCLUSIVE-OR phase detectors (XORPD) and edge-con-
trolled phase detectors (ECPD) are commonly used digital
types. The ECPD is more complex than the XORPD logic
function but can be described generally as a circuit that
changes states on one of the transitions of its inputs. The gain
φA
φB
L
XORPD OUT
1
L
L
L
H
H
L
H
L
(K ) for an XORPD is 4 because its output remains HIGH
d
H
H
(XORPD
= 1) for a phase error of one quarter cycle.
OUT
H
Similarly, K for the ECPD is 2 since its output remains HIGH
d
for a phase error of one half cycle. The type of phase detector
will determine the zero-phase-error point, i.e., the phase sep-
aration of the phase detector inputs for a φe defined to be
zero. For the basic DPLL system of Figure 3, φe = 0 when the
phase detector output is a square wave.
FUNCTION TABLE
EDGE-CONTROLLED PHASE DETECTOR
φA
φB
ECPD OUT
2
↓
H or L
H
↓
H or L
↑
L
The XORPD inputs are one quarter cycle out-of-phase for
zero phase error. For the ECPD, φe = 0 when the inputs are
one half cycle out of phase.
H or L
No Change
No Change
↑
H or L
The phase detector output controls the up/down input to the
H = Steady-State High Level, L = Steady-State Low Level, ↑ = LOW
K-counter. The counter is clocked by input frequency Mf
↓
to HIGH φ Transition, = HIGH to LOW φ Transition
c
which is a multiple M of the loop center frequency f . When
c
K-COUNTER FUNCTION TABLE
(DIGITAL CONTROL)
the K-counter recycles up, it generates a carry pulse. Recy-
cling while counting down generates a borrow pulse. If the
carry and the borrow outputs are conceptually combined into
one output that is positive for a carry and negative for a bor-
row, and if the K-counter is considered as a frequency divider
MODULO
(K)
D
L
C
L
B
L
A
L
Inhibited
with the ratio Mf /K, the output of the K-counter will equal the
c
3
L
L
L
H
L
2
input frequency multiplied by the division ratio. Thus the out-
4
L
L
H
H
L
2
put from the K-counter is (K φ Mf )/K.
d e
c
5
L
L
H
L
2
The carry and borrow pulses go to the increment/decrement
(I/D) circuit which, in the absence of any carry or borrow
6
L
H
H
H
H
L
2
pulses has an output that is one half of the input clock (I/D ).
7
CP
L
L
H
L
2
The input clock is just a multiple, 2N, of the loop center fre-
quency. In response to a carry of borrow pulse, the I/D circuit
8
L
H
H
L
2
9
will either add or delete a pulse at I/D
. Thus the output of
L
H
L
2
OUT
the I/D circuit will be Nf + (K φ Mf )/2K.
d e
10
2
c
c
H
H
H
H
H
H
H
H
The output of the N-counter (or the output of the phase-
locked-loop) is thus: f = f + (K φ Mf )/2KN.
11
2
L
L
H
L
o
c
d e
c
12
2
L
H
H
L
If this result is compared to the equation for a first-order ana-
log phase-locked-loop, the digital equivalent of the gain of the
13
2
L
H
L
14
2
H
H
H
H
VCO is just Mf /2KN or f /K for M = 2N.
c
c
15
2
L
H
L
Thus, the simple first-order phase-locked-loop with an adjust-
able K-counter is the equivalent of an analog phase-locked-
loop with a programmable VCO gain.
16
2
H
H
17
2
H
2
CD74HC297, CD74HCT297
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
-
-
-
-
1.9
4.4
5.9
3.84
-
-
-
-
1.9
4.4
5.9
3.7
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
4.5
(Note 4)
TTL Loads
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
(Note 4)
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
2
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
0.1
0.1
-
-
-
-
0.1
0.1
0.1
0.4
V
V
V
V
OL
IH
IL
4.5
6
0.1
0.1
Low Level Output
Voltage
4
4.5
0.26
0.33
(Note 4)
TTL Loads
5.2
6
-
-
0.26
-
0.33
-
0.4
V
(Note 4)
3
CD74HC297, CD74HCT297
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Leakage
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Current
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 3)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
5. XORPD, ECPD
HCT Input Loading Table
INPUT
EN , D/U
UNIT LOADS
0.3
0.6
1.5
CTR
A, B, C, D, K , φA
CP
2
I/D , φA , φB
CP
1
NOTE: Unit Load is ∆I
limit specified in DC Electrical
CC
Specifications table, e.g., 360µA max at 25 C.
o
4
CD74HC297, CD74HCT297
Prerequisite For Switching Function
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
Maximum Clock Frequency
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
f
2
6
30
35
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
24
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
ns
MAX
MAX
K
CP
4.5
6
2
Maximum Clock Frequency
I/D
f
CP
4.5
6
20
24
80
16
14
125
25
21
100
20
17
0
16
19
100
20
17
155
31
26
125
25
21
0
13
15
120
24
20
190
38
32
150
30
26
0
Clock Pulse Width
t
2
w
K
CP
4.5
6
ns
ns
Clock Pulse Width
I/D
t
2
ns
W
CP
4.5
6
ns
ns
Set-up Time
D/U, EN
t
2
ns
SU
to K
to K
CTR
CP
CP
4.5
6
ns
ns
Hold Time
D/U, EN
t
2
ns
H
CTR
4.5
6
0
0
0
ns
0
0
0
ns
HCT TYPES
Maximum Clock Frequency
f
f
4.5
4.5
4.5
4.5
4.5
4.5
30
20
16
25
20
0
-
-
-
-
-
-
24
16
20
31
25
0
-
-
-
-
-
-
20
13
24
38
30
0
-
-
-
-
-
-
MHz
MHz
ns
MAX
K
CP
Maximum Clock Frequency
I/D
MAX
CP
Clock Pulse Width
t
t
w
K
CP
Clock Pulse Width
I/D
ns
w
CP
Set-up Time
D/U, EN
t
ns
SU
to K
to K
CTR
Hold Time
D/U, EN
CP
CP
t
ns
H
CTR
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
HC TYPES
Propagation Delay,
I/D to I/D
t
, t
C = 50pF
2
-
-
-
175
35
220
44
265
53
ns
ns
ns
PLH PHL
L
CP OUT
4.5
6
30
34
43
5
CD74HC297, CD74HCT297
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
150
30
MAX
190
38
MAX
225
45
UNITS
ns
CC
Propagation Delay,
t , t
PLH PHL
C = 50pF
2
-
-
-
-
-
-
-
-
-
-
-
-
-
L
φA , φB to XORPD
1
OUT
4.5
ns
6
2
26
33
38
ns
Propagation Delay,
t , t
PHL PHL
C = 50pF
200
40
250
50
300
60
ns
L
φB, φA to ECPD
OUT
2
4.5
6
ns
34
43
51
ns
Output Transition Time
XORPD
t
C = 50pF
2
75
95
110
22
ns
TLH
TLH
L
OUT
4.5
6
15
19
ns
ECPD
OUT
13
16
19
ns
Output Transition Time
I/D
t
C = 50pF
L
2
60
75
90
ns
OUT
4.5
6
12
15
18
ns
10
13
15
ns
Input Capacitance
C
-
-
10
10
10
pF
I
HCT TYPES
Propagation Delay,
I/D to I/D
CP OUT
t
t
t
, t
C = 50pF
4.5
4.5
4.5
4.5
4.5
-
-
-
-
-
-
-
35
30
40
15
12
10
44
38
50
19
15
10
53
45
60
22
18
10
ns
ns
ns
ns
ns
pF
PLH PHL
L
Propagation Delay,
, t
PLH PHL
C = 50pF
L
φA , φB to XORPD
1
OUT
Propagation Delay,
, t
PHL PHL
C = 50pF
L
φB, φA to ECPD
OUT
2
Output Transition Time
XORPD
t
C = 50pF
L
TLH
TLH
OUT
Output Transition Time
ECPD
t
C = 50pF
L
OUT
Input Capacitance
C
-
I
6
CD74HC297, CD74HCT297
Logic Diagram
MODULO-K COUNTER
2
A
1
2
4
8
1
B
CONTROL CIRCUIT
14 13 12 11 10
15
C
14
D
9
8
7
6
5
4
3
2
1
0
TO MODE CONTROLS 12-2
(11 STAGES NOT SHOWN)
4
K
CP
6
D/U
R
R
R
R
D
R
R
D
D
D
D
D
D
D
T
D
T
D
T
Q
Q
Q
FF14
Q
CP
FF
Q
T
T
T
T
FF
FF
FF1
T
FF13
FF
M
M
Q
Q
M
3
EN
CTR
D
Q
Q
M
M
T
M
T
Q
FF14
Q
FF1
FF
CP
T
FF
Q
FF
T
FF
Q
FF13
Q
D
D
R
D
R
R
D
R
D
R
R
D
D
D
D
POWER ON RESET
1 = 1
1
BORROW
CARRY
INCREMENT/DECREMENT CIRCUIT
5
I/D
CP
7
I/D
OUT
D
Q
D
D
Q
Q
D
CP
CP
CP
FF
Q
CP
FF
Q
FF
FF
Q
Q
J
FF
CP
K
Q
D
Q
D
D
Q
D
Q
CP
CP
CP
FF
Q
CP
FF
FF
Q
FF
Q
9
φA
1
EXCLUSIVE-OR PHASE DETECTOR
11
XORPD
OUT
10
φB
EDGE-CONTROLLED PHASE DETECTOR
12
S
S
D
D
ECPD
OUT
Q
Q
FF
FF
Q
Q
R
R
D
D
13
φA
2
7
CD74HC297, CD74HCT297
K
CARRY
CP
Mf
C
D/U
CTR
DIVIDE-BY-K
COUNTER
EN
BORROW
XORPD
OUT
φA
1
φB
I/D
f
CP
OUT
2Nf
I/D CIRCUIT
C
φOUT
ECPD
OUT
J
J
ECPD
φA
2
f
IN
K
I/D
φIN
OUT
FF
DIVIDE-BY-N
COUNTER
FIGURE 1. DPLL USING BOTH PHASE DETECTORS IN A RIPPLE-CANCELLATION SCHEME
K
CARRY
CP
Mf
C
DIVIDE-BY-K
COUNTER
D/U
BORROW
XORPD
OUT
φA
f
1
OUT
φIN
φB
I/D
CP
2Nf
I/D CIRCUIT
C
I/D
OUT
f
DIVIDE-BY-N
COUNTER
OUT
φOUT
FIGURE 2. DPLL USING EXCLUSIVE-OR PHASE DETECTION
CARRY PULSE
(INTERNAL SIGNAL)
BORROW PULSE
(INTERNAL SIGNAL)
I/D
CP
INPUT
I/D
OUTPUT
OUT
FIGURE 3. TIMING DIAGRAM: I/D
IN-LOCK CONDITION
OUT
8
CD74HC297, CD74HCT297
øB INPUT
øA INPUT
2
ECPD
OUTPUT
OUT
FIGURE 4. TIMING DIAGRAM: EDGE CONTROLLED PHASE COMPARATOR WAVEFORMS
øB INPUT
øA INPUT
1
XORPD
OUT
OUTPUT
FIGURE 5. TIMING DIAGRAM: EXCLUSIVE OR PHASE DETECTOR WAVEFORMS
I/f
MAX
t
W
I/D
V
CP
S
t
PHL
t
PLH
V
I/D
OUT
S
t
t
THL
TLH
FIGURE 6. WAVEFORMS SHOWING THE CLOCK (I/D ) TO OUTPUT (I/D
CP
) PROPAGATION DELAYS, CLOCK PULSE WIDTH,
OUT
OUTPUT TRANSITION TIMES AND MAXIMUM CLOCK PULSE FREQUENCY
V
S
øB INPUT
V
S
øA INPUT
1
t
TLH
XORPD
OUT
V
S
OUTPUT
t
PLH
t
PLH
t
t
t
PLH
THL
PHL
FIGURE 7. WAVEFORMS SHOWING THE PHASE INPUT (øB, øA ) TO OUTPUT (XORPD
1
) PROPAGATION DELAYS AND
OUT
OUTPUT TRANSITION TIMES
9
CD74HC297, CD74HCT297
V
S
øB INPUT
øA INPUT
2
V
S
ECPD
OUT
OUTPUT
V
S
t
t
t
TLH
PHL
PLH
t
THL
FIGURE 8. WAVEFORMS SHOWING THE PHASE INPUT (øB, øA ) TO OUTPUT (ECPD
2
) PROPAGATION DELAYS AND OUTPUT
OUT
TRANSITION TIMES
t
t
H
H
D/U, EN
CTR
V
S
INPUT
t
t
SU
SU
V
S
K
INPUT
CP
t
W
1/f
MAX
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
FIGURE 9. WAVEFORMS SHOWING THE CLOCK (K ) PULSE WIDTH AND MAXIMUM CLOCK PULSE FREQUENCY, AND THE
CP
INPUT (D/U, EN
CTR
) TO CLOCK (K ) SETUP AND HOLD TIMES
CP
10
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明