CD74HCT299M96 [TI]
High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State; 高速CMOS逻辑8位通用移位寄存器;三态
| 型号： | CD74HCT299M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State |
| 文件： | 总13页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
Data sheet acquired from Harris Semiconductor
SCHS178C
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
January 1998 - Revised May 2003
Features
Description
The ’HC259 and ’HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
• Buffered Inputs
• Four Operating Modes: Shift Left, Shift Right, Load
and Store
[ /Title
(CD74
HC299
,
CD74
HCT29
9)
select, the serial data (DS0, DS7) and the parallel data (I/O
0
• Can be Cascaded for N-Bit Word Lengths
- I/O ) respond only to the low-to-high transition of the clock
7
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
• I/O - I/O Bus Drive Capability and Three-State for
0
7
Bus Oriented Applications
o
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
• Typical f = 50MHz at V
= 5V, C = 15pF, T = 25 C
MAX CC
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
/Sub-
ject
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
(High
Speed
CMOS
Logic
8-Bit
Uni-
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
• Significant Power Reduction Compared to LSTTL
Logic ICs
The three-state input/output I(/O) port has three modes of
operation:
• HC Types
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
- 2V to 6V Operation
versal
Shift
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
Ordering Information
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
o
PART NUMBER
CD54HC299F3A
CD54HCT299F3A
CD74HC299E
TEMP. RANGE ( C)
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
TOP VIEW
-55 to 125
1
2
3
4
5
6
7
8
9
V
S0
OE1
OE2
20
19
CC
-55 to 125
S1
CD74HC299M
-55 to 125
18 DS7
17 Q7
CD74HC299M96
CD74HCT299E
CD74HCT299M
CD74HCT299M96
-55 to 125
I/O
6
I/O
4
16 I/O
7
-55 to 125
I/O
2
15 I/O
5
-55 to 125
I/O
0
14 I/O
3
-55 to 125
Q0
13 I/O
12
1
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
MR
CP
GND 10
11 DS0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Functional Diagram
CP OE1 OE2 MR
12
2
3
9
20
THREE-
STATE
V
CC
CONTROL
7
6
5
4
8
1
13
I/O
14
I/O
15
I/O
I/O
I/O
I/O
I/O
0
2
4
1
3
5
7
I/O
I/O
SHIFT
REGISTER
THREE-STATE
OUTPUTS
THREE-STATE
OUTPUTS
BUS LINE
OUTPUTS
BUS LINE
OUTPUTS
16
I/O
6
17
Q7
19
S1
STANDARD
OUTPUT
STANDARD
OUTPUT
Q0
S0
MODE SELECTION
10
GND
11
18
DS0 DS7
MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE
INPUTS
INPUTS/OUTPUTS
FUNCTION
Read Register
OE1
L
OE2
S0
S1
X
X
L
Qn (REGISTER)
I/O0 --- I/O7
L
L
L
L
L
H
H
L
L
L
L
X
L
L
L
L
X
X
H
X
H
X
X
L
H
H
I/On = Inputs
(Z)
Load Register
Disable I/O
X
H
X
X
Qn = I/On
H
X
X
X
(Z)
TRUTH TABLE
INPUTS
REGISTER OUTPUTS
FUNCTION
RESET (CLEAR)
Shift Right
MR
CP
X
↑
S0
X
h
h
l
S1
X
l
DS0
X
DS7
X
I/On
X
Q0
L
Q1
L
---
---
---
---
---
---
---
---
---
Q6
L
Q7
L
L
H
H
H
H
H
H
H
l
X
X
L
q
q
q
q
q
q
q
q
6
0
5
5
7
7
6
↑
l
h
X
X
H
Q6
L
0
Shift Left
↑
h
h
l
X
l
X
q
q
q
q2
1
1
0
↑
l
X
h
X
q
q
H
2
1
Hold (Do Nothing)
Parallel Load
↑
l
X
X
X
q
7
↑
h
h
h
h
X
X
l
L
L
L
L
↑
X
X
h
H
H
H
H
H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage
low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock
transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, ↑ = Low to High Clock Transition.
2
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I For -0.5V < V < V
For Q Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
For I/O Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
+ 0.5V
O,
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
Qn
-4
I/On
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
-7.8
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
0.02
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
Qn
4
I/On
6
-
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
7.8
Input Leakage
Current
I
V
or
-
6
I
CC
GND
3
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three- State Leak-
age Current
V
or V
V
=V
CC
-
6
-
-
±0.5
-
±5
-
±10
µA
IL
IH
O
or GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
6
-
-
-
-
±0.1
8
-
-
-
-
±1
80
-
-
-
-
±1
µA
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
490
CC
CC
GND
Three- State Leak-
age Current
V
or V
V
=V
±0.5
360
±5
IL
IH
O
CC
or GND
Additional Quies-
cent Device Cur-
rent Per
∆I
CC
(Note 2)
V
-
4.5 to
5.5
100
450
CC
-2.1
Input Pin: 1 Unit
Load
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
S1, MR
0.25
0.25
0.25
0.6
I/O - I/O
0
7
DS0, DS7
S0, CP
OE1, OE2
0.3
NOTE: Unit Load is ∆I
e.g., 360µA max. at 25 C.
limit specific in Static Specifications Table,
CC
o
4
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Maximum Clock
Frequency
f
MAX
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
65
13
11
100
20
17
125
25
21
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
75
15
13
120
24
20
150
30
26
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
4.5
6
30
35
50
10
9
MR Pulse Width
t
t
2
W
W
4.5
6
ns
ns
Clock Pulse Width
2
80
16
14
100
20
17
0
ns
4.5
6
ns
ns
Setup Time
DS0, DS7, I/On to Clock
t
2
ns
SU
4.5
6
ns
ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
t
2
ns
H
4.5
6
0
0
0
ns
0
0
0
ns
Recovery Time
MR to Clock
t
REC
2
5
5
5
ns
4.5
6
5
5
5
ns
5
5
5
ns
Setup Time
S1, S0 to Clock
t
2
120
24
20
150
30
26
180
36
31
ns
SU
4.5
6
ns
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
25
-
-
20
-
-
16
-
-
MHz
MR Pulse Width
t
t
4.5
4.5
4.5
15
20
20
-
-
-
-
-
-
19
25
25
-
-
-
-
-
-
22
30
30
-
-
-
-
-
-
ns
ns
ns
W
W
Clock Pulse Width
Setup Time DS0, DS7,
I/On, S0, S1 to Clock
t
SU
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
t
4.5
4.5
4.5
0
5
-
-
-
-
-
-
0
5
-
-
-
-
-
-
0
5
-
-
-
-
-
-
ns
ns
ns
H
Recovery Time MR to
Clock
t
REC
Setup Time S1, S0 to
Clock
t
27
34
41
SU
5
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
, t
C
= 50pF
PLH PHL
L
Clock to I/O Output,
Clock to Q0 and Q7,
MR to Output
2
-
-
-
200
40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
250
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
60
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 15pF
17
-
L
L
L
6
34
-
43
-
51
-
Output Enable and Disable
Times
t
5
10
13
15
-
PZL
t
, t
-
-
-
PZH PLZ
t
-
-
-
PHZ
Output High-Z to High Level
Output High Level to High-Z
Output Low Level to High-Z
Output High-Z to Low Level
t
C
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
= 50pF
2
4.5
6
155
31
26
185
37
31
155
31
26
130
26
22
195
39
33
230
46
39
195
39
33
165
33
28
235
47
40
280
56
48
235
47
40
195
39
33
PZH
PHZ
L
L
L
L
L
-
-
t
2
-
4.5
6
-
-
t
2
-
PLZ
PZL
4.5
6
-
-
t
2
-
4.5
6
-
-
Output Transition Time
Q0, Q7
t
, t
THL TLH
2
4.5
6
-
-
-
-
-
-
-
-
-
-
75
15
13
60
12
10
10
20
-
-
-
-
-
-
-
-
95
19
16
75
15
13
10
20
-
-
-
-
-
-
-
-
110
22
19
90
18
15
10
20
ns
ns
ns
ns
ns
ns
pF
pF
-
I/O to I/O
t
, t
THL TLH
C
= 50pF
2
-
0
7
L
4.5
6
-
-
Input Capacitance
C
C
C
= 50pF
-
-
10
20
I
L
Three-State Output
Capacitance
C
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
= 15pF
5
-
150
-
-
-
-
-
pF
PD
L
6
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HCT TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
t
PHL, PLH
Clock to I/O Output,
Clock to Q0 and Q7
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
4.5
5
-
-
-
-
-
19
-
45
-
-
56
-
-
-
-
68
-
ns
ns
ns
ns
L
L
L
L
-
-
-
-
58
-
MR to Output
t
t
4.5
5
46
-
69
-
PHL, PLH
Output Enable and Disable
Times
t
,t
,
10,
13, 15
PZL PZH
, t
t
PLZ PHZ
Output High-Z to High Level
Output High Level to High-Z
Output Low Level to High-Z
Output High-Z to Low Level
t
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
4.5
4.5
4.5
4.5
-
-
-
-
-
-
-
-
32
37
32
30
-
-
-
-
40
46
40
38
-
-
-
-
48
56
48
45
ns
ns
ns
ns
PZH
PHZ
L
L
L
L
t
t
PLZ
t
PZL
Output Transition Time
Q0, Q7
t
, t
TLH THL
C
C
C
= 50pF
= 50pF
= 50pF
-
4.5
4.5
-
-
-
-
-
-
15
12
10
20
-
-
-
-
19
15
10
20
-
-
-
-
22
18
10
20
ns
ns
pF
pF
L
L
L
I/O to I/O
-
0
7
Input Capacitance
C
10
20
IN
Three-State Output
Capacitance
C
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
C
= 15pF
5
-
170
-
-
-
-
-
pF
PD
L
NOTES:
3. C
is used to determine the dynamic power consumption, per register.
PD
2
2
4. P = C
V
f + ∑ (C V
f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance,
D
PD CC
i
L
CC
O
i
O
L
V
= Supply Voltage.
CC
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Test Circuits and Waveforms (Continued)
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
9
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