CD74HCT40103 [TI]
High Speed CMOS Logic 8-Stage Synchronous Down Counters; 高速CMOS逻辑8级同步减计数器
| 型号： | CD74HCT40103 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 8-Stage Synchronous Down Counters |
| 文件： | 总9页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC40103,
CD74HCT40103
Data sheet acquired from Harris Semiconductor
SCHS221
High Speed CMOS Logic
November 1997
8-Stage Synchronous Down Counters
Features
Description
• Synchronous or Asynchronous Preset
• Cascadable in Synchronous or Ripple Mode
The Harris CD74HC40103 and CD74HCT40103 are
manufactured with high speed silicon gate technology and
consist of an 8-stage synchronous down counter with a
single output which is active when the internal count is zero.
The 40103 contains a single 8-bit binary counter. Each has
control inputs for enabling or disabling the clock, for clearing
the counter to its maximum count, and for presetting the
[ /Title
(CD74H
C40103,
CD74H
CT4010
3)
/Sub-
ject
(High
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C counter either synchronously or asynchronously. All control
inputs and the TC output are active-low logic.
• Balanced Propagation Delay and Transition Times
In normal operation, the counter is decremented by one
• Significant Power Reduction Compared to LSTTL
count on each positive transition of the CLOCK (CP).
Logic ICs
Counting is inhibited when the TE input is high. The TC
output goes low when the count reaches zero if the TE input
is low, and remains low for one full clock period.
• HC Types
Speed
CMOS
Logic 8-
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
When the PE input is low, data at the P0-P7 inputs are
clocked into the counter on the next positive clock transition
regardless of the state of the TE input. When the PL input is
low, data at the P0-P7 inputs are asynchronously forced into
the counter regardless of the state of the PE, TE, or CLOCK
inputs. Input P0-P7 represent a single 8-bit binary word for
the 40103. When the MR input is low, the counter is
IL
IH
CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
asynchronously cleared to its maximum count of 255 ,
l
OL OH
10
regardless of the state of any other input. The precedence
relationship between control inputs is indicated in the truth
table.
Ordering Information
PKG.
NO.
o
If all control inputs except TE are high at the time of zero
count, the counters will jump to the maximum count, giving a
counting sequence of 100 or 256 clock pulses long.
PART NUMBER TEMP. RANGE ( C) PACKAGE
CD74HC40103E
CD74HCT40103E
CD74HC40103M
CD74HCT40103M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP E16.3
16 Ld PDIP E16.3
16 Ld SOIC M16.15
16 Ld SOIC M16.15
The 40103 may be cascaded using the TE input and the TC
output, in either a synchronous or ripple mode. These
circuits possess the the low power consumption usually
associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL circuits and can drive
up to 10 LSTTL loads.
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1596.1
Copyright © Harris Corporation 1997
1
CD74HC40103, CD74HCT40103
Pinout
CD74HC40103, CD74HCT40103
(PDIP, SOIC)
TOP VIEW
CP
MR
TE
1
2
3
4
5
6
7
8
16 V
CC
15 PE (SYNC)
14 TC
P0
13 P7
P1
12 P6
P2
11 P5
10 P4
P3
9
PL (ASYNC)
GND
Functional Diagram
14
P7
P6
P5
P4
P3
P2
13
12
11
10
7
6
P1
P0
5
4
15
9
3
1
2
16
8
TRUTH TABLE
CONTROL INPUTS
MR
PL
1
PE
1
TE
1
PRESET MODE
ACTION
1
Synchronous
Inhibit Counter
Count Down
1
1
1
0
1
1
0
X
X
X
Preset On Next Positive Clock Transition
Preset Asychronously
1
0
0
X
X
Asynchronously
X
Clear to Maximum Count
NOTE:
1 = High Level.
0 = Low Level.
X = Don’t Care.
Clock connected to clock input.
Synchronous Operation: changes occur on negative-to-positive clock transitions.
Load Inputs: MSB = P7, LSB = P0.
2
CD74HC40103, CD74HCT40103
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC40103, CD74HCT40103
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS (NOTE)
P0-P7
0.20
TE, MR
0.40
CP
0.60
PE
PL
0.80
1.35
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
TYP
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
CP Pulse Width
t
2
165
33
-
-
-
-
-
-
-
-
-
-
-
-
205
41
-
-
-
-
-
-
250
50
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
W
W
4.5
6
2
28
35
43
PL Pulse Width
t
125
25
155
31
190
38
4.5
6
21
26
32
4
CD74HC40103, CD74HCT40103
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
MR Pulse Width
SYMBOL
V
(V)
MIN
125
25
21
3
TYP
MAX
MIN
135
31
26
2
MAX
MIN
190
38
32
2
MAX
UNITS
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
4.5
ns
6
2
ns
CP Max. Frequency
(Note 4)
f
CP(MAX)
MHz
MHz
MHz
ns
4.5
6
15
18
100
20
17
75
15
13
150
30
26
5
12
14
125
25
21
95
19
16
190
38
33
5
10
12
150
30
26
110
22
19
225
45
38
5
P to CP Set-up Time
PE to CP Set-up Time
TE to CP Set-up Time
P to CP Hold Time
t
t
t
2
SU
SU
SU
4.5
6
ns
ns
2
ns
4.5
6
ns
ns
2
ns
4.5
6
ns
ns
t
t
2
ns
H
4.5
6
5
5
5
ns
5
5
5
ns
TE to CP Hold Time
MR to CP Removal Time
PE to CP Hold Time
2
0
0
0
ns
H
4.5
6
0
0
0
ns
0
0
0
ns
t
2
50
10
9
65
13
11
2
75
15
13
2
ns
REM
4.5
6
ns
ns
t
2
2
ns
H
4.5
6
2
2
2
ns
2
2
2
ns
HCT TYPES
CP Pulse Width
PL Pulse Width
MR Pulse Width
t
t
t
4.5
4.5
4.5
4.5
35
43
35
14
-
-
-
-
-
-
-
-
44
54
44
11
-
-
-
-
53
65
53
9
-
-
-
-
ns
ns
W
W
W
ns
CP Max. Frequency
(Note 4)
f
CP(MAX)
MHz
P to CP Set-up Time
PE to CP Set-up Time
TE to CP Set-up Time
P to CP Hold Time
t
t
t
4.5
4.5
4.5
4.5
4.5
4.5
4.5
24
20
40
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
25
50
5
-
-
-
-
-
-
-
36
30
60
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SU
SU
SU
t
H
H
TE to CP Hold Time
MR to CP Removal Time
PE to CP Hold Time
t
0
0
0
t
10
2
13
2
15
2
REM
tH
5
CD74HC40103, CD74HCT40103
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
Propagation Delay
t
t
t
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
375
75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
450
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
MHz
pF
PLH,
L
t
PHL
CP to any TC (Async Preset)
C = 50pF
L
C = 15pF
25
-
L
C = 50pF
6
51
300
60
-
64
375
75
-
77
450
90
-
L
CP to TC (Sync Preset)
C = 50pF
2
-
PLH,
L
t
PHL
C = 50pF
4.5
5
-
L
C = 15pF
25
-
L
C = 50pF
6
51
200
40
-
64
250
50
-
77
300
60
-
L
TE to TC
C = 50pF
2
-
PLH,
L
t
PHL
C = 50pF
4.5
5
-
L
C = 15pF
17
-
L
C = 50pF
6
34
275
55
-
43
345
69
-
51
415
83
-
L
PL to TC
C = 50pF
2
-
PLH,
L
t
PHL
C = 50pF
4.5
5
-
L
C = 15pF
23
-
L
C = 50pF
6
47
275
55
-
59
345
69
-
71
415
83
-
L
MR to TC
C = 50pF
2
-
PLH,
L
t
PHL
C = 50pF
4.5
5
-
L
C = 15pF
23
-
L
C = 50pF
6
47
75
15
13
10
-
59
95
19
16
10
-
71
110
22
19
10
-
L
Output Transition Time
t
, t
C = 50pF
2
-
TLH THL
L
C = 50pF
4.5
6
-
L
C = 50pF
-
L
Input Capacitance
C
C = 50pF
-
-
I
L
CP Maximum Frequency
f
C = 15pF
L
5
25
25
MAX
Power Dissipation Capacitance
(Notes 5, 6)
C
-
5
-
-
-
PD
HCT TYPES
Propagation Delay
CP to TC (Async Preset)
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
25
-
60
-
-
-
-
-
-
-
-
-
75
-
-
-
-
-
-
-
-
-
90
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH,
L
PHL
C = 15pF
L
CE to TC (Sync Preset)
TE to TC
t
t
t
C = 50pF
4.5
5
63
-
79
-
95
-
PLH,
L
t
PHL
C = 15pF
26
-
L
C = 50pF
4.5
5
50
-
63
-
75
-
PLH,
L
t
PHL
C = 15pF
21
-
L
PL to TC
C = 50pF
4.5
5
68
-
85
-
102
-
PLH,
L
t
PHL
C = 15pF
28
L
6
CD74HC40103, CD74HCT40103
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
MR to TC
MIN TYP MAX MIN
MAX
69
MIN
MAX UNITS
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
-
23
-
55
-
-
-
-
-
-
-
-
-
-
-
-
-
83
-
ns
ns
PLH,
L
PHL
C = 15pF
-
19
10
-
L
Output Transition Time
Input Capacitance
t
, t
C = 50pF
4.5
-
15
10
-
22
10
-
ns
THL TLH
L
C
C = 50pF
-
pF
IN
L
CP Maximum Frequency
f
C = 15pF
L
5
25
27
MHz
pF
MAX
Power Dissipation Capacitance
(Notes 5, 6)
C
-
5
-
-
-
PD
NOTES:
4. Noncascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enables (PE or TE)-to-clock SET
UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC de-
vices:
1
1
----------------------------
60 + 30 + 0
C
f
= ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ =
≈ 11MHz
P
MAX
CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time
5. C
PD
is used to determine the dynamic power consumption, per package.
2
2
6. P = V
CC
f + C
V
f where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage, f = Output Frequency.
CC o
D
i
L
CC
o
i
L
Timing Diagrams
CP
MR
TE
PE
PL
P0
P1
P2
P3
P4
P5
P6
P7
TC
255 254
3
2
1
0
255 254 254 253
FIGURE 2.
8
7
6
5
4
255 254 253 252
HC/HCT40103 COUNT
7
CD74HC40103, CD74HCT40103
Test Circuits and Waveforms
t
t
f
r
t
W
INPUT LEVEL
INPUT LEVEL
GND
90%
10%
CP
V
S
V
MR
CP
S
GND
t
W
1/f
MAX
t
t
PHL
PLH
t
TC
REM
10%
90%
V
S
INPUT LEVEL
GND
V
S
t
t
THL
TLH
FIGURE 3.
FIGURE 4.
t
t
f
f
INPUT LEVEL
INPUT LEVEL
GND
V
MR
CP
S
10%
90%
V
S
TE
t
t
t
h
PHL
t
SU
PLH
10%
90%
INPUT LEVEL
GND
V
S
V
S
TC
t
t
THL
TLH
FIGURE 5.
FIGURE 6.
VALID
INPUT LEVEL
GND
INPUTS
P0 - P7
V
S
TE
OR
PE
INPUT LEVEL
V
S
t
h
GND
t
SU
INPUT LEVEL
GND
t
h
PE
t
SU
V
S
INPUT LEVEL
GND
CP
V
S
t
t
h
t
SU
REC
INPUT LEVEL
GND
CP
V
S
FIGURE 7.
t C
FIGURE 8.
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
f
L
fC
L
t C
f
L
r
L
3V
V
CC
90%
2.7V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
10%
0.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 10. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 9. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
8
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