CD74HCT4051-Q1_12 [TI]
HIGH-SPEED CMOS LOGIC;
| 型号： | CD74HCT4051-Q1_12 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED CMOS LOGIC |
| 文件： | 总11页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
D
Qualification in Accordance With
AEC-Q100
D
Operation Control Voltage: 4.5 V to 5.5 V
Switch Voltage: 0 V to 10 V
†
D
D
D
Qualified for Automotive Applications
Direct LSTTL Input Logic Compatibility:
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
V
= 0.8 V Max, V = 2 V Min
IL IH
D
CMOS Input Compatibility: I v 1 mA at V
,
I
OL
V
OH
D
D
Wide Analog Input Voltage Range:
+5 V Max
M PACKAGE
(TOP VIEW)
Low ON Resistance
− 70 W Typical (V
− 40 W Typical (V
− V = 4.5 V)
EE
CC
CC
A4
A6
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
− V = 9 V)
EE
A2
A1
A0
A3
S0
D
D
D
D
Low Crosstalk Between Switches
Fast Switching and Propagation Speeds
Break-Before-Make Switching
COM OUT/IN A
A7
A5
E
Wide Operating Temperature Range: −405C
V
10 S1
S2
EE
to 1255C
GND
9
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
This device is a digitally controlled analog switch that utilizes silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits.
This analog multiplexer/demultiplexer controls analog voltages that may vary across the voltage supply range
(i.e., V to V ). It is a bidirectional switch that allows any analog input to be used as an output and vice-versa.
CC
EE
The switch has low ON resistance and low OFF leakages. In addition, this device has an enable control that,
when high, disables all switches to their OFF state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
§
−40°C to 125°C
SOIC − M Reel of 2500
CD74HCT4051QM96Q1
HCT4051Q
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
The suffix 96 denotes tape and reel.
§
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋꢌ ꢄꢉꢍ ꢎꢏꢏ ꢁ ꢀ ꢐꢑ ꢍ ꢒꢑ ꢌ ꢋꢀ
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
FUNCTION TABLE
INPUTS
ON CHANNELS
ENABLE
S1
L
S2
L
S0
L
L
L
L
L
L
L
L
L
H
A0
A1
L
L
H
L
L
H
H
L
A2
L
H
L
A3
H
H
H
H
X
A4
L
H
L
A5
H
H
X
A6
H
X
A7
None
X = Don’t care
logic diagram (positive logic)
Channel In/Out
V
CC
A
A
A
A
A
A
A
A
0
7
6
5
4
3
2
1
16
4
2
5
1
12 15 14 13
TG
TG
TG
TG
TG
TG
TG
TG
11
10
9
S0
S1
S2
E
Binary
to
1 of 8
Decoder
With
COM
OUT/IN
A
3
Logic
Level
Conversion
Enable
8
8
7
GND
V
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: V
− V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 10.5 V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to +7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to −7 V
CC
CC
EE
V
V
Input clamp current, I (V < −0.5 V or V > V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < V − 0.5 V or V > V
+ 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
EE
O
CC
Switch current (V > V − 0.5 V or V < V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
I
EE
I
CC
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
V
current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
EE
EE
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Lead temperature (during soldering):
At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to GND unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
5.5
10
UNIT
V
V
CC
Supply voltage
Supply voltage, V
− V
EE
(see Figure 1)
V
CC
V
V
V
V
V
Supply voltage (see Note 4 and Figure 2)
High-level input voltage
0
−6
V
EE
IH
IL
I
2
V
Low-level input voltage
0.8
V
Input control voltage
0
V
V
V
CC
Analog switch I/O voltage
V
V
IS
EE
0
CC
t
t
Input transition (rise and fall) time
Operating free-air temperature
V
CC
= 4.5 V
500
125
ns
°C
T
A
−40
NOTES: 3. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. In certain applications, the external load resistor current may include both V
and signal-line components. To avoid drawing V
CC
CC
current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed
0.6 V (calculated from r values shown in electrical characteristics table). No V
into the COM OUT/IN A terminal.
current flows through R if the switch current flows
L
on
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
recommended operating area as a function of supply voltages
8
6
4
2
0
8
6
4
2
0
HCT
HCT
HC
HC
0
−2
−4
−6
−8
0
2
4
6
8
10
12
(V
CC
– V ) – V
EE
(V
EE
– GND) – V
Figure 1
Figure 2
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −40°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
EE
V
CC
UNIT
MIN
TYP
70
40
90
45
10
5
MAX
160
120
180
130
MIN MAX
0 V
−4.5 V 4.5 V
0 V 4.5 V
−4.5 V 4.5 V
0 V 4.5 V
−4.5 V 4.5 V
4.5 V
240
180
270
195
V
V
= V
= V
or V
to V
IS
CC
EE
I
= 1 mA,
O
I
V = V or V
See Figure 9
,
r
Ω
Ω
IH IL
on
IS
CC
EE
∆r
Between any two channels
For switch OFF:
on
When V = V , V
IS CC OS
= V
= V
;
0 V
6 V
5 V
0.2
0.4
2
4
EE
CC
When V = V , V
IS
EE OS
For switch ON:
I
IZ
µA
All applicable combinations of V and V
voltage levels,
IS
OS
−5 V
V = V or V
I
IH
IL
I
I
V = V
or GND
Control input
When V = V
5.5 V
5.5 V
0.1
8
1
µA
µA
IL
I
CC
,
EE
IS
0 V
160
V
OS
= V
CC
I
= 0,
O
I
CC
V = V
or GND
When V = V
IS CC
,
CC
−4.5 V 5.5 V
16
320
490
V
OS
= V
EE
4.5 V
to
5.5 V
Per input pin: 1 unit load,
See Note 5, V = V
∆I
CC
100
360
µA
− 2.1 V
IN CC
NOTE 5: For dual-supply systems, theoretical worst case (V = 2.4 V, V
I
= 5.5 V) specification is 1.8 mA.
CC
HCT input loading
†
TYPE
INPUT
UNIT LOADS
4051
All
0.5
†
Unit load is ∆I
characteristics table, e.g., 360 µA max at 25°C.
limit specified in the electrical
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 8)
T
= −40°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TO 125°C
PARAMETER
V
EE
V
CC
UNIT
MIN
TYP
MAX
MIN MAX
C
C
C
C
C
C
C
C
C
= 15 pF
= 50 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
5 V
4
L
L
L
L
L
L
L
L
L
0 V
4.5 V
12
8
18
12
t
t
t
IN
OUT
OUT
OUT
ns
pd
en
dis
−4.5 V 4.5 V
5 V
23
19
0 V
4.5 V
55
39
83
59
S or E
ns
−4.5 V 4.5 V
5 V
0 V
4.5 V
45
32
10
68
48
10
S or E
ns
−4.5 V 4.5 V
C
Control
pF
I
operating characteristics, V
= 5 V, T = 25°C, input t , t = 6 ns
CC
A
r f
PARAMETER
TYP
UNIT
C
Power dissipation capacitance (see Note 6)
52
pF
pd
NOTE 6:
C
is used to determine the dynamic power consumption (P ), per package.
pd
D
2
2
P
= (C × V
× f ) + Σ (C + C ) V × f
CC O
D
pd CC
I
L
S
f
O
= output frequency
f = input frequency
I
C
C
= output load capacitance
= switch capacitance
= supply voltage
L
S
V
CC
analog channel characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
V
EE
V
CC
TYP
5
UNIT
pF
C
C
Switch input capacitance
I
Common output capacitance
25
pF
COM
−2.25 V 2.25 V
−4.5 V 4.5 V
145
180
Minimum switch frequency
response at −3 dB
See Figure 3 and Figure 10 and
Notes 7 and 8
f
MHz
%
max
−2.25 V 2.25 V 0.035
Sine-wave distortion
See Figure 5
−4.5 V
−2.25 V 2.25 V
−4.5 V 4.5 V
−2.25 V 2.25 V
−4.5 V 4.5 V
4.5 V
0.018
TBE
TBE
−73
E or address select (S0, S1, S2) to
switch feedthrough noise
See Figure 6 and Notes 8 and 9
mV
dB
See Figure 7 and Figure 11 and
Notes 8 and 9
Switch OFF signal feedthrough
−75
NOTES: 7. Adjust input voltage to obtain 0 dBm at V
OS
for f = 1 MHz.
IN
8.
V
is centered at (V
− V )/2.
IS
CC
EE
9. Adjust input for 0 dBm.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
V
IS
R
SWITCH
ON
V
OS1
0.1 mF
INPUT
C
R
f
IS
= 1-MHz Sine Wave
R = 50 W
C = 10 pF
V
/2
CC
V
CC
V
CC
R
V
OS2
V
SWITCH
OFF
OS
SWITCH
ON
V
IS
dB
METER
0.1 mF
dB
METER
V
/2
CC
C
R
50 Ω
10 pF
V
/2
CC
V
/2
CC
Figure 3. Frequency-Response Test Circuit
Figure 4. Crosstalk Between Two Switches
Test Circuit
E
V
CC
V
P−P
V
CC
V
OS
SWITCH
ALTERNATING
ON AND OFF
V
600 Ω
IS
V
= V
IH
I
V
OS
Sine
Wave
SWITCH
ON
t , t ≤ 6 ns
V
r f
OS
V
/2
10 mF
CC
V
f
= 1 MHz
IS
600 Ω
50 pF
CONT
50% DUTY
CYCLE
10k Ω
50 pF
DISTORTION
METER
SCOPE
V
/2
CC
V
/2
CC
f
IS
= 1 kHz to 10 kHz
Figure 5. Sine-Wave Distortion Test Circuit
Figure 6. Control-to-Switch Feedthrough Noise
Test Circuit
f
IS
≥ 1-MHz Sine Wave
R = 50 Ω
C = 10 pF
V
CC
0.1 µF
V
= V
R
C
IL
V
OS
SWITCH
V
IS
OFF
dB
R
C
METER
V
/2
V
/2
CC
CC
Figure 7. Switch OFF Signal Feedthrough Test Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ
ꢎ
ꢒꢏ
ꢖ
ꢏ
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SCLS569A − JANUARY 2004 − FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
Point
R
= 1 kΩ
L
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
V
EE
LOAD CIRCUIT
V
V
CC
3 V
0 V
Input
50% V
CC
50% V
CC
Output
Control
1.3 V
1.3 V
EE
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(see Note B)
50%
10%
50% V
10%
CC
V
50% V
CC
OL
10%
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
50% V
10%
50%
10%
Output
Waveform 2
(see Note B)
V
OH
CC
90%
50% V
CC
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. includes probe and test-fixture capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 8. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋꢌ ꢄꢉꢍ ꢎꢏꢏ ꢁ ꢀ ꢐꢑ ꢍ ꢒꢑ ꢌ ꢋꢀ
ꢔꢓ
ꢒ
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ꢐ
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ꢒ
ꢅ
ꢋ
ꢎ
ꢒ
ꢏꢖ
ꢏꢗ
ꢘ
ꢁ
ꢏ
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ꢒꢅ
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ꢗ
SCLS569A − JANUARY 2004 − FEBRUARY 2004
TYPICAL CHARACTERISTICS
120
100
80
V
CC
− V = 4.5 V
EE
60
V
CC
− V = 6 V
EE
40
V
CC
− V = 9 V
EE
20
1
2
3
4
5
6
7
8
9
Input Signal Voltage − V
Figure 9. Typical ON Resistance vs Input Signal Voltage
0
0
V
= 4.5 V
CC
GND = −4.5 V
−20
−40
−2
−4
−6
V
= 2.25 V
CC
GND = −2.25 V
= −2.25 V
V
= −4.5 V
= 50 Ω
EE
L
R
V
EE
Pin 12 to 3
R
= 50 Ω
L
V
= 2.25 V
CC
GND = −2.25 V
Pin 12 to 3
−60
V
EE
R
= −2.25 V
= 50 Ω
V
= 4.5 V
L
CC
GND = −4.5 V
Pin 12 to 3
−80
−8
V
= −4.5 V
= 50 Ω
EE
L
R
Pin 12 to 3
−100
−10
1M
Frequency − Hz
10K
100K
10M 100M
10K
100K
1M
10M
100M
Frequency − Hz
Figure 10. Channel ON Bandwidth
Figure 11. Channel OFF Feedthrough
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
CD74HCT4051QM96Q1
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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