CD74HCT42EE4 [TI]
High-Speed CMOS Logic BCD-to-Decimal Decoders (1 of 10); 高速CMOS逻辑BCD至十进制解码器（ 1 10 ）
| 型号： | CD74HCT42EE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic BCD-to-Decimal Decoders (1 of 10) |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC42, CD74HC42,
CD74HCT42
Data sheet acquired from Harris Semiconductor
SCHS133C
High-Speed CMOS Logic
August 1997 - Revised May 2003
BCD-to-Decimal Decoders (1 of 10)
Features
Description
• Buffered Inputs and Outputs
The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL decoders with the low power
consumption of standard CMOS integrated circuits. These
devices have the capability of driving 10 LSTLL loads and
are compatible with the standard LS logic family. One of ten
outputs (low on select) is selected in accordance with the
BCD input. Non-valid BCD inputs result in none of the
• Typical Propagation Delay: 12ns at V
o
= 5V,
[ /Title
(CD74H
C42,
CC
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74H
CT42)
/Subject
(High
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C outputs being selected (all outputs are high).
• Balanced Propagation Delay and Transition Times
Ordering Information
Speed
• Significant Power Reduction Compared to LSTTL
o
CMOS
Logic
BCD To
Deci-
PART NUMBER
CD54HC42F3A
CD74HC42E
TEMP. RANGE ( C)
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
Logic ICs
• HC Types
- 2V to 6V Operation
-55 to 125
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC42M
-55 to 125
16 Ld SOIC
16 Ld PDIP
at V
= 5V
CC
• HCT Types
CD74HCT42E
-55 to 125
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD54HC42
(CERDIP)
CD74HC42
(PDIP, SOIC)
CD74HCT42
(PDIP)
TOP VIEW
Y0
Y1
1
2
3
4
5
6
7
8
16 V
CC
15 A0
14 A1
13 A2
12 A3
11 Y9
10 Y8
Y2
Y3
Y4
Y5
Y6
9
Y7
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003 Texas Instruments Incorporated.
1
CD54HC42, CD74HC42, CD74HCT42
Functional Diagram
1
Y0
15
14
13
12
2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
A0
A1
A2
A3
3
4
5
6
7
9
10
11
TRUTH TABLE
INPUTS
OUTPUTS
A3
L
A2
L
A1
L
A0
L
Y0
L
Y1
Y2
H
H
L
Y3
H
H
H
L
Y4
Y5
Y6
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
L
Y8
H
H
H
H
H
H
H
H
L
Y9
H
H
H
H
H
H
H
H
H
L
H
L
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H = High Voltage Level, L = Low Voltage Level
2
CD54HC42, CD74HC42, CD74HCT42
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC42, CD74HC42, CD74HCT42
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay,
Input to Y (Figure 1)
t
t
C = 50pF
2
-
-
-
150
30
26
-
-
-
-
-
-
-
-
-
190
38
33
-
-
-
-
-
-
-
-
-
225
45
38
-
ns
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
6
-
-
-
-
-
-
-
-
Any Input to Y
t
, t
C = 15pF
5
12
-
PLH PHL
L
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
L
2
75
15
13
10
95
19
16
10
110
22
19
10
4.5
6
-
-
Input Capacitance
C
-
-
-
IN
4
CD54HC42, CD74HC42, CD74HCT42
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
65
-
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay,
Input to Y (Figure 2)
t
, t
PLH PHL
C = 50pF
4.5
-
35
-
44
-
53
ns
L
Any Input to Y
t
, t
PLH PHL
C = 15pF
5
-
-
14
-
-
-
-
-
-
-
-
ns
ns
L
Output Transition Time
(Figure 2)
t
, t
TLH THL
C = 50pF
L
4.5
15
19
22
Input Capacitance
C
-
-
-
-
-
-
10
-
-
-
10
-
-
-
10
-
pF
pF
IN
Power Dissipation Capacitance
(Notes 3, 4)
C
5
70
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
2
PD
4. P = V
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54HC42F3A
CD74HC42E
ACTIVE
ACTIVE
J
16
16
1
TBD
A42
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC42EE4
CD74HC42M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
PDIP
PDIP
N
D
D
D
N
N
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC42ME4
CD74HC42MG4
CD74HCT42E
CD74HCT42EE4
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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