CD74HCT4514E [TI]
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS; ????????? 4线路至16线路解码器/多路解复用器型号: | CD74HCT4514E |
厂家: | TEXAS INSTRUMENTS |
描述: | 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS |
文件: | 总10页 (文件大小:249K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢃ ꢉꢊ ꢋꢌꢍ ꢅ ꢎ ꢇ ꢏ ꢉꢊ ꢋꢌꢍ ꢁꢍꢀ ꢎꢁ ꢍꢐꢑꢒ ꢁꢍꢓ ꢔꢊꢅ ꢋ ꢕꢊ ꢍꢖ ꢍ ꢐ
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SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004
CD74HCT4514 . . . E PACKAGE
CD74HCT4515 . . . E OR EN PACKAGE
(TOP VIEW)
D
D
4.5-V to 5.5-V V
Operation
CC
Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus-Driver Outputs . . . 15 LSTTL Loads
1
24
23
22
21
20
19
18
17
16
15
14
13
LE
A0
A1
Y7
Y6
Y5
Y4
Y3
Y1
V
E
A3
CC
2
D
D
D
D
Wide Operating Temperature Range of
−55°C to 125°C
Balanced Propagation Delays and
Transition Times
3
4
A2
5
Y10
Y11
Y8
6
Significant Power Reduction Compared to
LSTTL Logic ICs
7
8
Y9
HCT Types
− Direct LSTTL Input Logic Compatibility,
9
Y14
Y15
Y12
Y13
10
11
12
Y2
Y0
GND
V
= 0.8 V (Max), V = 2 V (Min)
IL
IH
− CMOS Input Compatibility,
I ≤ 1 µA at V , V
I
OL OH
description/ordering information
The CD74HCT4514 and CD74HCT4515 are high-speed silicon-gate devices consisting of a 4-bit strobed latch
and a 4-line to 16-line decoder. The selected output is enabled by a low on the enable (E) input. A high on E
inhibits selection of any output. Demultiplexing is accomplished by using E as the data input and the select inputs
(A0−A3) as addresses. E also serves as a chip select when these devices are cascaded.
When the latch enable (LE) is high, the output follows changes in the inputs (see decode function table). When
LE is low, the output is isolated from changes in the input and remains at the level (high for the ’4514, low for
the ’4515) it had before the latch was enabled.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
CD74HCT4514E
CD74HCT4515E
CD74HCT4514E
CD74HCT4515E
PDIP − E
Tube
−55°C to 125°C
PDIP − EN Tube
CD74HCT4515EN
CD74HCT4515EN
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢃ ꢆꢇ ꢃꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢃꢆ ꢇ ꢆ
ꢃꢉ ꢊ ꢋ ꢌꢍ ꢅꢎ ꢇ ꢏꢉ ꢊ ꢋ ꢌꢍ ꢁꢍ ꢀꢎ ꢁꢍ ꢐꢑ ꢒ ꢁꢍ ꢓꢔ ꢊꢅ ꢋꢕ ꢊꢍ ꢖꢍꢐꢑ
ꢗꢋ ꢅ ꢄ ꢋ ꢌ ꢕꢔ ꢅ ꢊ ꢘꢅꢀ ꢄꢍ ꢑ
SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004
DECODE FUNCTION TABLE
(LE = H)
ADDRESSED OUTPUT
CD74HCT4514 = H
CD74HCT4515 = L
DECODER INPUTS
E
A3
A2
A1
A0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Y0
Y1
L
L
H
H
L
Y2
L
L
H
L
Y3
L
H
H
H
H
L
Y4
L
L
H
L
Y5
L
H
H
L
Y6
L
H
L
Y7
H
H
H
H
H
H
H
H
Y8
L
L
H
L
Y9
L
H
H
L
Y10
Y11
Y12
Y13
Y14
Y15
L
H
L
H
H
H
H
L
H
L
H
H
H
All outputs = L, CD74HCT4514
All outputs = H, CD74HCT4515
H
X
X
X
X
H = high, L = low, X = don’t care
logic diagram (positive logic)
CD74HCT4514 CD74HCT4515
11
9
10
Y0
Y1
Y2
Y0
Y1
Y2
8
7
Y3
Y4
Y5
Y6
Y7
Y8
Y3
Y4
Y5
Y6
Y7
Y8
2
A0
A1
A2
A3
6
3
5
21
22
Latch
4
4-Line
to
16-Line
Decoder
18
17
Y9
Y9
20
19
14
13
16
Y10
Y11
Y12
Y13
Y14
Y10
Y11
Y12
Y13
Y14
1
LE
15
Y15
Y15
23
GND = 12
E
V
CC
= 24
2
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SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-3.
recommended operating conditions (see Note 3)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
0
0
V
V
0
0
V
V
0
0
V
V
V
CC
CC
CC
Output voltage
V
O
CC
CC
CC
∆t/∆v Input transition rise or fall rate
500
500
500
ns
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN MAX
MIN MAX
MIN MAX
I
I
I
I
= −20 µA
= −4 mA
= 20 µA
= 4 mA
4.4
3.98
0.1
0.26
0.1
8
4.4
3.7
0.1
0.4
1
4.4
3.84
0.1
0.33
1
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
V
V
OH
I
IL
V = V or V
OL
I
IH
IL
I
I
V = V
or 0
5.5 V
5.5 V
µA
µA
I
I
CC
V = V
or 0,
I
O
= 0
160
80
CC
I
CC
4.5 V to
5.5 V
‡
One input at V
CC
− 2.1 V, Other inputs at 0 or V
CC
360
490
450
µA
∆I
CC
C
10
10
10
pF
i
‡
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(V = 2.4 V, V = 5.5 V) specification is 1.8 mA.
I
CC
3
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ꢃꢉ ꢊ ꢋ ꢌꢍ ꢅꢎ ꢇ ꢏꢉ ꢊ ꢋ ꢌꢍ ꢁꢍ ꢀꢎ ꢁꢍ ꢐꢑ ꢒ ꢁꢍ ꢓꢔ ꢊꢅ ꢋꢕ ꢊꢍ ꢖꢍꢐꢑ
ꢗꢋ ꢅ ꢄ ꢋ ꢌ ꢕꢔ ꢅ ꢊ ꢘꢅꢀ ꢄꢍ ꢑ
SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004
HCT INPUT LOADING TABLE
INPUT
A0−A3
LE
UNIT LOAD
0.15
0.85
0.3
E
Unit load is ∆I
limit
CC
electrical
specified
in
characteristics table (e.g.,
360 µA max at 25°C).
timing requirements over recommended operating free-air temperature range, V
L
= 4.5 V,
CC
C = 15 pF (unless otherwise noted) (see Figure 1)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
30
20
5
MAX
MIN
45
30
5
MAX
MIN
38
25
5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 4.5 V
CC
T
= −55°C
T = −40°C
A
A
T
= 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TO 125°C
TO 85°C
PARAMETER
UNIT
MIN
MAX
55
MIN MAX
MIN
MAX
69
A0−A3
LE
83
75
60
22
50
63
t
t
Y
Y
C
C
= 50 pF
= 50 pF
ns
ns
pd
L
L
40
50
E
15
19
t
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
75
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢋꢅ ꢄ ꢋꢌ ꢕꢔꢅ ꢊꢘꢅꢀ ꢄ ꢍ
SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
1 kΩ
Point
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
or t
t
t
w
LOAD CIRCUIT
3 V
0 V
1.3 V
1.3 V
Input
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
Reference
Input
3 V
0 V
1.3 V
CLR
Input
1.3 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
2.7 V
2.7 V
3 V
0 V
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
CLK
t
t
f
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.3 V
1.3 V
Output
Control
1.3 V
1.3 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(see Note B)
1.3 V
10%
1.3 V
10%
1.3 V
V
OL
10%
V
OL
t
t
r
f
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
Output
Waveform 2
(see Note B)
V
OH
90%
1.3 V
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CD74HCT4514E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
24
24
24
24
24
24
15
15
15
15
15
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CD74HCT4514EE4
CD74HCT4515E
PDIP
PDIP
PDIP
PDIP
PDIP
N
N
Pb-Free
(RoHS)
Pb-Free
(RoHS)
CD74HCT4515EE4
CD74HCT4515EN
CD74HCT4515ENE4
N
Pb-Free
(RoHS)
NT
NT
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.020 (0,51) MIN
0.425 (10,80) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.020 (0,51) MIN
0.610 (15,49)
0.590 (14,99)
Seating Plane
0.100 (2,54)
0.125 (3,18) MIN
0.010 (0,25) NOM
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
PINS **
M
24
28
32
40
48
52
DIM
1.270
1.450
1.650
2.090
2.450
2.650
A MAX
(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)
1.230
1.410
1.610
2.040
2.390
2.590
A MIN
(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)
4040053/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
CD74HCT4514EE4
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches 24-PDIP -55 to 125
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