CD74HCT541E [TI]
High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State; 高速CMOS逻辑八路缓冲器和线路驱动器，三态
| 型号： | CD74HCT541E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State |
| 文件： | 总8页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC540, CD74HCT540,
CD74HC541, CD74HCT541
Data sheet acquired from Harris Semiconductor
SCHS189
High Speed CMOS Logic
Octal Buffer and Line Drivers, Three-State
January 1998
Features
Description
• CD74HC540, CD74HCT540 . . . . . . . . . . . . . . . Inverting The Harris CD74HC540 and CD74HCT540 are Inverting
Octal Buffers and Line Drivers with Three-State Outputs and
the capability to drive 15 LSTTL loads. The Harris
• CD74HC541, CD74HCT541 . . . . . . . . . . . . . .Non-Inverting
[ /Title
(CD74
HC540
,
CD74
HCT54
0,
CD74
HC541
,
CD74
HCT54
CD74HC541 and CD74HCT541 are Non-Inverting Octal Buff-
ers and Line Drivers with Three-State Outputs that can drive
15 LSTTL loads. The Output Enables (OE1) and (OE2) con-
trol the Three-State Outputs. If either OE1 or OE2 is HIGH the
outputs will be in the high impedance state. For data output
OE1 and OE2 both must be LOW.
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay = 9ns at V
o
= 5V,
CC
C = 15pF, T = 25 C
L
A
Ordering Information
• Fanout (Over Temperature Range)
TEMP.
PKG.
NO.
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
PART NUMBER RANGE ( C)
PACKAGE
20 Ld PDIP
CD74HC540E
CD74HCT540E
CD74HC541E
CD74HCT541E
CD74HC540M
CD74HCT540M
CD74HC541M
CD74HCT541M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E20.3
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
E20.3
E20.3
E20.3
M20.3
M20.3
M20.3
M20.3
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
• HCT Types
- 4.5V to 5.5V Operation
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinouts
CD74HC540, CD74HCT540
(PDIP, SOIC)
CD74HC541, CD74HCT541
(PDIP, SOIC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
1
2
3
4
5
6
7
8
9
V
OE
A0
A1
A2
A3
A4
A5
A6
A7
20
19
OE1
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
CC
OE2
OE2
18 Y0
17 Y1
16 Y2
15 Y3
14 Y4
13 Y5
18 Y0
17 Y1
16 Y2
15 Y3
14 Y4
13 Y5
12
12
Y6
Y6
GND 10
11 Y7
GND 10
11 Y7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1659.2
Copyright © Harris Corporation 1998
1
CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
Functional Diagram
OE
OE
B
A
540 541
D
D
Y
Y
0
0
0
Y
Y
Y
1
1
1
D
Y
2
4
6
2
2
D
Y
Y
3
3
3
D
D
Y
Y
4
4
Y
Y
5
5
5
D
Y
Y
6
6
D
Y
Y
7
7
7
TRUTH TABLE
INPUTS
OUTPUTS
OE1
L
OE2
L
An
H
X
540
541
H
L
Z
Z
H
H
X
Z
X
H
X
Z
L
L
L
L
NOTE:
H = HIGH Voltage Level
L
X
Z
= LOW Voltage Level
= Don’t Care
= High Impedance
2
CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
120
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-7.8
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
6
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
7.8
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three- State Leakage
Current
I
V
or V
V
=
or
6
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
IH
O
V
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-6
0.02
6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
CC
CC
GND
Three- State Leakage
Current
I
V
or V
V =
O
±0.5
±5.0
OZ
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
UNIT LOADS
INPUT
A0 - A7
HCT540
1
HCT541
0.4
OE2
0.75
1.15
0.75
OE1
1.15
NOTE: Unit load is ∆I
Table, e.g., 360µA max. at 25 C.
limit specific in DC Electrical Specifications
CC
o
4
CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
, t
C = 50pF
L
PLH PHL
Data to Outputs (540)
2
-
-
-
110
22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
165
33
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
4.5
5
-
-
C = 15pF
9
-
L
C = 50pF
6
-
19
115
23
-
24
145
29
-
28
175
35
-
L
Data to Outputs (541)
t
t
t
t
, t
C
= 50pF
2
-
-
PLZ PHZ
L
L
4.5
5
-
-
C
= 15pF
-
9
-
C = 50pF
6
-
20
160
32
-
25
200
40
-
30
240
48
-
L
Output Enable and Disable
to Outputs (540)
, t
PLZ PHZ
C
= 50pF
2
-
-
L
L
4.5
5
-
-
C
= 15pF
-
13
-
C = 50pF
6
-
27
160
32
-
34
200
40
-
41
240
48
-
L
Output Enable and Disable
to Outputs (541)
, t
PLZ PHZ
C
= 50pF
2
-
-
L
L
4.5
5
-
-
C
= 15pF
-
14
-
C = 50pF
6
-
23
60
12
10
10
20
29
75
15
13
10
20
35
90
18
15
10
20
L
Output Transition Time
Input Capacitance
, t
THL TLH
C
= 50pF
2
-
-
L
4.5
6
-
-
-
-
C
C
= 50pF
-
-
10
20
-
I
L
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 4, 5) (540)
C
C
C
= 15pF
= 15pF
5
5
-
-
50
48
-
-
-
-
-
-
-
-
-
-
pF
pF
PD
PD
L
Power Dissipation Capacitance
(Notes 4, 5) (541)
C
L
HCT TYPES
Propagation Delay
t
t
PHL, PLH
Data to Outputs (540)
C
= 50pF
4.5
5
-
-
-
9
-
24
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
36
-
ns
ns
ns
ns
ns
ns
ns
pF
L
C = 15pF
L
Data to Outputs (541)
t
t
t
t
C
= 50pF
4.5
5
-
28
-
35
-
42
-
PHL, PLH
L
C = 15pF
-
11
-
L
Output Enable and Disable
to Outputs (540, 541)
, t
PLZ PHZ
C
= 50pF
4.5
5
-
35
-
44
-
53
-
L
C = 15pF
-
14
-
L
Output Transition Time
Input Capacitance
, t
TLH THL
C
= 50pF
= 50pF
4.5
-
-
12
10
15
10
18
10
L
L
C
C
10
-
I
5
CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
20
MIN
MAX UNITS
CC
Three-State Output
Capacitance
C
-
-
20
-
20
-
-
20
pF
O
Power Dissipation Capacitance
(Notes 4, 5) (540, 541)
C
C
= 15pF
5
-
55
-
-
-
-
-
pF
PD
L
NOTES:
4. C
is used to determine the dynamic power consumption, per channel.
2
PD
5. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
6
Test Circuits and Waveforms (Continued)
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
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