CD74HCT573DBRG4
更新时间：2024-09-18 15:04:14
品牌：TI
描述：HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SSOP-20
概述
规格参数
数据手册
替代型号CD74HCT573DBRG4 概述
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SSOP-20 锁存器 总线驱动器/收发器
CD74HCT573DBRG4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | SSOP |
| 包装说明： | SSOP, SSOP20,.3 | 针数： | 20 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.12 | 系列： | HCT |
| JESD-30 代码： | R-PDSO-G20 | JESD-609代码： | e4 |
| 长度： | 7.2 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | BUS DRIVER | 最大I（ol）： | 0.006 A |
| 湿度敏感等级： | 1 | 位数： | 8 |
| 功能数量： | 1 | 端口数量： | 2 |
| 端子数量： | 20 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 输出特性： | 3-STATE |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SSOP | 封装等效代码： | SSOP20,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, SHRINK PITCH |
| 包装方法： | TAPE AND REEL | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 5 V | Prop。Delay @ Nom-Sup： | 53 ns |
| 传播延迟（tpd）： | 53 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 2 mm | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | MILITARY |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 5.3 mm |
| Base Number Matches： | 1 |
CD74HCT573DBRG4 数据手册
通过下载CD74HCT573DBRG4数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
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SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
CD54HCT573 . . . F PACKAGE
CD74HCT573 . . . DB, E, OR M PACKAGE
(TOP VIEW)
D
D
4.5-V to 5.5-V V
Operation
CC
Wide Operating Temperature Range of
−55°C to 125°C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
D
D
D
D
Balanced Propagation Delays and
Transition Times
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Standard Outputs Drive Up To 10 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible
description/ordering information
GND
The ’HCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
PDIP − E Tube
CD74HCT573E
CD74HCT573E
HK573
SSOP − DB Tape and reel
Tube
CD74HCT573DBR
CD74HCT573M
CD74HCT573M96
CD54HCT573F3A
−55°C to 125°C
SOIC − M
HCT573M
Tape and reel
CDIP − F
Tube
CD54HCT573F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢂ ꢆꢇ ꢈ ꢀꢁ ꢆ ꢃꢄ ꢀꢅ ꢂꢆ ꢇ
ꢉꢀ ꢅꢊ ꢋ ꢅ ꢌ ꢊꢍ ꢎꢏꢊꢌ ꢐꢍ ꢅ ꢁꢑꢅ ꢒꢏ ꢐ ꢋꢊꢅꢀ ꢄ ꢐꢎ
ꢓꢔ ꢅ ꢄ ꢇ ꢑꢎꢅꢊꢅ ꢐ ꢉꢕꢅ ꢏꢕ ꢅꢎ
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
19
1Q
2
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
recommended operating conditions (see Note 3)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
V
V
V
V
V
V
V
CC
CC
CC
Output voltage
V
O
CC
CC
CC
∆t/∆v Input transition rise or fall rate
500
500
500
ns
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −20 µA
= −6 mA
= 20 µA
= 6 mA
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
V
V
OH
I
IL
3.98
3.7
3.84
0.1
0.26
0.1
0.5
8
0.1
0.4
1
0.1
0.33
1
V = V or V
OL
I
IH
IL
I
I
I
V = V
or 0
5.5 V
5.5 V
5.5 V
µA
µA
µA
I
I
CC
V
= V
or 0
or 0,
10
5
OZ
CC
O CC
V = V
I
I
O
= 0
160
80
CC
4.5 V to
5.5 V
†
One input at V
CC
− 2.1 V, Other inputs at 0 or V
360
490
450
µA
∆I
CC
CC
C
C
10
20
10
20
10
20
pF
pF
i
o
†
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(V = 2.4 V, V = 5.5 V) specification is 1.8 mA.
I
CC
HCT INPUT LOADING TABLE
INPUT
OE
UNIT LOAD
1.25
Any D
LE
0.3
0.65
Unit load is ∆I
limit
CC
electrical
specified
in
characteristics table (e.g.,
360 µA max at 25°C).
3
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ꢓꢔ ꢅ ꢄ ꢇ ꢑꢎꢅꢊꢅ ꢐ ꢉꢕꢅ ꢏꢕ ꢅꢎ
SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
timing requirements over recommended operating free-air temperature range, V
otherwise noted) (see Figure 1)
= 4.5 V (unless
CC
T
= −55°C
T
= −40°C
TO 85°C
A
A
T
A
= 25°C
TO 125°C
UNIT
MIN
16
MAX
MIN
24
MAX
MIN
20
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
13
20
16
10
15
13
switching characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 4.5 V
CC
T
= −55°C
T = −40°C
A
A
T
= 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TO 125°C
TO 85°C
PARAMETER
UNIT
MIN
MAX
35
MIN MAX
MIN
MAX
44
D
53
53
53
t
pd
Q
C
= 50 pF
ns
L
LE
35
44
t
t
t
Q
Q
Q
C
C
C
= 50 pF
= 50 pF
= 50 pF
35
44
ns
ns
ns
OE
OE
en
dis
t
L
L
L
35
12
53
18
44
15
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
53
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
1 kΩ
Point
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
or t
t
t
w
LOAD CIRCUIT
3 V
0 V
1.3 V
1.3 V
Input
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
Reference
Input
3 V
0 V
1.3 V
CLR
Input
1.3 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
2.7 V
2.7 V
3 V
0 V
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
CLK
t
t
f
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.3 V
1.3 V
Output
Control
1.3 V
1.3 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(see Note B)
1.3 V
10%
1.3 V
10%
1.3 V
V
OL
10%
V
OL
t
t
r
f
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
Output
Waveform 2
(see Note B)
V
OH
90%
1.3 V
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-8685601RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8685601RA
CD54HCT573F3A
CD54HCT573F
ACTIVE
ACTIVE
CDIP
CDIP
J
J
20
20
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
CD54HCT573F
CD54HCT573F3A
5962-8685601RA
CD54HCT573F3A
CD74HCT573DBR
CD74HCT573DBRE4
CD74HCT573DBRG4
CD74HCT573E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
DB
N
20
20
20
20
20
20
20
20
20
20
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
HK573
Green (RoHS
& no Sb/Br)
HK573
Green (RoHS
& no Sb/Br)
HK573
Pb-Free
(RoHS)
CD74HCT573E
CD74HCT573E
HCT573M
HCT573M
HCT573M
HCT573M
HCT573M
CD74HCT573EE4
CD74HCT573M
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
DW
DW
DW
DW
DW
25
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD74HCT573M96
CD74HCT573M96E4
CD74HCT573M96G4
CD74HCT573MG4
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HCT573, CD74HCT573 :
Catalog: CD74HCT573
•
Military: CD54HCT573
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HCT573DBR
CD74HCT573M96
SSOP
SOIC
DB
20
20
2000
2000
330.0
330.0
16.4
24.4
8.2
7.5
2.5
2.7
12.0
12.0
16.0
24.0
Q1
Q1
DW
10.8
13.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HCT573DBR
CD74HCT573M96
SSOP
SOIC
DB
20
20
2000
2000
367.0
367.0
367.0
367.0
38.0
45.0
DW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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CD74HCT573DBRG4 CAD模型
引脚图
封装焊盘图
CD74HCT573DBRG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CD74HCT573DBR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3 STATE OUTPUTS | 完全替代 |
|
| CD74HCT573DBRE4 | TI | High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SSOP -55 to 125 | 完全替代 |
|
| SN74HCT573DBR | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS | 类似代替 |
|
CD74HCT573DBRG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CD74HCT573E | TI | High Speed CMOS Logic Octal Transparent Latch, Three-State Output | 获取价格 |
|
| CD74HCT573E | HARRIS | High Speed CMOS Logic Octal Transparent Latch, Three-State Output | 获取价格 |
|
| CD74HCT573EN | ETC | Logic IC | 获取价格 |
|
| CD74HCT573EX | RENESAS | 暂无描述 | 获取价格 |
|
| CD74HCT573EX | ROCHESTER | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PACKAGE-20 | 获取价格 |
|
| CD74HCT573F | ETC | Logic IC | 获取价格 |
|
| CD74HCT573H | ETC | 8-Bit D-Type Latch | 获取价格 |
|
| CD74HCT573M | TI | High Speed CMOS Logic Octal Transparent Latch, Three-State Output | 获取价格 |
|
| CD74HCT573M | HARRIS | High Speed CMOS Logic Octal Transparent Latch, Three-State Output | 获取价格 |
|
| CD74HCT573M96 | TI | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3 STATE OUTPUTS | 获取价格 |
|
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