CD74HCT74M96G4 [TI]
具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 D 触发器 | D | 14 | -55 to 125;
| 型号： | CD74HCT74M96G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 D 触发器 | D | 14 | -55 to 125 光电二极管 逻辑集成电路 触发器 锁存器 |
| 文件： | 总8页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC74, CD74HC74,
CD74HCT74
Data sheet acquired from Harris Semiconductor
SCHS124
Dual D Flip-Flop with Set and Reset
Positive-Edge Trigger
January 1998
Features
Description
• Hysteresis on Clock Inputs for Improved Noise Immu-
nity and Increased Input Rise and Fall Times
The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize
silicon gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL loads.
[ /Title
(CD54H
C74,
CD74H
C74,
CD74H
CT74)
/Subject
(Dual D
Flip-
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
This flip-flop has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going transition of the clock pulse. SET and RESET
are independent of the clock and are accomplished by a low
level at the appropriate input.
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF,
CC L
o
T = 25 C
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Flop
with Set
Ordering Information
TEMP. RANGE
PKG.
NO.
• Significant Power Reduction Compared to LSTTL
Logic ICs
o
PART NUMBER
CD54HC74F
CD74HC74E
CD74HCT74E
CD74HC74M
CD74HCT74M
NOTES:
( C)
PACKAGE
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
14 Ld CERDIP F14.3
• HC Types
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
E14.3
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
E14.3
IL
IH
at V
= 5V
CC
M14.15
M14.15
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
2. Die is available which meets all electrical specifications. Please
contact your local sales office or Harris customer service for
ordering information.
Pinout
CD54HC74, CD74HC74, CD74HCT74
(PDIP, SOIC, CERDIP)
TOP VIEW
1R
1D
1
2
3
4
5
6
7
14 V
CC
13 2R
12 2D
11 2CP
10 2S
1CP
1S
1Q
1Q
9
8
2Q
2Q
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1476.1
Copyright © Harris Corporation 1998
1
CD54HC74, CD74HC74, CD74HCT74
Functional Diagram
1
RESET
R
2
3
5
6
Q
Q
DATA
D
F/F 1
CP
CLOCK
S
4
SET
13
RESET
R
12
11
9
8
D
Q
Q
DATA
F/F 2
CP
CLOCK
GND = PIN 7
= PIN 14
S
V
CC
10
SET
TRUTH TABLE
INPUTS
OUTPUTS
SET
L
RESET
CP
X
X
X
↑
D
Q
Q
H
L
X
X
X
H
L
H
L
H
L
H
L
L
H (Note 3)
H (Note 3)
H
H
H
H
L
L
H
H
↑
H
H
L
X
Q0
Q0
NOTE:
H = High Level (Steady State)
L
X
↑
= Low Level (Steady State)
= Don’t Care
= Low-to-High Transition
Q0 = the level of Q before the indicated input conditions were established.
3. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.
2
CD54HC74, CD74HC74, CD74HCT74
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 4)
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
JA
JC
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
90
120
130
-
-
55
IK
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
I
I
CC
DC Drain Current, per Output, I
O
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
O
CC
o
DC Output Diode Current, I
OK
For V < -0.5V or V > V
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
(SOIC - Lead Tips Only)
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
4.5
3.15
-
-
3.15
-
-
3.15
6
2
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
1.9
1.9
OH
IH
V
IL
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or
0.02
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
IH
V
IL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
-
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54HC74, CD74HC74, CD74HCT74
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
4
-
40
-
80
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
V
V
or
IH
4.5
4.4
4.4
4.4
OH
V
IL
CMOS Loads
High Level Output
Voltage
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
TTL Loads
Low Level Output
Voltage CMOS Loads
V
V
V
or
IH
-4
4.5
4.5
-
-
-
-
0.1
-
-
0.1
-
-
0.1
0.4
V
V
OL
IL
Low Level Output
Voltage
TTL Loads
0.02
4
0.26
0.33
Input Leakage
Current
I
V
and
GND
5.5
5.5
-
±0.1
-
±1
-
±1
µA
I
CC
Quiescent Device
Current
I
V
or
0
-
-
-
-
4
-
-
40
-
-
80
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
490
CC
(Note 5)
CC
- 2.1
NOTE:
5. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
D
0.5
0.5
R
CP
S
0.7
0.75
NOTE: Unit Load is ∆I
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
CC
o
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Data to CP Setup Time
(Figure 5)
t
-
2
60
12
10
-
-
-
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
SU
4.5
6
4
CD54HC74, CD74HC74, CD74HCT74
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
3
MAX
MIN
3
MAX
UNITS
ns
Hold Time (Figure 5)
t
-
-
-
-
-
2
4.5
6
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H
3
3
ns
3
3
3
ns
Removal Time R, S, to CP
(Figure 5)
t
REM
2
30
6
40
8
45
9
ns
4.5
6
ns
5
7
8
ns
Pulse Width R, S (Figure 1)
Pulse Width CP (Figure 1)
CP Frequency
t
2
80
16
14
80
16
14
6
100
20
17
100
20
17
5
120
24
20
120
24
20
4
ns
W
W
4.5
6
ns
ns
t
2
ns
4.5
6
ns
ns
f
MAX
2
MHz
MHz
MHz
4.5
6
30
35
25
29
20
23
HCT TYPES
Data to CP Setup Time
(Figure 6)
t
-
4.5
12
-
-
15
-
18
-
ns
SU
Hold Time (Figure 6)
t
-
-
4.5
4.5
3
6
-
-
-
-
3
8
-
-
3
9
-
-
ns
ns
H
Removal Time R, S, to CP
(Figure 6)
t
f
REM
Pulse Width R, S (Figure 2)
Pulse Width CP (Figure 2)
CP Frequency
t
t
-
-
-
4.5
4.5
4.5
16
18
25
-
-
-
-
-
-
20
23
20
-
-
-
24
27
16
-
-
-
ns
ns
W
W
MHz
MAX
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
MIN TYP MAX
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,
CP to Q, Q (Figure 3)
t
, t
PLH PHL
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
L
C = 50pF
L
C = 15pF
14
-
L
C = 50pF
6
30
200
40
-
37
250
50
-
45
300
60
-
L
Propagation Delay,
R, S to Q, Q (Figure 3)
t , t
PLH PHL
C = 50pF
2
-
L
C = 50pF
4.5
5
-
L
C = 15pF
17
-
L
C = 50pF
6
34
75
15
13
10
43
95
19
16
10
51
110
22
19
10
L
Transition Time (Figure 3)
Input Capacitance
t
, t
TLH THL
C = 50pF
2
-
L
C = 50pF
4.5
6
-
L
C = 50pF
L
-
C
-
-
-
I
5
CD54HC74, CD74HC74, CD74HCT74
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
CP Frequency
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
MHz
pF
f
CL = 15pF
-
5
5
-
-
50
25
-
-
-
-
-
-
-
-
-
-
MAX
Power Dissipation Capacitance
(Notes 6, 7)
C
PD
HCT TYPES
Propagation Delay,
CP to Q, Q (Figure 4)
t
, t
PLH PHL
C = 50pF
L
4.5
4.5
-
-
-
-
35
40
-
-
44
50
-
-
53
60
ns
ns
Propagation Delay,
t , t
PHL PLH
CL = 50pF
R, S to Q, Q (Figure 4)
Transition Time (Figure 4)
Input Capacitance
CP Frequency
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
-
15
10
-
-
-
-
-
19
10
-
-
-
-
-
22
10
-
ns
pF
C
-
-
I
f
CL = 15pF
-
5
50
30
MHz
pF
MAX
Power Dissipation Capacitance
(Notes 6, 7)
C
5
-
-
-
PD
NOTES:
6. C
PD
is used to determine the dynamic power consumption, per flip-flop.
2
2
7. P = C
V
f + Σ (C V
f ) where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage.
D
PD CC
i
L
CC
o
i
o
L
CC
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
0.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
CD54HC74, CD74HC74, CD74HCT74
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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