CD74HCT85E [TI]
High Speed CMOS Logic 4-Bit Magnitude Comparator; 高速CMOS逻辑4位幅度比较
| 型号： | CD74HCT85E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 4-Bit Magnitude Comparator |
| 文件： | 总8页 (文件大小：50K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC85,
CD74HCT85
Data sheet acquired from Harris Semiconductor
SCHS136
High Speed CMOS Logic
August 1997
4-Bit Magnitude Comparator
Features
Description
• Buffered Inputs and Outputs
The CD74HC85 and CD74HCT85 are high speed
magnitude comparators that use silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
with the low power consumption of standard CMOS
integrated circuits.
• Typical Propagation Delay: 13ns (Data to Output at
o
[ /Title
(CD74
HC85,
CD74
HCT85
)
V
= 5V, C = 15pF, T = 25 C
L A
CC
• Serial or Parallel Expansion Without External Gating
These 4-bit devices compare two binary, BCD, or other
monotonic codes and present the three possible magnitude
results at the outputs (A > B, A < B, and A = B). The 4-bit
input words are weighted (A0 to A3 and B0 to B3), where A3
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
/Sub-
ject
• Wide Operating Temperature Range . . . -55 C to 125 C and B are the most significant bits.
3
• Balanced Propagation Delay and Transition Times
The devices are expandable without external gating, in both
(High
Speed
CMOS
Logic
4-Bit
Magni-
tude
serial and parallel fashion. The upper part of the truth table
indicates operation using a single device or devices in a
serially expanded application. The parallel expansion
scheme is described by the last three entries in the truth
table.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%of V at
CC
Ordering Information
IL
IH
V
= 5V
CC
PKG.
• HCT Types
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
Com-
para-
- 4.5V to 5.5V Operation
CD74HC85E
CD74HCT85E
CD74HC85M
CD74HCT85M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
16 Ld SOIC M16.15
16 Ld SOIC M16.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC85, CD74HCT85
(PDIP, SOIC)
TOP VIEW
B3
(A < B) IN
(A = B) IN
(A > B) IN
(A > B) OUT
(A = B) OUT
(A < B) OUT
GND
1
2
3
4
5
6
7
8
16 V
CC
15 A3
14 B2
13 A2
12 A1
11 B1
10 A0
9
B0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1770.1
Copyright © Harris Corporation 1997
1
CD74HC85, CD74HCT85
Functional Diagram
15
A3
13
A2
12
A1
10
A0
7
2
3
4
(A < B) OUT
(A < B) IN
(A = B) IN
(A > B) IN
6
5
(A = B) OUT
(A > B) OUT
1
14
11
9
B3
B2
B1
B0
TRUTH TABLE
CASCADING INPUTS
COMPARING INPUTS
A2, B2 A1, B1
SINGLE DEVICE OR SERIES CASCADING
OUTPUTS
A < B
A3, B3
A0, B0
A > B
A < B
A = B
A > B
A = B
A3 > B3
A3 < B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
X
X
A2 >B2
A2 < B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
X
H
L
X
H
L
A1 > B1
A1 < B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
H
L
H
L
A0 > B0
A0 < B0
A0 = B0
A0 = B0
A0 = B0
H
L
H
L
H
L
H
L
L
H
L
L
H
L
PARALLEL CASCADING
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
X
H
L
X
H
L
H
L
L
L
L
L
L
H
L
L
A2 = B2
A2 = B2S
H
H
NOTE: H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care
2
CD74HC85, CD74HCT85
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
190
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
1.9
4.4
5.9
-
-
1.9
4.4
5.9
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
4.4
5.9
-
OH
-0.02
-0.02
-
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-4
4.5
6
3.98
5.48
-
-
3.84
5.34
-
-
3.7
5.2
-
-
-5.2
0.02
0.02
0.02
4
-
-
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
0.1
0.1
0.1
0.26
0.1
0.1
0.1
0.33
0.1
0.1
0.1
0.4
OL
4.5
6
-
-
-
-
-
-
Low Level Output
Voltage
4.5
-
-
-
TTL Loads
5.2
-
6
6
-
-
-
-
0.26
-
-
0.33
-
-
0.4
V
Input Leakage
Current
I
V
or
±0.1
±1
±1
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC85, CD74HCT85
DC Electrical Specifications (Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theorectical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A3, B0-B3 and (A = B) IN
(A > B) IN, (A < B) IN
1.5
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
Propagation Delay,
A , B to (A > B) OUT,
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
t
C = 50pF
2
-
-
-
195
39
-
-
-
-
-
-
-
-
-
245
47
-
-
-
-
-
-
-
-
-
295
59
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
n
n
4.5
5
-
-
-
-
-
-
-
(A < B) OUT
C = 15pF
16
-
L
C = 50pF
6
33
175
35
-
42
240
44
-
50
265
53
-
L
A , B to (A = B) OUT
t
t
C = 50pF
2
-
n
n
PLH, PHL
L
4.5
5
-
C = 15pF
14
-
L
C = 50pF
6
30
37
45
L
4
CD74HC85, CD74HCT85
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
t
t
C = 50pF
2
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
210
42
-
ns
ns
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
C = 15pF
11
-
L
C = 50pF
6
24
120
24
-
30
150
30
-
36
180
36
-
L
(A > B) IN to (A = B) OUT
t
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C = 15pF
9
-
L
C = 50pF
L
6
20
-
26
-
31
-
Power Dissipation Capacitance
(Notes 2, 3)
C
-
5
24
PD
Output Transition Times
(Figure 1)
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
95
19
16
10
-
-
-
-
110
22
ns
ns
ns
pF
19
Input Capacitance
C
-
-
10
IN
HCT TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
t
t
C = 50pF
4.5
5
-
-
-
37
-
-
-
46
-
-
-
56
-
ns
ns
PLH, PHL
L
C = 15pF
15
L
An, Bn to (A = B) OUT
t
t
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
17
-
40
-
-
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
60
-
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
C = 15pF
L
(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
t
C = 50pF
4.5
5
30
-
38
-
45
-
PLH, PHL
L
C = 15pF
12
-
L
(A > B) IN to (A = B) OUT
t
C = 50pF
4.5
5
31
-
39
-
47
-
PLH, PHL
L
C = 15pF
13
-
L
Output Transition Times
(Figure 1)
t
, t
TLH THL
C = 50pF
L
4.5
15
19
22
Power Dissipation Capacitance
(Notes 4, 5)
C
-
5
-
-
-
26
-
-
-
-
-
-
-
-
pF
pF
PD
Input Capacitance
NOTES:
C
-
10
10
10
IN
4. C
is used to determine the dynamic power consumption, per gate/package.
2
PD
5. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
CD74HC85, CD74HCT85
Test Circuits and Waveforms
GND
(A > B) IN
(A = B) IN
(A < B) IN
V
CC
GND
A0
A1
A2
A3
B0
B1
B2
B3
A0
A1
CD74HC85
CD74HCT85
A2
LEAST SIGNIFICANT
4-BITS OF EACH WORD
A3
B0
B1
B2
B3
(A > B) IN
(A = B) IN
(A < B) IN
A4
A5
A6
A7
B4
B5
B6
B7
A4
A5
CD74HC85
A6
A7
B4
B5
B6
B7
CD74HCT85
(A > B) OUT
(A = B) OUT
(A < B) OUT
(A > B) IN
(A = B) IN
(A < B) IN
A0
A1
A2
A3
B0
B1
B2
B3
A0
A1
CD74HC85
A2
A3
B0
B1
B2
B3
CD74HCT85
MOST SIGNIFICANT
4-BITS OF EACH WORD
(A > B) OUT
(A = B) OUT
(A < B) OUT
OUTPUTS
FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS
6
Test Circuits and Waveforms
CD74HC85
B11
A11
B10
A10
B9
B3
A3
B2
CD74HCT85
A2 (A < B) OUT
B1
NC
(A = B) OUT
A1
A9
(A > B) OUT
B0
B8
A0
A8
B7
(A < B) IN
(A = B) IN
(A > B) IN
GND
A7
CD74HC85
B6
A6
B3
CD74HCT85
A3
B2
A2
B1
A1
B0
A0
B5
(A < B) OUT
(A = B) OUT
(A > B) OUT
A5
CD74HC85
B4
NC
B3
A3
B2
A2
B1
A1
B0
A0
CD74HCT85
A4
B3
A3
(A > B) OUT
(A = B) OUT
(A < B) OUT
(A < B) IN
(A = B) IN
(A > B) IN
B2
OUTPUTS
CD74HC85
GND
A2
B1
A1
B0
A0
B3
A3
B2
CD74HCT85
OUTPUTS
(A < B) IN
(A = B) IN
(A > B) IN
A2 (A < B) OUT
B1
A1
B0
A0
(A = B) OUT
(A > B) OUT
GND
(A < B) IN
(A = B) IN
(A > B) IN
VCC
GND
FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS
7
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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