CDC2351DW [TI]
1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS; 1线路至10线路时钟驱动器，具有三态输出
| 型号： | CDC2351DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
DB OR DW PACKAGE
(TOP VIEW)
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
GND
Y10
GND
23 Y1
1
24
Operates at 3.3-V V
CC
2
LVTTL-Compatible Inputs and Outputs
V
3
22
21
20
19
18
17
16
15
14
13
V
Y2
GND
Y3
Y4
GND
Y5
V
Y6
GND
CC
Y9
CC
4
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
5
OE
A
6
V
)
CC
7
P0
P1
Y8
Distributes One Clock Input to Ten Outputs
8
Outputs Have Internal Series Damping
Resistor to Reduce Transmission Line
Effects
9
10
11
12
V
CC
Y7
CC
Distributed V
Switching Noise
and Ground Pins Reduce
CC
GND
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
description
The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with
minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance
state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351
operates at nominal 3.3-V V
.
CC
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended
for customer use and should be connected to GND.
The CDC2351 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Yn
A
OE
H
L
H
L
Z
Z
L
H
L
H
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
†
logic symbol
5
EN
OE
23
21
19
18
16
14
11
9
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
6
A
4
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
5
OE
23
21
19
Y1
Y2
Y3
18
16
Y4
Y5
6
A
7
8
P0 P1
14
11
Y6
Y7
9
4
Y8
Y9
2
Y10
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
O
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
O
IK
OK
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
I
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.65 W
A
DW package . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
5.5
–12
12
V
IL
0
0
V
I
I
I
f
High-level output current
Low-level output current
Input clock frequency
Operating free-air temperature
mA
mA
MHz
°C
OH
OL
clock
100
70
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN
TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
= 3 V,
–1.2
IK
CC
CC
CC
CC
CC
CC
I
= 3 V,
I
I
= – 12 mA
= 12 mA
2
V
OH
OL
OH
OL
= 3 V,
0.8
±1
V
I
I
I
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = V
or GND
µA
mA
µA
I
I
CC
= 2.5 V
‡
V
O
–7
–70
±10
0.3
15
O
V
CC
= 3 V or 0
OZ
Outputs high
Outputs low
V
CC
= 3.6 V,
I
O
= 0,
I
mA
CC
V = V
or GND
I
CC
Outputs disabled
f = 10 MHz
0.3
C
C
V = V
I
or GND,
V
V
= 3.3 V,
= 3.3 V,
4
6
pF
pF
i
CC
CC
V
O
= V or GND,
CC
f = 10 MHz
o
CC
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
switching characteristics, C = 50 pF (see Figures 1 and 2)
L
V
T
= 3.3 V,
= 25°C
V
= 3 V to 3.6 V,
CC
A
CC
T = 0°C to 70°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.8
3.6
2.4
2.4
2.2
2.2
TYP
4.3
4.1
4.9
4.3
4.4
4.6
0.3
0.2
MAX
4.8
4.6
6.0
6.0
6.3
6.3
0.5
0.8
1
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
sk(p)
sk(pr)
r
A
Y
Y
Y
ns
ns
ns
1.8
1.8
2.1
2.1
6.9
6.9
7.1
7.3
0.5
0.8
1
OE
OE
A
A
A
A
A
Y
Y
Y
Y
Y
ns
ns
ns
ns
ns
2.5
2.5
f
switching characteristics temperature and V
coefficients over recommended operating free-air
CC
temperature and V
range (see Note 4)
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
Average temperature coefficient of low to high
propagation delay
†
†
‡
‡
t
t
t
t
(T)
(T)
(V
A
A
A
A
Y
Y
Y
Y
85
50
ps/10°C
ps/10°C
PLH
Average temperature coefficient of high to low
propagation delay
PHL
Average V
delay
coefficient of low to high propagation
ps/
100 mV
CC
)
)
–145
–100
PLH CC
Average V
delay
coefficient of high to low propagation
ps/
100 mV
CC
(V
PHL CC
†
‡
t
t
(T) and
(V ) and
PLH CC
t
(T) are virtually independent of V
t
PHL CC
.
PLH
PHL
CC
(V ) are virtually independent of temperature.
NOTE 4: These data were extracted from characterization material and are not tested at the factory.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
t /t
PLH PHL
S1
Open
6 V
S1
500 Ω
Open
GND
From Output
Under Test
t
/t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
3 V
Timing Input
0 V
VOLTAGE WAVEFORMS
t
t
h
su
3 V
0 V
Data Input
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
t
PZL
3 V
0 V
t
PLZ
Input
1.5 V
1.5 V
3 V
Output
Waveform 1
S1 at 6 V
1.5 V
t
PLH
V
V
+ 0.3 V
– 0.3 V
OL
t
PHL
V
OL
OH
(see Note B)
t
V
V
PHZ
OH
2 V
0.8 V
2 V
t
PZH
Output
1.5 V
Output
Waveform 2
S1 at GND
0.8 V
V
OL
OH
1.5 V
t
t
f
r
(see Note B)
≈ 0 V
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
A
Y1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PHL1
PHL2
PHL3
PHL4
PHL5
PHL6
PHL7
PHL8
PHL9
PLH1
PLH2
PLH3
PLH4
PLH5
PLH6
PLH7
PLH8
PLH9
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
t
t
PLH10
PHL10
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
PLHn
PHLn
B. Pulse skew, t
C. Process skew, t
, is calculated as the greater of | t
– t
PLHn PHLn
| (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).
sk(p)
, is calculated as the greater of:
sk(pr)
– The difference between the fastest and slowest of t
operating conditions
– The difference between the fastest and slowest of t
operating conditions
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
, t
, t
sk(o) sk(p) sk(pr)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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