CDC2510CPWG4 [TI]
3.3-V Phase-Lock Loop Clock Driver 24-TSSOP;
| 型号： | CDC2510CPWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
Use CDCVF2510A as a Replacement for
this Device
Designed to Meet PC SDRAM Registered
DIMM Design Support Document Rev. 1.2
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
V
2
CC
CC
Spread Spectrum Clock Compatible
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
Operating Frequency 25 MHz to 125 MHz
1Y9
1Y8
GND
GND
1Y7
1Y6
4
5
Static tPhase Error Distribution at 66 MHz
to 100 MHz is 150 ps
6
7
Drop-In Replacement for TI CDC2510A With
Enhanced Performance
8
1Y4
9
Jitter (cyc − cyc) at 66 MHz to 100 MHz is
|100 ps|
V
10
11
12
15 1Y5
CC
G
V
14
13
CC
D
Available in Plastic 24-Pin TSSOP
FBOUT
FBIN
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
D
Distributes One Clock Input to One Bank of
Ten Outputs
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
D
D
D
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
description
The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at V
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
= 3.3 V . It also
CC
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC2510C is characterized for operation from 0°C to 85°C.
For application information, see the High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039) application reports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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ꢔ
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
FUNCTION TABLE
INPUTS OUTPUTS
1Y
(0:9)
G
CLK
FBOUT
X
L
L
H
H
L
L
L
H
H
H
H
functional block diagram
11
G
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
15
16
1Y5
1Y6
1Y7
1Y8
17
20
21
12
24
CLK
PLL
13
FBIN
1Y9
23
AV
CC
FBOUT
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 85°C
CDC2510CPWR
2
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SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2510C clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
CLK
24
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBIN
G
13
11
12
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
I
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
FBOUT
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
O
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition, AV
CC
AV
CC
23
Power
can be used to bypass the PLL for test purposes. When AV
and CLK is buffered directly to the device outputs.
is strapped to ground, PLL is bypassed
CC
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply
Ground Ground
V
CC
GND
2, 10, 14, 22
6, 7, 18, 19
3
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SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, AV
Supply voltage range, V , AV
Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
< V
+0.7 V
CC
CC
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
CC
I
or low state, V (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through each V
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AV
must not exceed V .
CC
CC
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
3
MAX
UNIT
V
V
V
V
V
, AV
CC
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
V
IL
0
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
−12
12
mA
mA
°C
OH
OL
T
A
85
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
125
60%
1
UNIT
f
Clock frequency
MHz
clk
Input clock duty cycle
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
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SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
AV , V
CC CC
MIN TYP
MAX
UNIT
V
IK
Input clamp voltage
I = −18 mA
I
3 V
−1.2
V
I
I
I
I
I
I
= −100 µA
= −12 mA
= −6 mA
= 100 µA
= 12 mA
= 6 mA
MIN to MAX
3 V
V
CC
−0.2
2.1
OH
OH
OH
OL
OL
OL
V
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
V
V
OH
3 V
2.4
MIN to MAX
3 V
0.2
0.8
V
OL
3 V
0.55
V
V
V
V
V
V
= 1 V
3.135 V
3.3 V
−32
34
O
O
O
O
O
O
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
−36
40
I
mA
mA
OH
3.465 V
3.135 V
3.3 V
−12
I
OL
3.465 V
3.6 V
14
5
I
I
Input current
V = V
or GND
µA
µA
I
I
CC
V = V
Outputs: low or high
or GND,
I
O
= 0,
I
CC
§
Supply current
3.6 V
10
CC
One input at V − 0.6 V,
CC
Other inputs at V
∆I
Change in supply current
3.3 V to 3.6 V
500
µA
CC
or GND
CC
or GND
C
C
Input capacitance
Output capacitance
V = V
I CC
3.3 V
3.3 V
4
6
pF
pF
i
V
O
= V or GND
CC
o
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For I of AV and I vs Frequency (see Figures 11 and 12).
CC CC CC
switching characteristics over recommended ranges of supply voltage and operating free-air
‡
temperature, C = 30 pF (see Note 6 and Figures 1 and 2)
L
V
, AV = 3.3 V
CC
CC
FROM
PARAMETER
TO
(OUTPUT)
0.165 V
UNIT
(INPUT)/CONDITION
MIN
TYP
MAX
Phase error time − static (normalized)
CLKIN↑ = 66 MHz to 100 MHz
(See Figures 3 − 8)
FBIN↑
−150
150
ps
§
t
Output skew time
Phase error time − jitter (see Note 7)
Jitter (See Figures 9 and 10)
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
Clkin = 66 MHz to 100 MHz
F(clkin > 60 MHz)
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
200
50
ps
ps
ps
sk(o)
−50
|100|
55%
(cycle-cycle)
Duty cycle
45%
2.5
V
O
= 1.2 V to 1.8 V,
IBIS simulation
t
t
Rise time (See Notes 8 and 9)
Fall time (See Notes 8 and 9)
Any Y or FBOUT
Any Y or FBOUT
1
1
V/ns
V/ns
r
V
O
= 1.2 V to 1.8 V,
IBIS simulation
2.5
f
‡
§
These parameters are not production tested.
The t
specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (t , static − jitter ).
phase error (cycle-to-cycle)
8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 04. V to 2 V.
9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13.
Intel is a trademark of Intel Corporation.
PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.
5
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ꢔ
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500 W
50% V
CC
0.4 V
30 pF
OL
t
t
f
r
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
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SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
CDC2510C
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
20
10
200
V
= 3.3 V
CC
= 100 MHz
f
C
c
= 30pF
(LY)
= 25°C
100
T
A
See Notes A and B
0
0
Phase Error
−10
−100
−20
−200
−30
−40
−300
−400
Phase Adjustment Slope
45 50
0
5
10 15 20 25 30 35 40
C
− Lumped Feedback Capacitance at FBIN − pF
(LF)
Figure 3
CDC2510A
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
10
0
100
V
= 3.3 V
CC
= 100 MHz
f
C
c
= 30pF
(LY)
= 25°C
0
T
A
See Notes A and B
−10
−20
−100
−200
Phase Error
−30
−300
−40
−50
−400
−500
Phase
Adjustment Slope
45 50
0
5
10 15 20 25 30 35 40
C
− Lumped Feedback Capacitance at FBIN − pF
(LF)
Figure 4
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, Z = 50 Ω Phase error measured from CLK to Y
O
B. CLF = Lumped feedback capacitance at FBIN
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ꢔ
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
PHASE ERROR
PHASE ERROR
vs
vs
CLOCK FREQUENCY
SUPPLY VOLTAGE
0
−50
0
−50
V
= 3.3 V
f
= 100 MHz
= 30 pF
(LY)
CC
c
C
C
T
= 30 pF
= 0
C
C
T
(LY)
(LF)
= 0
= 25°C
(LF)
A
−100
−100
= 25°C
A
See Note A
See Note A
−150
−200
−250
−150
−200
−250
−300
−350
−400
−300
−350
−400
−450
−500
−450
−500
20
40
60
80
100
120
140
160
3.1
3.2
V
3.3
3.4
3.5
f
− Clock Frequency − MHz
c
− Supply Voltage − V
Figure 6
CC
Figure 5
CDC2510C
CDC2510A
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
−200
−300
−200
−300
V
C
= 3.3 V
= C = 30 pF
(LY) (LF)
= 25°C
CC
V
C
= 3.3 V
CC
= C
= 30 pF
(LY)
(LF)
T
A
See Notes B to D
See Notes B to D
−400
−500
−400
−500
−600
−700
−600
−700
35 45
55
65
75
85 95 105 115 125
35 45
55
65
75
85 95 105 115 125
f
− Clock Frequency − MHz
c
f
− Clock Frequency − MHz
c
Figure 7
Figure 8
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, Z = 50 Ω
O
B. Phase error measured from CLK to FBIN
C. CLY = Lumped capacitive load at Y
D. CLF = Lumped feedback capacitance at FBIN
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢀ
ꢆ ꢇꢆ ꢈꢉ ꢊꢋ ꢌꢍꢎꢈꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢊ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢉ ꢎꢒ
ꢔ
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
CDC2510C
JITTER
vs
CDC2510A
JITTER
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
400
350
300
250
700
600
500
V
C
= 3.3 V
= C = 30 pF
(LY) (LF)
= 25°C
CC
V
C
= 3.3 V
= C
= 25°C
CC
(LY)
= 30 pF
(LF)
T
A
T
A
See Notes A and B
See Notes A and B
400
300
Peak to Peak
200
150
Peak to Peak
200
100
Cycle to Cycle
Cycle to Cycle
100
0
50
0
35 45
55
f
65 75
85 95 105 115 125
35 45
55
f
65 75
85 95 105 115 125
− Clock Frequency − MHz
− Clock Frequency − MHz
c
c
Figure 9
Figure 10
ANALOG SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
16
14
12
300
AV
CC
= V = 3.465 V
CC
AV
CC
= V = 3.465 V
CC
Bias = 0/3 V
Bias = 0/3 V
C
C
= 30 pf
= 0
(LY)
(LF)
C
C
= 30 pf
= 0
250
200
150
100
(LY)
(LF)
T
= 25°C
A
T
= 25°C
A
See Notes A and B
See Notes A and B
10
8
6
4
2
0
50
0
10
30
50
70
90
110
130
150
10
30
50
70
90
110
130
150
f
− Clock Frequency − MHz
c
f
− Clock Frequency − MHz
Figure 12
c
Figure 11
NOTES: A.
B.
C
C
= Lumped capacitive load at Y
= Lumped feedback capacitance at FBIN
(LY)
(LF)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢀ
ꢆꢇ ꢆꢈꢉ ꢊꢋ ꢌ ꢍꢎꢈꢏ ꢐꢀ ꢑ ꢏꢐ ꢐ ꢊ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢉ ꢎꢒ
ꢔ
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
TI SILICON-BASED
PLL PULLDOWN IBIS I/V
TI SILICON-BASED
PLL PULLUP IBIS I/V
120
100
0
V
= 3.465 V
V
= 3.135 V
CC
High IDS
CC
Low IDS
T = 85°C
A
T
A
= 0°C
−20
I
(Intel)
max
I
(Intel)
min
80
60
40
V
= 3.3 V
CC
Nom IDS
−40
−60
T
A
= 25°C
V
= 3.3 V
CC
Nom IDS
= 25°C
T
A
V
= 3.465 V
CC
High IDS
= 0°C
V
= 3.135 V
CC
Low IDS
−80
T
A
20
0
T
A
= 85°C
I
(Intel)
2
min
I
(Intel)
max
−100
0
0.5
1
1.5
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
V
O
− Output Voltage − V
V
− Output Voltage − V
O
Figure 13
Figure 14
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDC2510CPW
CDC2510CPWG4
CDC2510CPWR
CDC2510CPWRG4
NRND
NRND
NRND
NRND
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
24
24
24
24
60
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Samples Not Available
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Samples Not Available
Samples Not Available
Samples Not Available
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDC2510CPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
CDC2510CPWR
2000
Pack Materials-Page 2
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