概述
规格参数
数据手册
替代型号CDC341DWG4 概述
1-LINE TO 8-LINE CLOCK DRIVER 1线路至8线路时钟驱动器 时钟缓冲器、驱动器、锁相环 时钟驱动器
CDC341DWG4 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | GREEN, PLASTIC, SOIC-20 | 针数： | 20 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 6 weeks | 风险等级： | 5.24 |
| Is Samacsys： | N | 系列： | 341 |
| 输入调节： | STANDARD | JESD-30 代码： | R-PDSO-G20 |
| JESD-609代码： | e4 | 长度： | 12.8 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | LOW SKEW CLOCK DRIVER |
| 最大I（ol）： | 0.048 A | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 反相输出次数： | |
| 端子数量： | 20 | 实输出次数： | 8 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP20,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 包装方法： | TUBE |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 5 V |
| 最大电源电流（ICC）： | 33 mA | Prop。Delay @ Nom-Sup： | 4.9 ns |
| 传播延迟（tpd）： | 4.9 ns | 认证状态： | Not Qualified |
| Same Edge Skew-Max（tskwd）： | 0.6 ns | 座面最大高度： | 2.65 mm |
| 子类别： | Clock Drivers | 最大供电电压 (Vsup)： | 5.25 V |
| 最小供电电压 (Vsup)： | 4.75 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | BICMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 7.5 mm | 最小 fmax： | 80 MHz |
| Base Number Matches： | 1 |
CDC341DWG4 数据手册
通过下载CDC341DWG4数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
DW PACKAGE
(TOP VIEW)
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
V
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
CC
TTL-Compatible Inputs and Outputs
1G
2G
A
1Y1
1Y2
GND
1Y3
1Y4
GND
Distributes One Clock Input to Eight
Outputs
P0
P1
Distributed V
Switching Noise
and Ground Pins Reduce
CC
V
2Y4
2Y3
CC
High-Drive Outputs (–48-mA I
,
OH
13 2Y1
12 2Y2
11 GND
48-mA I
)
OL
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
GND 10
Packaging Options Include Plastic
Small-Outline (DW) Packages
description
The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs
with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be
placed in a low state regardless of the A input.
The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for
customer use and should be strapped to GND.
The CDC341 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
1G
X
2G
X
A
L
1Y1–1Y4 2Y1–2Y4
L
L
L
L
L
L
H
H
H
H
L
H
L
L
H
L
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
†
logic symbol
2
1G
G1
G2
3
2G
19
18
16
15
1
1
1
1
1Y1
1Y2
1Y3
1Y4
4
A
13
12
9
2
2
2
2
2Y1
2Y2
2Y3
2Y4
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
2
19
1G
1Y1
1Y2
1Y3
1Y4
3
18
16
15
2G
4
A
13
12
9
2Y1
2Y2
2Y3
2Y4
8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
IK
I
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
4.75
2
MAX
UNIT
V
V
V
V
V
Supply voltage
5.25
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
CC
V
I
I
High-level output current
Low-level output current
–48
48
mA
mA
OH
OL
I
One output bank loaded
Both output banks loaded
80
f
Input clock frequency
MHz
clock
40
T
A
Operating free-air temperature
0
70
°C
NOTE 3: Unused pins (input or I/O) must be held high or low.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
†
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 5 V,
I = –18 mA
–1.2
–1.2
V
IK
I
I
I
I
I
= – 3 mA
= – 3 mA
= – 48 mA
= 48 mA
2.5
3
2.5
3
OH
OH
OH
OL
V
OH
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
2
2
0.5
V
OL
I
I
V = V
or GND
±1
±1
µA
mA
I
I
CC
= 2.5 V
O
‡
V
–50 –100 –200
–50 –200
O
Outputs high
Outputs low
2
24
3
3.5
33
V
= 5.25 V,
I
O
= 0,
CC
I
mA
pF
CC
V = V
I
or GND
CC
C
V = 2.5 V or 0.5 V
I
i
†
‡
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
switching characteristics, C = 50 pF (see Figures 1 and 2)
L
V
T
= 5 V,
= 25°C
V
CC
= 4.75 V to 5.25 V,
T = 0°C to 70°C
A
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.5
3.5
2
TYP
MAX
4.5
4.3
3.8
3.8
0.5
0.8
1
MIN
3.1
3.1
2
MAX
4.9
4.9
4
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
sk(o)
sk(p)
sk(pr)
r
A
Y
Y
ns
ns
G
2
2
4
0.3
0.6
0.6
0.9
1
A
Y
ns
A
A
Y
Y
1.5
1.5
ns
ns
f
t
performance information relative to V
and temperature variation (see Note 4)
pd
CC
from 0°C to 70°C
from 0°C to 70°C
†
Dt
Dt
Dt
Dt
Temperature drift of t
Temperature drift of t
–41 ps/10°C
PLH(TA)
PHL(TA)
PLH
PHL
†
–52 ps/10°C
28 ps/100 mV
20 ps/100 mV
‡
V
drift of t
drift of t
from 4.75 V to 5.25 V
from 4.75 V to 5.25 V
PLH(VCC)
PHL(VCC)
CC
CC
PLH
PHL
‡§
V
†
‡
Virtually independent of V
CC
Virtually independent of temperature
NOTE 4: The data extracted is from a wide range of characterization material.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
t
t
PHL
PLH
V
V
OH
2 V
1.5 V
0.8 V
1.5 V
0.8 V
Output
OL
t
r
t
f
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
A
1G
2G
1Yn
t
t
PHL1
PLH1
2Yn
t
t
PHL2
PLH2
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2)
(n = 1, 2)
PLHn
PHLn
B. Pulse skew, t
, is calculated as the greater of | t
sk(p)
– t
| (n = 1, 2).
PLHn PHLn
, is calculated as the greater of:
C. Process skew, t
sk(pr)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2) across multiple devices under identical operating conditions
(n = 1, 2) across multiple devices under identical operating conditions
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
, t
, t
sk(o) sk(p) sk(pr)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
0.610
DIM
0.410
0.510
A MAX
(10,41) (12,95) (15,49)
0.400
0.500
0.600
A MIN
(10,16) (12,70) (15,24)
4040000/D 02/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SOIC
Drawing
CDC341DBLE
CDC341DW
OBSOLETE
ACTIVE
DB
20
20
TBD
Call TI
Call TI
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC341DWG4
CDC341DWR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC341DWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC341NSR
OBSOLETE
OBSOLETE
SO
SO
NS
NS
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
CDC341NSRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CDC341DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CDC341DWR
2000
Pack Materials-Page 2
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CDC341DWG4 CAD模型
引脚图
封装焊盘图
CDC341DWG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CDC341DWRG4 | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 完全替代 |
|
| CDC341DW | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 类似代替 |
|
| CDC341DWR | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 类似代替 |
|
CDC341DWG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CDC341DWR | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 获取价格 |
|
| CDC341DWRG4 | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 获取价格 |
|
| CDC341NSR | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 获取价格 |
|
| CDC341NSRG4 | TI | 1-LINE TO 8-LINE CLOCK DRIVER | 获取价格 |
|
| CDC351 | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
| CDC351DB | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
| CDC351DBG4 | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
| CDC351DBLE | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
| CDC351DBR | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
| CDC351DBRG4 | TI | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS | 获取价格 |
|
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