CDC3RL02_16 [TI]
Low Phase-Noise Two-Channel Clock Fan-Out Buffer;
| 型号： | CDC3RL02_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Phase-Noise Two-Channel Clock Fan-Out Buffer |
| 文件： | 总15页 (文件大小：750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC3RL02
www.ti.com
SCHS371 –NOVEMBER 2009
LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER
Check for Samples: CDC3RL02
1
FEATURES
APPLICATIONS
•
•
•
•
•
•
Cellular Phones
Global Positioning Systems (GPS)
Wireless LAN
FM Radio
WiMAX
2
•
Low Additive Noise:
–
–
–149 dBc/Hz at 10-kHz Offset Phase Noise
0.37-ps (RMS) Output Jitter
•
Limited Output Slew Rate for EMI Reduction
(1- to 5-ns/Rise/Fall Time for 10-pF to 50-pF
Loads)
W-BT
•
•
Adaptive Output Stage Controls Reflection
Regulated 1.8-V Externally Available I/O
Supply
•
•
Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP
(0.8 mm × 1.6 mm)
EESD Performance Exceeds JESD 22
–
–
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model
(JESD22-C101-A Level III)
YFP PACKAGE
(TOP VIEW)
Table 1. YFP PACKAGE TERMINAL
ASSIGNMENTS
1
2
1
2
A1
B1
C1
D1
A2
B2
C2
D2
A
B
C
D
A
B
C
D
VBATT
VLDO
CLK_OUT1
CLK_REQ1
CLK_REQ2
CLK_OUT2
MCLK_IN
GND
DESCRIPTION/ORDERING INFORMATION
The CDC3RL02 is a two-channel clock fan-out buffer. It buffers a single master clock, such as a temperature
compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs
(CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an
AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has been
designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive
clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI
emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution
lines.
The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3
V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8V supply is externally available to provide regulated power to
peripheral devices such as a TCXO.
The CDC3RL02 is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering
with minimal additive phase noise and fan-out capabilities. It is offered in a 0.4-mm pitch wafer-level chip-scale
(WCSP) package (0.8 mm × 1.6 mm) and is optimized for very low standby current consumption.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
CDC3RL02
SCHS371 –NOVEMBER 2009
www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1) (2)
NanoStar™ WCSP – YFP
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
–40°C to 85°C
Tape and reel
CDC3RL02YFPR _ _ _ 4 L _
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
TERMINAL FUNCTIONS
NO.
A1
A2
B1
B2
C1
C2
D1
D2
NAME
VBATT
I/O
I
DESCRIPTION
Input to internal LDO
Clock output 1
CLK_OUT1
VLDO
O
O
I
1.8 V I/O supply for CDC3RL02 and external TCXO
Clock request from peripheral 2
Master clock input
CLK_REQ1
MCLK_IN
CLK_REQ2
GND
I
I
Clock request from peripheral 1
Ground
–
O
CLK_OUT2
Clock output 2
Table 2. FUNCTION TABLE
INPUTS
CLK_REQ1 CLK_REQ2
OUTPUTS
MCLK_IN
X
CLK_OUT1 CLK_OUT2
L
L
L
H
L
L
L
CLK
L
CLK
L
H
H
CLK
CLK
CLK
H
CLK
CLK
LOGIC DIAGRAM
V
V
LDO
BATT
LDO
V
GND
CLK_OUT1
CLK_REQ1
CC
CC
EN
EN
V
MCLK_IN
CLK_OUT2
CLK_REQ2
Switch/
Decoder
2
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CDC3RL02
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SCHS371 –NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
MAX
7
UNIT
VBATT voltage range(2)
V
CLK_REQ_1/2, MCLK_IN
VLDO, CLK_OUT_1/2(2)
VBATT + 0.3
VBATT + 0.3
Voltage range(3)
V
IIK
IO
Input clamp current at VBATT,
CLK_REQ_1/2, and MCLK_IN
VI < 0
–50
mA
Continuous output current
CLK_OUT1/2
±20
±50
2000
1000
200
150
85
mA
mA
Continuous current through GND, VBATT, VLDO
Human-Body Model
Charged-Device Model
Machine Model
ESD rating
V
TJ
Operating virtual junction temperature
Operating ambient temperature range
Storage temperature range
–40
–40
–55
°C
°C
°C
TA
Tstg
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
2.3
0
MAX UNIT
VBATT
VI
Input voltage
5.5
1.89
1.8
V
V
Input voltage
MCLK_IN, CLK_REQ1/2
CLK_OUT1/2
VO
Output voltage
0
V
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output current, DC current
Low-level output current, DC current
CLK_REQ1/2
1.3
0
1.89
0.5
V
CLK_REQ1/2
V
IOH
IOL
–8
mA
mA
8
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2009, Texas Instruments Incorporated
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SCHS371 –NOVEMBER 2009
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UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.8
MAX
LDO
VOUT
LDO output voltage
IOUT = 50 mA
1.71
1
1.89
10
V
CLDO
External load capacitance
Short circuit output current
Peak output current
μF
IOUT(SC)
I0UT(PK)
RL = 0 Ω
100
mA
mA
VBATT = 2.3 V, VLDO = VOUT – 5%
100
fIN = 217 Hz and
1 kHz
60
40
PSR
Power supply rejection
VBATT = 2.3V, IOUT = 2 mA,
dB
fIN = 3.25 MHz
VBATT = 2.3 V , CLDO = 1 μF, CLK_REQ_n to
VLDO = 1.71 V
0.2
tsu
LDO startup time
ms
VBATT = 5.5 V , CLDO = 10 μF, CLK_REQ_n to
VLDO = 1.71 V
1
Power Consumption
ISB
Standby current
Device in standby (all VCLK_REQ_n = 0 V)
Device active but not switching
fIN = 26 MHz, CLOAD = 50 pF
0.2
0.4
4.2
1
1
μA
mA
mA
ICCS
IOB
Static current consumption
Output buffer average current
Output power dissipation
capacitance
CPD
fIN = 26 MHz
44
1
pF
MCLK_IN Input
MCLK_IN, CLK_REQ_1/2
leakage current
II
VI = VLDO or GND
μA
CI
RI
fIN
MCLK_IN capacitance
MCLK_IN impedance
MCLK_IN frequency range
fIN = 26 MHz
fIN = 26 MHz
4.75
6
pF
kΩ
10
26
52
MHz
MCLK_IN LVCMOS Source
Additive phase noise
Additive jitter
1-kHz offset
–140
–149
–153
–148
0.37
10-kHz offset
fIN = 26 MHz, tr/tf ≤ 1 ns
dBc/Hz
100-kHz offset
1-MHz offset
fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz
ps (rms)
MCLK_IN to CLK_OUT_n
propagation delay
tDL
11
50
ns
%
DCL
Output duty cycle
fIN = 26 MHz, DCIN = 50%
45
55
4
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SCHS371 –NOVEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCLK_IN Sinusoidal Source
VMA
Input amplitude
0.3
1.8
V
1-kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
1-kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
–141
–149
–152
–148
–139
–146
–150
–146
fIN = 26 MHz, VMA = 1.8 VPP
Additive phase noise
dBc/Hz
fIN = 26 MHz, VMA = 0.8 VPP
ps
(RMS)
Additive jitter
fIN = 26 MHz, VMA = 1.8 VPP, BW = 10–5 MHz
0.41
MCLK_IN to CLK_OUT_1/2
propagation delay
tDS
12
50
ns
%
DCs
Output duty cycle
fIN = 26 MHz, VMA > 1.8 VPP
45
55
CLK_OUT_N Outputs
tr
20% to 80% rise time
CL = 10 pF to 50 pF
CL = 10 pF to 50 pF
1
1
5.2
5.2
0.5
ns
ns
ns
tf
20% to 80% fall time
tsk
Channel-to-channel skew
CL = 10 pF to 50 pF (CL1 = CL2
)
–0.5
–0.1
1.2
IOH = –100 μA, reference to VLDO
IOH = –8 mA
VOH
High-level output voltage
Low-level output voltage
V
V
IOL = 20 μA
0.2
VOL
IOL = 8 mA
0.55
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CDC3RL02
SCHS371 –NOVEMBER 2009
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TYPICAL PERFORMANCE
ADDITIVE PHASE NOISE
SUPPLY CURRENT
vs
vs
OFFSET FREQUENCY
INPUT AMPLITUDE
-90
-100
-110
-120
-130
-140
-150
-160
-170
3.54
VBATT = 3.3 V
VBATT = 3.3 V
CVLDO = 1 µF
3.53
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.52
CBATT = 0.1 µF
COUT = 30 pF
3.51
3.50
3.49
3.48
3.47
3.46
3.45
3.44
3.43
3.42
3.41
3.40
3.39
3.38
TA = 85°C
TA = 25°C
Square Wave 1.8 V 1 µF
Sine Wave 0.8 Vpp 1 µF
TA = -40°C
Sine Wave 1.8 Vpp 1 µF
0.3
0.6
0.9
1.2
1.5
1.8
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Offset Frequency (Hz)
Input Amplitude (Vpp)
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
INPUT FREQUENCY
SUPPLY VOLTAGE
8
7
6
5
4
3
2
1
0
3.50
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
VBATT = 3.3 V
TA = -40°C
CVLDO = 1 µF
3.49
3.48
3.47
3.46
3.45
3.44
3.43
3.42
3.41
3.40
3.39
3.38
3.37
3.36
CBATT = 0.1 µF
COUT = 30 pF
TA = 25°C
TA = 85°C
TA = 85°C
TA = 25°C
TA = -40°C
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
10
20
30
40
50
60
70
VBATT (V)
Frequency (MHz)
6
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SCHS371 –NOVEMBER 2009
TYPICAL PERFORMANCE (continued)
STANDBY CURRENT
POWER SUPPLY REJECTION
vs
vs
TEMPERATURE
INPUT FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
200
180
160
140
120
100
80
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
5.5 V
3.3 V
2.3 V
60
40
20
0
-40
-15
10
35
60
85
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Temperature (°C)
SINE-WAVE INPUT
vs
RISE TIME
vs
SQUARE-WAVE OUTPUT
LOAD
2.4
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
VBATT = 3.3 V CVLDO = 1 µF
CBATT = 0.1 µF COUT = 30 pF
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
TA = 85°C
TA = 25°C
TA = -40°C
MCLK_IN
10 20
CLK_OUT1
0
10
20
30
40
50
60
70
0
30
40
50 60
70
80 90 100
Time (ns)
CLOAD (pF)
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SCHS371 –NOVEMBER 2009
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TYPICAL PERFORMANCE (continued)
FALL TIME
vs
LOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VBATT = 3.3 V
CVLDO = 1 µF
TA = 85°C
CBATT = 0.1 µF
COUT = 30 pF
TA = 25°C
TA = -40°C
0
10
20
30
CLOAD (pF)
DIGITAL CROSS-TALK SCOPE SHOT
40
50
60
70
MCLK_IN
0.5 V/div
CLK_OUT1
0.5 V/div
CLK_OUT2
10 mV/div
0
20
40
60
80
100
120
140
160
180
200
Time (ns)
8
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SCHS371 –NOVEMBER 2009
APPLICATION INFORMATION
Typical Application
The CDC3RL02 is ideal for use in mobile applications as shown in Figure 1. In this example, a single low noise
TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral
independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2).
When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode,
the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO will be unpowered.
V
V
BATT
LDO
LDO
2.2 µF
1 µF
Li
GPS
CLK_REQ_1
CLK_OUT_1
TCXO REQ
TCXO CLK
MCLK_IN
CLK_REQ_2
CLK_OUT_2
TCXO REQ
TCXO CLK
TCXO
WLAN
CDC3RL02
GND
Figure 1. Mobile Application
When either peripheral requests the clock, the CDC3RL02 will enable the LDO and power the TCXO. The TCXO
output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the
requested output.
Input Clock Squarer
Figure 2 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or sine
wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the
CDC3RL02 without an external capacitor.
MCLK _IN
C
MCLK
Figure 2. Input Stage
Any external component added in the series path of the clock signal will potentially add phase noise and jitter.
The error source associated with the internal decoupling capacitor is included in the specification of the
CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 52 MHz for specified
functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude
is 0.8 VPP for specified performance. Amplitudes as low as 0.3 VPP are acceptable but with reduced phase noise
and jitter performance.
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Output Stage
Each output drives 1.8-V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within 1
to 5ns with load capacitance between 10 pF and 50 pF. Fast slew rates introduce EMI into the system. Each
output buffer limits EMI by keeping the rise/fall time above 1 ns. Slow rise/fall times can induce additive phase
noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall time
below 5 ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage level
of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions. Each
output is active low when not requested to avoid false clocking of the load device.
LDO
A low noise 1.8-V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally
available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock
source for optimum phase noise performance. The input range of the LDO allows the device to be powered
directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,
the device enters a low power shutdown mode consuming less than 1 μA from the battery. The LDO requires an
output decoupling capacitor in the range of 1 μF to 10 μF for compensation and high frequency PSR. This
capacitor must stay within the specified range over the entire operating temperature range. An input bypass
capacitor of 1 μF or larger is recommended.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CDC3RL02YFPR
ACTIVE
DSBGA
YFP
8
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 85
4L2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDC3RL02YFPR
DSBGA
YFP
8
3000
180.0
8.4
0.9
1.75
0.6
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFP
SPQ
Length (mm) Width (mm) Height (mm)
220.0 220.0 34.0
CDC3RL02YFPR
8
3000
Pack Materials-Page 2
D: Max = 1.59 mm, Min = 1.53 mm
E: Max = 0.79 mm, Min = 0.73 mm
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