CDC421A100RGER [TI]
Fully-Integrated, Fixed-Frequency, Low-Jitter Crystal Oscillator Clock Generator; 完全集成的固定频率低抖动晶振时钟发生器
| 型号： | CDC421A100RGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fully-Integrated, Fixed-Frequency, Low-Jitter Crystal Oscillator Clock Generator |
| 文件： | 总15页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC421AXXX
www.ti.com ....................................................................................................................................................................................................... SCAS875–MAY 2009
Fully-Integrated, Fixed-Frequency, Low-Jitter
Crystal Oscillator Clock Generator
1
FEATURES
APPLICATIONS
•
Low-Cost, Low-Jitter Frequency Multiplier
2
•
Single 3.3-V Supply
•
High-Performance Clock Generator,
Incorporating Crystal Oscillator Circuitry with
Integrated Frequency Synthesizer
DESCRIPTION
The
CDC421Axxx
is
a
high-performance,
low-phase-noise clock generator. It has an integrated
low-noise, LC-based voltage-controlled oscillator
(VCO) that operates within the 1.75 GHz to 2.35 GHz
frequency range. It has an integrated crystal oscillator
that operates in conjunction with an external AT-cut
crystal to produce a stable frequency reference for a
•
•
Low Output Jitter: As low as 380 fs (RMS
integrated between 10 kHz to 20 MHz)
Low Phase Noise at 312.5 MHz:
–
Less than –120 dBc/Hz at 10 kHz and
–147 dBc/Hz at 10-MHz offset from carrier
phase-locked
synthesizer. The output frequency (fOUT
proportional to the frequency of the input crystal
(fXTAL).
loop
(PLL)-based
frequency
is
•
•
Supports Crystal or LVCMOS Input
Frequencies at 31.25 MHz, 33.33 MHz, and
35.42 MHz
)
Output Frequencies: 100 MHz, 106.25 MHz,
125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and
312.5 MHz
The device operates in 3.3-V supply environment and
is characterized for operation from –40°C to +85°C.
The CDC421Axxx is available in a QFN-24 4-mm ×
4-mm package.
•
•
Differential Low-Voltage Positive Emitter
Coupled Logic (LVPECL) Outputs
The CDC421Axxx differs from the CDC421xxx in
the following ways:
Fully-Integrated Voltage-Controlled Oscillator
(VCO): Runs from 1.75 GHz to 2.35 GHz
•
Device Startup
•
•
•
•
•
Typical Power Consumption: 300 mW
Chip Enable Control Pin
The CDC421Axxx has an improved startup circuit
to enable correct operation for all power-supply
ramp times.
Available in 4-mm × 4-mm QFN-24 Package
ESD Protection Exceeds 2 kV (HBM)
Industrial Temperature Range: –40°C to +85°C
Loop Filter
Crystal
Oscillator
Input
CLK
External
Crystal
VCO
Feedback
Divider
NCLK
CDC421Axxx
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
CDC421AXXX
SCAS875–MAY 2009 ....................................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
INPUT
OUTPUT
FREQUENCY OR
CRYSTAL
VALUE (MHz)
FREQUENCY FOR
SPECIFIED INPUT
FREQUENCY (MHz)
PACKAGE-
LEAD
PACKAGE
MARKING
ORDERING
INFORMATION
TRANSPORT MEDIA,
QUANTITY
PRODUCT
CDC421A100RGET
CDC421A100RGER
CDC421A106RGET
CDC421A106RGER
CDC421A125RGET
CDC421A125RGER
CDC421A156RGET
CDC421A156RGER
CDC421A212RGET
CDC421A212RGER
CDC421A250RGET
CDC421A250RGER
CDC421A312RGET
CDC421A312RGER
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 2500
CDC421A100
33.3333
35.4167
31.2500
31.2500
35.4167
31.2500
31.2500
100.00
106.25
125.00
156.25
212.50
250.00
312.50
QFN-24
QFN-24
QFN-24
QFN-24
QFN-24
QFN-24
QFN-24
421A100
421A106
421A125
421A156
421A212
421A250
421A312
CDC421A106
CDC421A125
CDC421A156
CDC421A212
CDC421A250
CDC421A312
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
CDC421Axxx
–0.5 to 4.6
–0.5 to VCC to +0.5
–50
UNIT
V
VCC
VI
Supply voltage(2)
Voltage range for all other input pins(2)
V
IO
Output current for LVPECL
mA
kV
°C
°C
°C
ESD
TA
Electrostatic discharge (HBM)
2
Specified free-air temperature range (no airflow)
Maximum junction temperature
Storage temperature range
–40 to +85
+125
TJ
TSTG
–65 to +150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN
3.0
NOM
MAX UNIT
VCC
TA
Supply voltage
3.30
3.60
+85
V
Ambient temperature (no airflow, no heatsink)
–40
°C
2
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CDC421AXXX
www.ti.com ....................................................................................................................................................................................................... SCAS875–MAY 2009
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
CDC421Axxx
PARAMETER
Supply voltage
Total current
TEST CONDITIONS
MIN
TYP
3.30
91
MAX
3.60
110
UNIT
V
VCC
IVCC
3.00
mA
LVPECL OUTPUT
fCLK
VOH
VOL
|VOD
tR
Output frequency
100
VCC – 1.20
VCC – 2.17
407
312.5
VCC – 0.81
VCC – 1.36
1076
MHz
LVPECL high-level output voltage
LVPECL low-level output voltage
LVPECL differential output voltage
Output rise time
V
V
|
mV
ps
20% to 80% of VOUT(PP)
20% to 80% of VOUT(PP)
230
230
tF
Output fall time
ps
Duty cycle of the output waveform
RMS jitter
45
55
1
%
tj
10 kHz to 20 MHz
ps, RMS
LVCMOS INPUT
VIL, CMOS
Low-level CMOS input voltage
High-level CMOS input voltage
Low-level CMOS input current
High-level CMOS input current
VCC = 3.3 V
0.3 × VCC
V
V
VIH, CMOS
IL, CMOS
VCC = 3.3 V
0.7 × VCC
VCC = VCC, max, VIL = 0.0 V
VCC = VCC, min, VIH = 3.7 V
–200
200
µA
µA
IH, CMOS
FUNCTIONAL BLOCK DIAGRAM
XIN 1
XIN 2
Crystal
Oscillator
Loop Filter
PFD/
Charge Pump
Output
Divider
VCO
Prescaler
Feedback
Divider
Figure 1. CDC421Axxx: High-Level Block Diagram
Copyright © 2009, Texas Instruments Incorporated
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CDC421AXXX
SCAS875–MAY 2009 ....................................................................................................................................................................................................... www.ti.com
DEVICE INFORMATION
RGE PACKAGE
QFN-24
(TOP VIEW)
1
2
3
4
5
6
18 NC
17 VCC
16 VCC
15 NC
14 NC
13 NC
CE
NC
NC
NC
NC
NC
Thermal Pad
(Bottom Side)
CDC421AXXX
CDC421Axxx Pin Descriptions
TERMINAL
NAME
ESD
PROTECTION
NO.
16, 17
8, 9
TYPE
Power
Ground
I
DESCRIPTION
VCC
GND
XIN1
Y
Y
Y
3.3-V power supply
Ground
21
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
other end of the crystal.
In LVCMOS single-ended driven mode, XIN1 (pin 21) acts as input reference
and XIN2 should connect to GND.
XIN2
CE
22
1
I
I
N
Y
Chip enable (LVCMOS input)
CE = 1 enables the device and the outputs.
CE = 0 disables all current sources (LVPECLP = LVPECLN = Hi-Z).
High-speed positive differential LVPECL output. (Outputs are enabled by CE
pin.)
OUTP
OUTN
NC
10
7
O
O
Y
Y
Y
High-speed negative differential LVPECL output. (Outputs are enabled by CE
pin.)
2–6, 11–15,
18–20, 23, 24
TI test pin. Do not connect; leave floating.
—
4
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CDC421AXXX
www.ti.com ....................................................................................................................................................................................................... SCAS875–MAY 2009
JITTER CHARACTERISTICS IN INPUT CLOCK MODE
Jitter characterization tests are performed using an LVCMOS input signal driving the CDC421Axxx device, as
Figure 2 illustrates.
0.1 pF
Phase Noise
Analyzer
XIN 1
CDC421Axxx
50 W
XIN 2
100 pF
150 W
150 W
50 W
Figure 2. Jitter Test Configuration for an LVTTL Input Driving CDC421Axxx
When the CDC421Axxx is referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33 MHz, and
35.4167 MHz, Table 1 to Table 7 list the measured SSB phase noise of all the outputs supported by the
CDC421Axxx device (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz)
from 100 Hz to 20 MHz from the carrier.
Table 1. Phase Noise Data with LVCMOS Input of 33.3333 MHz and LVPECL Output at 100.00 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–111
–121
–131
–133
–142
–149
–149
507
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
35.33
11.54
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 33.3333 MHz, output frequency = 100.00 MHz.
Table 2. Phase Noise Data with LVCMOS Input of 35.4167 MHz and LVPECL Output at 106.25 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–112
–121
–125
–129
–142
–151
–151
530
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
30.39
11
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 35.4167 MHz, output frequency = 106.25 MHz.
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CDC421AXXX
SCAS875–MAY 2009 ....................................................................................................................................................................................................... www.ti.com
Table 3. Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 125.00 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–108
–118
–127
–130
–139
–147
–147
529
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
47.47
25.2
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 31.2500 MHz, output frequency = 125.00 MHz.
Table 4. Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 156.25 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–106
–117
–126
–128
–139
–147
–147
472
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
31.54
9.12
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 31.2500 MHz, output frequency = 156.25 MHz.
Table 5. Phase Noise Data with LVCMOS Input of 35.4167 MHz and LVPECL Output at 212.50 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–105
–115
–119
–123
–135
–148
–148
512
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
33.96
13.78
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 35.4167 MHz, output frequency = 212.50 MHz.
6
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CDC421AXXX
www.ti.com ....................................................................................................................................................................................................... SCAS875–MAY 2009
Table 6. Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 250.00 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–105
–112
–121
–124
–134
–148
–149
420
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
36.98
18.52
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 31.2500 MHz, output frequency = 250.00 MHz.
Table 7. Phase Noise Data with LVCMOS Input of 31.2500 MHz and LVPECL Output at 312.50 MHz(1)
PARAMETER
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
MIN
TYP
–102
–111
–120
–123
–135
–147
–147
378
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Tj
29.82
11
ps
Dj
Deterministic jitter
ps
(1) Phase noise specifications under following conditions: input frequency = 31.2500 MHz, output frequency = 312.50 MHz.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2009
PACKAGING INFORMATION
Orderable Device
CDC421A100RGER
CDC421A100RGET
CDC421A106RGER
CDC421A106RGET
CDC421A125RGER
CDC421A125RGET
CDC421A156RGER
CDC421A156RGET
CDC421A212RGER
CDC421A212RGET
CDC421A250RGER
CDC421A250RGET
CDC421A312RGER
CDC421A312RGET
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2009
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDC421A100RGER
CDC421A100RGET
CDC421A106RGER
CDC421A106RGET
CDC421A125RGER
CDC421A125RGET
CDC421A156RGER
CDC421A156RGET
CDC421A212RGER
CDC421A212RGET
CDC421A250RGER
CDC421A250RGET
CDC421A312RGER
CDC421A312RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDC421A100RGER
CDC421A100RGET
CDC421A106RGER
CDC421A106RGET
CDC421A125RGER
CDC421A125RGET
CDC421A156RGER
CDC421A156RGET
CDC421A212RGER
CDC421A212RGET
CDC421A250RGER
CDC421A250RGET
CDC421A312RGER
CDC421A312RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
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