CDC421XXX [TI]
FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR; 完全集成的固定频率低抖动，晶体振荡器的时钟发生器
| 型号： | CDC421XXX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR |
| 文件： | 总18页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC421xxx
www.ti.com
SLAS540–APRIL 2007
FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK
GENERATOR
FEATURES
•
Output Frequencies: 100 MHz, 106.25 MHz,
125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz,
and 312.5 MHz
•
Single 3.3 V Supply
•
High-Performance Clock Generator,
Incorporating Crystal Oscillator Circuitry With
Integrated Frequency Synthesizer
•
•
Differential Low-Voltage Positive Emitter
Coupled Logic (LVPECL) Output
Fully Integrated Voltage-Controlled Oscillator
(VCO) Running from 1.75 GHz to 2.35 GHz
•
•
Low Output Jitter, as Low as 380 fs (rms
integrated between 10 kHz–20 MHz)
•
•
•
•
•
Typical Power Consumption 300 mW
Chip-Enable Control Pin
Low Phase Noise at 312.5 MHz, Less Than
–120 dBc/Hz at 10 kHz and –147 dBc/Hz at 10
MHz Offset From the Carrier
QFN-24 Package
•
Supports Crystal Frequencies or LVCMOS
ESD Protection Exceeds 2 kV HBM
Industrial Temperature Range –40°C to 85°C
Input Frequencies at 31.25 MHz, 33.33 MHz,
and 35.42 MHz
A
A
A
A
APPLICATIONS
•
Low-Cost, Low-Jitter Frequency Multiplier
External Crystal
Loop Filter
Crystal
Oscillator
Input
CLK
VCO
Feedback
Divider
NCLK
B0216-02
DESCRIPTION
CDC421xxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based
voltage-controlled oscillator (VCO) that operates within the 1.75 GHz–2.35 GHz frequency range. It has an
integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable
frequency reference for the PLL-based frequency synthesizer. The output frequency (fout) is proportional to the
frequency of the input crystal (fxtal).
The device operates in a 3.3 V supply environment and is characterized for operation from –40°C to 85°C.
CDC421xxx is available in a QFN-24 package.
A high-level block diagram of the CDC421xxx is shown in Figure 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDC421xxx
www.ti.com
SLAS540–APRIL 2007
XIN 1
Crystal
Oscillator
Loop Filter
XIN 2
PFD/
Charge Pump
Output
Divider
VCO
Prescaler
Feedback
Divider
B0230-01
Figure 1. High-Level Block Diagram of the CDC421xxx
PACKAGE (QFN-24)
The CDC421xxx is packaged in a QFN-24 terminal package. The QFN package footprint is shown. Terminal
locations and numbers are shown in Figure 2.
RGE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
18
17
16
15
14
13
CE
NC
NC
NC
NC
NC
NC
VCC
VCC
NC
NC
NC
CDC421xxx
P0024-06
Figure 2. Pinout of the CDC421xxx QFN-24 Package
The terminal functions table shows the terminal descriptions for the CDC421xxx QFN-24 package.
Table 1. TERMINAL FUNCTIONS
TERMINAL
NO.
ESD
PROTECTION
TYPE
DESCRIPTION
NAME
VCC
16, 17
8, 9
Power
GND
Y
Y
3.3V power supply
Ground
GND
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
other end of the crystal. In LVCMOS single-ended driven mode, XIN1 (pin 21) acts
as input reference and XIN2 should connect to GND.
XIN 1
XIN 2
21
22
I
I
Y
N
2
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CDC421xxx
www.ti.com
SLAS540–APRIL 2007
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
ESD
PROTECTION
TYPE
DESCRIPTION
NAME
NO.
Chip enable (LVCMOS input)
CE
1
I
Y
CE = 1 enables the device and the outputs.
CE = 0 disables all current sources (LVPECLP = LVPECLN = Hi-Z).
OUTP
OUTN
10
7
O
O
Y
Y
High-speed positive differential LVPECL output. (Outputs are enabled by CE )
High-speed negative differential LVPECL output. (Outputs are enabled by CE )
2–6, 11–15,
18–20, 23,
24
NC
I or O
Y
TI test pin. Do not connect; leave floating.
DEVICE SELECTION
The CDC421xxx device is an LVPECL low-phase-noise clock generator designed to work with a low-frequency
AT-crystal oscillator of a single-ended LVCMOS.
Table 2. Device Selection Table for CDC421xxx
CDC421xxx
ORDERING
OUTPUT FREQUENCY FOR
THE SPECIFIED INPUT
FREQUENCY (MHz)
INPUT FREQUENCY OR
CRYSTAL VALUE (MHz)
PACKAGE
DEVICE
MARKING
PART NUMBER
CDC421100RGER
CDC421100RGET
CDC421106RGER
CDC421106RGET
CDC421125RGER
CDC421125RGET
CDC421156RGER
CDC421156RGET
CDC421212RGER
CDC421212RGET
CDC421250RGER
CDC421250RGET
CDC421312RGER
CDC421312RGET
421100
421100
421106
421106
421125
421125
421156
421156
421212
421212
421250
421250
421312
421312
QFN-24 tape and reel
33.3333
33.3333
35.4167
35.4167
31.2500
31.2500
31.2500
31.2500
35.4167
35.4167
31.2500
31.2500
31.2500
31.2500
100.00
100.00
106.25
106.25
125.00
125.00
156.25
156.25
212.50
212.50
250.00
250.00
312.50
312.50
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
QFN-24 tape and reel
QFN-24 small tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.5 to 4.6
UNIT
V
VCC
VI
Supply voltage(2)
Voltage range for all other input pins(2)
–0.5 to VCC + 0.5
–50
V
IO
Output current for LVPECL
mA
V
Electrostatic discharge (HBM)
Characterized free-air temperature range (no airflow)
Maximum junction temperature
Storage temperature range
2 k
TA
–40 to 85
125
°C
°C
°C
TJ
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
3
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CDC421xxx
www.ti.com
SLAS540–APRIL 2007
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
VCC
TA
Supply voltage
3.3
V
Ambient temperature, no airflow, no heat sink
–40
85
°C
ELECTRICAL CHARACTERISTICS
over recommended operating conditions for CDC421xxx device
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
TYP
MAX
3.6
UNIT
V
VCC
3
3.3
91
IVCC
Total current at 3.3 V
3.3 V, 312.5 MHz
110
mA
LVPECL OUTPUT
fCLK
VOH
VOL
Output frequency
100
VCC – 1.20
VCC – 2.17
407
312.5
VCC – 0.81
VCC – 1.36
1076
MHz
V
LVPECL high-level output voltage
LVPECL low-level output voltage
LVPECL differential output voltage
Output rise time
V
|VOD
|
mV
ps
tr
tf
20% to 80% of VOUTpp
80% to 20% of VOUTpp
170
170
Output fall time
ps
Duty cycle of the output waveform
45%
55%
LVCMOS INPUT
VIL,CMOS
Low-level CMOS input voltage
High-level CMOS input voltage
Low-level CMOS input current
High-level CMOS input current
VCC = 3.3 V
0.3 VCC
V
V
VIH,CMOS
VCC = 3.3 V
0.7 VCC
IL,CMOS
VCC = VCC max, VIL = 0 V
VCC = VCC min, VIH = 3.7 V
–200
200
µA
µA
IH,CMOS
4
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CDC421xxx
www.ti.com
SLAS540–APRIL 2007
JITTER CHARACTERISTICS IN INPUT CLOCK MODE
The jitter characterization test is performed using an LVCMOS input signal driving the CDC421xxx device.
0.1 mF
Phase Noise
Analyzer
XIN 1
CDC421xxx
50 W
XIN 2
100 pF
150 W
150 W
150 W
S0246-02
Figure 3. Jitter Test Configuration for an LVTTL Input Driving CDC421xxx
For the cases of the CDC421xxx being referenced by an external, clean LVCMOS input of 31.25 MHz, 33.33
MHz and 35.4167 MHz, the following tables list the measured SSB phase noise of all the outputs supported by
the CDC421xxx device, (100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz)
from 100 Hz to 20 MHz from the carrier.
Table 3. Phase Noise Parameters With LVCMOS Input of 33.3333 MHz and LVPECL Output at 100.00 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 33.3333 MHz, fout = 100.00 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase Noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–111
–121
–131
–133
–142
–149
–149
507
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
35.33
11.54
ps
Dj
Deterministic jitter
ps
Table 4. Phase Noise Parameters With LVCMOS Input of 35.4167 MHz and LVPECL Output at 106.25 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin= 35.4167 MHz , fout = 106.25 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–112
–121
–125
–129
–142
–151
–151
530
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
30.39
11
ps
Dj
Deterministic jitter
ps
5
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CDC421xxx
www.ti.com
SLAS540–APRIL 2007
Table 5. Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 125.00 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 31.2500 MHz, fout = 125.00 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–108
–118
–127
–130
–139
–147
–147
529
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
47.47
25.2
ps
Dj
Deterministic jitter
ps
Table 6. Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 156.25 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 31.2500 MHz, fout = 156.25 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–106
–117
–126
–128
–139
–147
–147
472
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
31.54
9.12
ps
Dj
Deterministic jitter
ps
Table 7. Phase Noise Parameters With LVCMOS Input of 35.4167 MHz and LVPECL Output at 212.50 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 35.4167 MHz, fout = 212.50 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–105
–115
–119
–123
–135
–148
–148
512
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
33.96
13.78
ps
Dj
Deterministic jitter
ps
6
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CDC421xxx
www.ti.com
SLAS540–APRIL 2007
Table 8. Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 250.00 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 31.2500 MHz, fout = 250.00 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–103
–112
–121
–124
–134
–148
–149
420
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
36.98
18.52
ps
Dj
Deterministic jitter
ps
Table 9. Phase Noise Parameters With LVCMOS Input of 31.2500 MHz and LVPECL Output at 312.50 MHz
PARAMETER
MIN
TYP
MAX
UNIT
Phase Noise Specifications Under Following Conditions: fin = 31.2500 MHz, fout = 312.50 MHz
phn100
phn1K
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
Total jitter
–102
–111
–120
–123
–135
–147
–147
378
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Tj
29.82
11
ps
Dj
Deterministic jitter
ps
7
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PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
4.3
B0 (mm)
4.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
CDC421100RGER
CDC421100RGET
CDC421106RGER
CDC421106RGET
CDC421125RGER
CDC421125RGET
CDC421156RGER
CDC421156RGET
CDC421212RGER
CDC421212RGET
CDC421250RGER
CDC421250RGET
CDC421312RGER
CDC421312RGET
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
330
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12 PKGORN
T2TR-MS
P
180
330
180
330
180
330
180
330
180
330
180
330
180
12
12
12
12
12
12
12
12
12
12
12
12
12
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CDC421100RGER
CDC421100RGET
CDC421106RGER
CDC421106RGET
CDC421125RGER
CDC421125RGET
CDC421156RGER
CDC421156RGET
CDC421212RGER
CDC421212RGET
CDC421250RGER
CDC421250RGET
CDC421312RGER
CDC421312RGET
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
24
24
24
24
24
24
24
24
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
MLA
346.0
190.0
346.0
190.0
346.0
190.0
346.0
190.0
346.0
190.0
346.0
190.0
346.0
190.0
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
29.0
31.75
29.0
31.75
29.0
31.75
29.0
31.75
29.0
31.75
29.0
31.75
29.0
31.75
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 4
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