CDC9842 [TI]
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER;
| 型号： | CDC9842 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER PC 驱动 |
| 文件： | 总7页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
DW PACKAGE
(TOP VIEW)
Provides System Clock Solution for
Pentium /82430X/82430VX and
PentiumPro 82440FX Chipsets
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
REF0
REF1
CC
X1
Four Host-Clock Outputs With
Programmable Frequency (50 MHz, 60 MHz
and 66 MHz)
2
3
X2
V
CC
4
GND
OE
HCLK0
HCLK1
REF2
SBCLK
GND
PCLK0
PCLK1
Six PCI Clock Outputs at Half-CPU
Frequency
5
6
One 48-MHz Universal Serial Bus (USB)
Clock Output
7
8
V
CC
Three 14.318-MHz Reference Clock Outputs
9
HCLK2
HCLK3
GND
SEL1
SEL0
V
CC
10
11
12
13
14
PCLK2
PCLK3
GND
PCLK4
PCLK5
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Locked
Loops Eliminate the Need for External
Components
V
CC
Operates at 3.3 V
CC
Packaged in Plastic Small-Outline Package
description
The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to
support Pentium /82430X/82430VXandPentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn) are
programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs.
Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from
the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and
three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided.
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the
X1 input instead of a crystal input.
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency.
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock
frequency is derived directly from the host-clock frequency. The PLL circuit can be bypassed in the TEST mode
(i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
Thehost-andPCI-clockoutputsprovidelow-skew/low-jitterclocksignalsforreliableclockoperation. Alloutputs
are 3 state and are enabled via OE.
BecausetheCDC9842isbasedonPLLcircuitry, itrequiresastabilizationtimetoachievephase-lockofthePLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the OE or SELn inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pentium is a trademark of Intel Corporation.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
FUNCTION TABLE
OE
L
SEL0
SEL1
X1
HCLKn
Hi-Z
PCLKn
Hi-Z
REFn
Hi-Z
SBCLK
Hi-Z
X
L
X
L
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
H
50 MHz
60 MHz
66 MHz
TCLK/2
25 MHz
30 MHz
33 MHz
TCLK/4
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
48 MHz
48 MHz
48 MHz
TCLK/4
H
L
H
L
H
H
H
†
TCLK
H
H
†
TCLK is a test-clock input at the X1 input during test mode.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
functional block diagram
5
OE
3
28
X2
REF0
OSC
2
X1
27
REF1
25
REF2
÷2
÷2
24
SBCLK
6
HCLK0
48-MHz
PLL
7
HCLK1
9
HCLK2
CPU CLK
PLL
10
HCLK3
15
÷2
PCLK5
PCLK4
16
13
12
SEL0
SEL1
Select
Logic
18
19
PCLK3
PCLK2
21
22
PCLK1
PCLK0
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
O
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mA
O
IK
OK
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
3.135
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
0
V
CC
–8
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
8
OL
T
A
70
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
‡
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 3.135 V,
= 3.135 V,
= 3.135 V,
= 3.6 V,
–1.2
V
V
IK
CC
CC
CC
CC
CC
I
I
= –8 mA
= 8 mA
2.5
OH
OL
OH
OL
I
0.4
V
I
I
V = V
or GND
±1
µA
µA
mA
mA
pF
pF
I
I
CC
= V or GND
CC
= 3.6 V,
V
O
OZ
CC
§
Outputs enabled
50
1
V
= 3.6 V,
I
O
= 0,
CC
I
V = V
I
or GND
Outputs disabled
CC
C
C
V = V
I
or GND
6
6
i
CC
V
O
= V
or GND
o
CC
‡
§
All typical values are at V
Device in normal operating mode with no load on outputs
= 3.3 V.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
After SEL1, SEL0
After OE↑
5
5
5
†
ms
Stabilization time
After power up
†
TimerequiredfortheintegratedPLLcircuittoobtainphaselockofitsfeedbacksignaltoitsreferencesignal. Inorderforphaselocktobeobtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
switching characteristics (see Figures 1 and 2)
V
= 3.135 V
to 3.6 V,
CC
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
T
A
= 0°C to 70°C
MIN
MAX
200
ps
ps
ns
HCLKn
PCLKn
‡
t
skew
400
4
‡
Offset
1
HCLKn
PCLKn
HCKLn
±250
±350
55%
ps
ps
‡
Jitter
PCLKn
Duty cycle
Any output
45%
SEL0 = L, SEL1 = L
SEL0 = L, SEL1 = H
SEL0 = H, SEL1 = L
SEL0 = L, SEL1 = L
SEL0 = L, SEL1 = H
SEL0 = H, SEL1 = L
HCLKn
20
16.7
15
ns
ns
ns
ns
ns
ns
HCKLn
PCLKn
‡
t
c
40
33.3
30
‡§
2
2
ns
ns
t
t
r
PCKLn
HCKLn
‡§
f
PCLKn
‡
§
Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the load circuits shown in Figure 1.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
t
From Output
Under Test
c
Duty Cycle
C
= 20 pF
L
500 Ω
(see Note A)
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
t
t
f
r
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t ≤ 2.5 ns,t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
V
OH
1.5 V
CPU Clock
GND
(HCLK)
V
OH
1.5 V
CPU Clock
(HCLK)
GND
skew
skew
Offset
HCLK-to-HCLK Skew
V
OH
1.5 V
PCI Clock
(PCLK)
GND
V
OH
1.5 V
PCI Clock
(PCLK)
GND
PCLK-to-PCLK Skew
V
OH
1.5 V
CPU Clock
(HCLK)
GND
V
OH
1.5 V
PCI Clock
(PCLK)
GND
Offset
HCLK-to-PCLK Offset
Figure 2. Waveforms for Calculation of t
and Offset
skew
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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