CDCDLP223PW [TI]
用于 DLP 系统的 3.3V 时钟合成器 | PW | 20 | -40 to 85;
| 型号： | CDCDLP223PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于 DLP 系统的 3.3V 时钟合成器 | PW | 20 | -40 to 85 时钟 控制器 微控制器 微控制器和处理器 时钟发生器 |
| 文件： | 总7页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCDLP223
www.ti.com
SCAS836–DECEMBER 2006
3.3 V Clock Synthesizer for DLP™ Systems
FEATURES
CDCDLP223 PIN ASSIGNMENTS
•
High-Performance Clock Synthesizer
•
Uses a 20 MHz Crystal Input to Generate
Multiple Output Frequencies
TSSOP 20
XIN
XOUT
VSS
20
19
18
17
16
15
14
13
12
11
IREF
1
2
VDD
•
•
•
Integrated Load Capacitance for 20 MHz
Oscillator Reducing System Cost
100MHZ
100MHZ
VSS
3
All PLL Loop Filter Components are
Integrated
VDD
4
20MHZ
VSS
5
Generates the Following Clocks:
VSS
6
–
–
–
REF CLK 20 MHz (Buffered)
XCG CLK 100 MHz With SSC
EN
300MHZ
300MHZ
VSS
7
IDO
8
DMD CLK 200-400 MHz With Selectable
SSC
SDATA
SCLK
9
•
Very Low Period Jitter Characteristic:
VDD
10
–
–
±100 ps at 20 MHz Output
±75 ps at 100 MHz and 200–400 MHz
Outputs
The 100 MHz HCLK output provides the reference
clock for the XDR Clock Generator (CDCD5704).
Spread-spectrum clocking with 0.5% down spread,
which reduces Electro Magnetic Interference (EMI),
is applied in the default configuration. The
spread-spectrum clocking (SSC) is turned on and off
via the serial control interface.
•
•
Includes Spread-Spectrum Clocking (SSC),
With Down Spread for 100 MHz and Center
Spread for 200–400 MHz
HCLK Differential Outputs for the 100 MHz
and the 200–400 MHz Clock
•
•
•
Operates From Single 3.3-V Supply
Packaged in TSSOP20
The 300 MHz HCLK output provides a 200-400 MHz
clock signal for the DMD Control Logic of the DLP™
Control ASIC. Frequency selection in 20 MHz steps
is possible via the serial control interface.
Spread-spectrum clocking with ±1.0% or ±1.5%
center spread is applied, which can be disabled via
the serial control interface
Characterized for the Industrial Temperature
Range -40°C to 85°C
•
•
ESD Protection Exceeds JESD22
2000-V Human-Body Model (A114-C) –
MIL-STD-883, Method 3015
The CDCDLP223 features a fail safe start-up circuit,
which enables the PLLs only if a sufficient supply
voltage is applied and a stable oscillation is delivered
from the crystal oscillator. After the crystal start-up
time and the PLL stabilization time, all outputs are
ready for use.
TYPICAL APPLICATIONS
•
Central Clock Generator for DLP™ Systems
DESCRIPTION
The CDCDLP223 is a PLL-based high performance
clock synthesizer that is optimized for use in DLP™
systems. It uses a 20 MHz crystal to generate the
fundamental frequency and derives the frequencies
for the 100 MHz HCLK and the 300 MHz HCLK
The CDCDLP223 works from a single 3.3-V supply
and is characterized for operation from –40°C to
85°C.
output. Further, the CDCDLP223 generates
a
buffered copy of the 20 MHz Crystal Oscillator
Frequency at the 20 MHz output terminal.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCDLP223
www.ti.com
SCAS836–DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
XOUT
20 Mhz
Crystal
Oscillator
20 Mhz
LVTTL
HCLK out
HCLK out
XIN
100 Mhz
SSC PLL 1
OUT = 100 Mhz
–0.5% SSC
VDD
300 Mhz
SSC PLL 2
OUT = 200-400 Mhz
1.0% anꢀ
150 KW
EN
1.5% SSC
2-Wire Serial
SCLK
Interface
Control
Logic
IREF
VDD
SDATA
150 KW
IDO
VDD
VSS
TERMINAL FUNCTIONS
TERMINAL
PIN
1
TYPE
DESCRIPTION
XIN
I
Crystal oscillator input for 20-MHz crystal in parallel resonance
Crystal oscillator output for 20-MHz crystal in parallel resonance
XOUT
2
O
SDATA
SCLK
9
I/O Open drain Data I/O, 2-wire serial interface controller, internal 1-MΩ pullup
I Interface Clock Clock input, 2-wire serial interface controller, internal 1-MΩ pullup
10
5
20 MHz
100 MHz
100 MHz
300 MHz
300 MHz
VDD
O LVTTL
O HCLK
O HCLK
O HCLK
O HCLK
Power
Clock output, 20 MHz (buffered output from crystal oscillator)
Clock output for XDR clock generator
Clock output for XDR clock generator
Clock output for DMD system
Clock output for DMD system
3.3 V Power supply
18
17
14
13
4,11,19
VSS
3,6,12,15,16
20
Ground
Ground
IREF
O RREF to GND IREF pin for HCLK output drive-current biasing
Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 kΩ pullup, default =
logic high
EN
7
8
I LVTTL
I LVTTL
Sets 2-wire serial interface ID address bit A0, 150 kΩ pull-up resistor, default = logic
high
IDO
Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks)
EN PIN
DESCRIPTION
1
All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface
settings.
0
All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides
2-wire serial interface settings.
2
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CDCDLP223
www.ti.com
SCAS836–DECEMBER 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
VDD
VI
Supply voltage range
Input voltage range(2)
–0.5 to 4.6
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
±20
V
VO
Output voltage range(2)
Input current (VI < 0, VI > VDD
Continuous output current
Storage temperature range
V
)
mA
mA
°C
IO
±17.5
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
PACKAGE THERMAL IMPEDANCE FOR TSSOP20 PACKAGE(1)
Airflow (lfm)
θJA (°C/W)
83.0
θJC (°C/W)
θJB (°C/W)
ΨJT (°C/W)
0
32
–
54
–
0.25
150
250
500
77.9
75.4
–
–
71.4
–
–
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k
board).
RECOMMENDED OPERATING CONDITIONS
MIN
-40
NOM
MAX UNIT
TA
Operating free-air temperature
85
3.6
°C
V
VDD Supply voltage
3.0
3.3
VIH
VIL
High level input voltage SDATA and SCLK
0.7 × VDD
–0.15
VDD
V
0.3 ×
VDD
Low level input voltage SDATA and SCLK
V
VIL
VI
Low level input voltage LVTTL
0.8
V
thresh Input Voltage threshold LVTTL
High level input voltage LVTTL
1.40
V
VIH
IOH
IOL
IOH
IOL
tPU
2.0
V
High-level output current LVTTL
Low-level output current LVTTL
High-level output current HCLK/HCLK
Low-level output current HCLK/HCLK
–8
8
mA
mA
mA
mA
ms
–20
0
Power-up time for all VDDs to reach minimum specified voltage (power ramps must be
monotonic)
0.05
500
RECOMMENDED CRYSTAL SPECIFICATION(1)
MIN
NOM
MAX
UNIT
MHz
Ω
fxtal
Crystal input frequency (fundamental)
Effective series resistance
20
ESR
Pdrive
CL
100
Maximum power handling (drive level)
Load capacitance
100
µW
pF
20
(1) See DLP™ Control ASIC DDP2230 datasheet for additional requirements.
3
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CDCDLP223
www.ti.com
SCAS836–DECEMBER 2006
TIMING REQUIREMENTS(1)
over recommended ranges of supply voltage, load and operating free air temperature
PARAMETER
MIN
TYP MAX UNIT
XIN, XOUT REQUIREMENTS
fXIN
Frequency of crystal attached to XIN, XOUT, with CL = 20 pF (2 × 40 pF) on-die
20
MHz
capacitance
2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE
fSCLK
SCLK frequency
0
4.0
4.7
4.0
4.7
0
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
th(START)
tw(SCLL)
tw(SCLH)
tsu(START)
th(SDATA)
tsu(SDATA)
tr(SDATA)
tf(SDATA)
tsu(STOP)
tBUS
START hold time (see Figure 1)
SCLK low-pulse duration (see Figure 1)
SCLK high-pulse duration (see Figure 1)
START setup time (see Figure 1)
SDATA hold time (see Figure 1)
SDATA setup time (see Figure 1)
SCLK / SDATA input rise time (see Figure 1)
SCLK / SDATA input fall time (see Figure 1)
STOP setup time (see Figure 1)
Bus free time
3.45
250
1000
300
4.0
4.7
2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE
fSCLK
SCLK frequency
0
0.6
1.3
0.6
0.6
0
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
th(START)
tw(SCLL)
tw(SCLH)
tsu(START)
th(SDATA)
tsu(DATA)
tr(SDATA)
tf(SDATA)
tsu(STOP)
tBUS
START hold time (see Figure 1)
SCLK low-pulse duration (see Figure 1)
SCLK high-pulse duration (see Figure 1)
START setup time (see Figure 1)
SDATA hold time (see Figure 1)
SDATA setup time (see Figure 1)
SCLK / SDATA input rise time (see Figure 1)
SCLK / SDATA input fall time (see Figure 1)
STOP setup time (see Figure 1)
Bus free time
0.9
100
20
300
300
20
0.6
1.3
(1) The CDCDLP223 2-wire serial interface in Send-Mode meets both I2C and SMBus set up time tsu and hold time th requirements.
4
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CDCDLP223
www.ti.com
SCAS836–DECEMBER 2006
APPLICATION INFORMATION
Figure 1. Timing Diagram, Serial Control Interface
3.3V
20MHz
SCLK
IREF
SDATA
CDCDLP223
ID0
EN
100MHz
3.3V
320MHz
2
20MHz
2
Spread
ISET
CDCD5704
ID1 ID0
400MHz
2
Spread
Spread
No Spread
ClockA
ClockB
ClockC
Div by A
XDR
DRAM
Clock
Div by B
Div by C
PLL
xN
DMD
Control
Logic
Distribution
.
.
.
DLPTM Processor Chip
Figure 2. Typical CDCDLP223 Application
5
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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