CDCE813QPWRQ1 [TI]

具有 2.5V 和 3.3V 输出的可编程 1-PLL 时钟合成器和抖动消除器 | PW | 14 | -40 to 105;


型号：	CDCE813QPWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 2.5V 和 3.3V 输出的可编程 1-PLL 时钟合成器和抖动消除器 \| PW \| 14 \| -40 to 105 时钟
文件：	总34页 (文件大小：1614K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

具有 2.5V 和 3.3V 输出的 CDCE813-Q1 可编程 1-PLL 时钟合成器

和抖动消除器

1 特性

2 应用

•

符合汽车应用要求

•

仪表组

•

具有符合 AEC-Q100 标准的下列特性：

音响主机

导航系统

–

器件温度等级 2：–40°C 至 105°C 的环境工作

温度范围

高级驾驶辅助系统 (ADAS)

–

器件 HBM ESD 分类等级 H2

器件 CDM ESD 分类等级 C6

3 说明

CDCE813-Q1 器件是一款基于模块化锁相环 (PLL) 的

低成本、高性能、可编程时钟合成器。它们最多可从单

个输入频率中生成 3 个输出时钟。借助集成的可配置

PLL，可在系统内针对任何时钟频率（高达 230MHz）

对每个输出进行编程。

•

系统内可编程和 EEPROM

–

串行可编程易失性寄存器

用于存储客户设置的非易失性 EEPROM

灵活的输入计时理念

–

外部晶体：8MHz 至 32MHz

高达 160MHz 的单端 LVCMOS

CDCE813-Q1 具有独立的输出电源引脚 V_DDOUT，可提

供 2.5V 至 3.3V 电压。

•

高达 230MHz 的自由可选输出频率

低噪声 PLL 内核

此输入接受外部晶振或 LVCMOS 时钟信号。凭借可选

片载 VCXO，可将输出频率与外部控制信号同步。

–

已集成的 PLL 环路滤波器组件

低电平周期抖动（典型值 50ps）

PLL 支持 SSC（扩频时钟），从而改善抗电磁干扰

(EMI) 性能。

•

1.8V 器件电源（内核电压）

独立的输出电源引脚：3.3V 和 2.5V

灵活的时钟驱动器

器件信息⁽¹⁾

–

三个用户可定义的控制输入 [S0、S1、S2]，例

如 SSC 选择、频率切换、输出使能或断电

器件型号

封装

封装尺寸（标称值）

CDCE813-Q1

TSSOP (14)

5.00mm × 4.40mm

–

生成适用于视频、音频、USB、IEEE1394 和

RFID、 Bluetooth^®、WLAN、以太网和 GPS 的

高精度时钟

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

生成可与 TI-DaVinci™、 OMAP™和 DSP 配合

使用的共同时钟频率

器件比较

可订购产品

CDCE813R02-Q1

CDCE813-Q1

S0 控制引脚默认功能

Y1 输出使能（高电平有效）

未使用⁽¹⁾

–

可编程 SSC 调制

启用 0-PPM 时钟生成功能

•

采用 TSSOP 封装

典型应用原理图

适用于简易 PLL 设计和编程的开发和编程套件（TI

ClockPro™编程软件）

PCLK

CDCE813-Q1

I2C

SoC

To Display

Image Data

Serializer

(1) 必须由 I2C 控制启用输出。

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS705

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

www.ti.com.cn

9.3 Feature Description................................................. 12

9.4 Device Functional Modes........................................ 15

9.5 Programming........................................................... 15

9.6 Register Maps......................................................... 17

10 Application and Implementation........................ 21

10.1 Application Information.......................................... 21

10.2 Typical Application ................................................ 21

11 Power Supply Recommendations ..................... 25

12 Layout................................................................... 26

12.1 Layout Guidelines ................................................. 26

12.2 Layout Example .................................................... 26

13 器件和文档支持 ..................................................... 27

13.1 文档支持................................................................ 27

13.2 接收文档更新通知 ................................................. 27

13.3 社区资源................................................................ 27

13.4 商标....................................................................... 27

13.5 静电放电警告......................................................... 27

13.6 Glossary................................................................ 27

14 机械、封装和可订购信息....................................... 27

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics .......................................... 6

7.6 Timing Requirements................................................ 8

7.7 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 10

Detailed Description ............................................ 11

9.1 Overview ................................................................. 11

9.2 Functional Block Diagram ....................................... 11

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (May 2018) to Revision C

Page

•

向数据表中添加了 CDCE813R02-Q1 可订购信息 .................................................................................................................. 1

添加了器件对比表.................................................................................................................................................................. 1

Added default configuration information to the S0 pin description......................................................................................... 4

Removed 'CDCE813-Q1' text from the V_DDOUTpin description. The information applies to both CDCE813-Q1 and

CDCE813R02-Q1 orderables................................................................................................................................................. 4

•

Added S0 pin information in the Overview section............................................................................................................... 11

Added S0 pin information to the Default Device Configuration section................................................................................ 13

Added CDCE813R02-Q1 Default Configuration graphic...................................................................................................... 14

Changed S0 pin information in the Factory Default Setting for Control Terminal Register tablenote.................................. 14

Added Y1_ST1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderables .................................................. 18

Added Y1_1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderables....................................................... 18

Changes from Revision A (May 2018) to Revision B

Page

•

Changed the text in the Default Device Configuration section from: However the outputs are disabled by default and

need to be turned on through I2C or with the S0 pin to: However the outputs are disabled by default and need to be

turned on through I2C........................................................................................................................................................... 13

•

Changed the Factory Default Setting table and Default Configuration graphic text to show that the Y1 outputs as 3-

state when S0 = 1 or S0 = 0................................................................................................................................................. 14

•

Changed the default value of the SLAVE_ADR 1:0 bits from: 00b to: 01b in the Generic Configuration Register table .... 18

Changed the default value of the Y1_ST0 3:2 bits from: 11b to: 01b in the Generic Configuration Register table............. 18

Changed the default value of the BCOUNT 7:1 bits from: 20h to: 00h in the Generic Configuration Register table .......... 18

Changed the default value of the Y2Y3_1 bit from: 1b to: 0b in the PLL1 Configuration Register table............................. 19

CDCE813-Q1

www.ti.com.cn

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

Changes from Original (January 2017) to Revision A

Page

•

Changed the Factory Default Setting table and Default Configuration graphic text to show that S0 = 1 means Y1

outputs 3-state and S0 = 0 means Y1 is enabled ................................................................................................................ 14

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

www.ti.com.cn

5 说明（续）

为了轻松实现器件自定义来满足应用需要，该器件支持使用非易失性 EEPROM 进行编程。所有器件设置均可通过

I2C 总线（一种两线制串行接口）进行编程。

CDCE813-Q1 在 1.8V 内核环境下运行，无需额外使用独立的 XTAL 振荡器，可减少组件数量并缩减电路板尺寸。

它的运行温度范围为 –40°C 至 105°C。

6 Pin Configuration and Functions

PW Package

14-Pin TSSOP

Top View

Xin/CLK

Xout

SDA/S1

SCL/S2

VDD

Vctr

GND

VDDOUT

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

GND

5, 10

Ground

SCL: serial clock input LVCMOS (default configuration), 500-kΩ internal pullup; or

S2: user-programmable control input, LVCMOS input, 500-kΩ internal pullup

SCL/S2

SDA/S1

SDA: bidirectional serial data input or output (default configuration), LVCMOS internal pullup; or

S1: user-programmable control input, LVCMOS input, 500-kΩ internal pullup

I/O or I

User-programmable control input S0, LVCMOS input, 500-kΩ internal pullup

CDCE813-Q1 default:

S0 = 1: Y1 is 3-state,

S0 = 0: Y1 is 3-state

CDCE813R02-Q1 default:

S0 = 1: Y1 is enabled,

S0 = 0: Y1 is 3-state

V_ctr

VCXO control voltage (leave open or pull up when not used)

1.8-V power supply for the device

V_DD

V_DDOUT

Xin/CLK

Xout

6, 7

3.3-V or 2.5-V supply for all outputs

Crystal oscillator input or LVCMOS clock input (selectable through the I2C bus)

Crystal oscillator output (leave open or pull up when not used)

LVCMOS output

(1) G = Ground, I = Input, O = Output, P = Power

CDCE813-Q1

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

2.5

UNIT

V_DD

V_DDOUT

V_I

Supply voltage

Output clocks supply voltage

Input voltage⁽²⁾⁽³⁾

Output voltage⁽²⁾

CDCE813-Q1

3.6 + 0.5

V_DD+ 0.5

V_DDOUT+ 0.5

V_O

I_I

Input current (V_I< 0, V_I> V_DD

)

I_O

Continuous output current

T_J

Maximum junction temperature

Storage temperature

125

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.

7.2 ESD Ratings

VALUE

±2000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN

1.7

NOM

MAX

1.9

UNIT

V_DD

V_O

Device supply voltage

1.8

Output Yx supply voltage, V_DDOUT

Low-level input voltage, LVCMOS

High-level input voltage, LVCMOS

Input voltage threshold, LVCMOS

Input voltage range, S0

CDCE813-Q1

2.3

3.6

V_IL

0.3 × V_DD

V_IH

0.7 × V_DD

V_I(thresh)

0.5 × V_DD

1.9

3.6

1.9

±12

±10

V_I(S)

Input voltage range S1, S2, SDA, SCL (V_I(thresh)= 0.5 V_DD

)

V_I(CLK)

I_OH, I_OL

Input voltage range CLK

V_DDOUT= 3.3 V

V_DDOUT= 2.5 V

Output current

C_L

T_A

Output load, LVCMOS

°C

Operating ambient temperature

–40

105

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

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Recommended Operating Conditions (continued)

MIN

NOM

MAX

UNIT

CRYSTAL AND VCXO SPECIFICATIONS⁽¹⁾

f_Xtal

Crystal input frequency range (fundamental mode)

Effective series resistance

Pulling range (0 V ≤ V_ctr≤ 1.8 V)⁽²⁾

MHz

Ω

ESR

f_PR

100

±120

±150

ppm

V_ctr

Frequency control voltage

V_DD

220

C₀/ C₁

C_L

Pullability ratio

On-chip load capacitance at Xin and Xout

(1) For more information about VCXO configuration, and crystal recommendation, see application report VCXO Application Guideline for

CDCE(L)9xx Family (SCAA085).

(2) Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120

ppm applies for crystal listed in the application report VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

7.4 Thermal Information

CDCE813-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

PW (TSSOP)

14 PINS

110.6

35.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

53.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.1

ψ_JB

52.8

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

OVERALL PARAMETER

All outputs off,

All PLLS on

Per PLL

f_CLK= 27 MHz,

f_VCO= 135 MHz,

f_OUT= 27 MHz

I_DD

Supply current (see Figure 1)

No load, all outputs on,

f_OUT= 27 MHz

I_DD(OUT)

I_DD(PD)

V_(PUC)

Supply current (see Figure 2)

V_DDOUT= 3.3 V

1.3

Power-down current. Every circuit

powered down except I2C

f_IN= 0 MHz, V_DD= 1.9 V

μA

Supply voltage V_DDthreshold for

power-up control circuit

0.85

1.45

f_VCO

f_OUT

VCO frequency range of PLL

LVCMOS output frequency

230 MHz

V_DDOUT= 3.3 V

(1) All typical values are at respective nominal V_DD

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

LVCMOS PARAMETER

V_IK

I_I

LVCMOS input voltage

LVCMOS input current

V_DD= 1.7 V, I_I= –18 mA

–1.2

±5

V_I= 0 V or V_DD, V_DD= 1.9 V

μA

LVCMOS input current for S0, S1,

and S2

I_IH

I_IL

V_I= V_DD, V_DD= 1.9 V

V_I= 0 V, V_DD= 1.9 V

μA

LVCMOS input current for S0, S1,

and S2

–4

Input capacitance at Xin/CLK

Input capacitance at Xout

V_IClk= 0 V or V_DD

V_IXout= 0 V or V_DD

V_IS= 0 V or V_DD

C_I

Input capacitance at S0, S1, and S2

CDCE813-Q1, LVCMOS PARAMETER FOR V_DDOUT= 3.3-V MODE

V_DDOUT= 3 V, I_OH= –0.1 mA

2.9

2.4

2.2

V_OH

LVCMOS high-level output voltage

V_DDOUT= 3 V, I_OH= –8 mA

V_DDOUT= 3 V, I_OH= –12 mA

V_DDOUT= 3 V, I_OL= 0.1 mA

V_DDOUT= 3 V, I_OL= 8 mA

V_DDOUT= 3 V, I_OL= 12 mA

PLL bypass

0.1

0.5

0.8

V_OL

LVCMOS low-level output voltage

Propagation delay

3.2

t_PLH, t_PHL

PLL enabled (f_CLK= f_VCO), 70 MHz ≤ f_VCO

85 MHz

≤

1.6

4.3

t_r, t_f

Rise and fall time

Cycle-to-cycle jitter⁽²⁾

Peak-to-peak period jitter⁽²⁾

Output skew (see Table 2)⁽³⁾

V_DDOUT= 3.3 V (20%–80%)

1 PLL switching, Y2-to-Y3, 10,000 cycles

1 PLL switching, Y2-to-Y3

0.6

t_jit(cc)

t_jit(per)

t_sk(o)

odc

200

440

55%

f_OUT= 50 MHz, Y1-to-Y3

(4)

Output duty cycle

f_VCO= 100 MHz, Pdiv = 1

45%

CDCE813-Q1, LVCMOS PARAMETER FOR V_DDOUT= 2.5-V MODE

V_DDOUT= 2.3 V, I_OH= –0.1 mA

2.2

1.7

1.6

V_OH

LVCMOS high-level output voltage

V_DDOUT= 2.3 V, I_OH= –6 mA

V_DDOUT= 2.3 V, I_OH= –10 mA

V_DDOUT= 2.3 V, I_OL= 0.1 mA

V_DDOUT= 2.3 V, I_OL= 6 mA

V_DDOUT= 2.3 V, I_OL= 10 mA

PLL bypass

0.1

0.5

0.7

V_OL

LVCMOS low-level output voltage

t_PLH, t_PHL

t_r, t_f

Propagation delay

3.6

0.8

Rise and fall time

V_DDOUT= 2.5 V (20%–80%)

1 PLL switching, Y2-to-Y3, 10,000 cycles

1 PLL switching, Y2-to-Y3

f_OUT= 50 MHz, Y1-to-Y3

t_jit(cc)

t_jit(per)

t_sk(o)

Cycle-to-cycle jitter⁽²⁾

Peak-to-peak period jitter⁽²⁾

Output skew (see Table 2)⁽³⁾

Output duty cycle⁽⁴⁾

200

440

55%

odc

f_VCO= 100 MHz, Pdiv = 1

45%

(2) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f_VCO= 108 MHz, f_OUT= 27 MHz (measured at Y2).

(3) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.

(4) odc depends on the output rise and fall time (t_rand t_f); data sampled on the rising edge (t_r)

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

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MAX UNIT

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN TYP⁽¹⁾

I2C PARAMETER

V_IK

I_IH

SCL and SDA input clamp voltage

SCL and SDA input current

I2C input high voltage⁽⁵⁾

V_DD= 1.7 V, I_I= –18 mA

V_I= V_DD, V_DD= 1.9 V

–1.2

±10

μA

V_IH

0.7 × V_DD

0.3 ×

V_DD

V_IL

I2C input low voltage⁽⁵⁾

0.2 ×

V_DD

V_OL

C_I

SDA low-level output voltage

SCL-SDA input capacitance

I_OL= 3 mA, V_DD= 1.7 V

V_I= 0 V or V_DD

EEPROM SPECIFICATION

EEcyc

EEret

Programming cycles of EEPROM

Data retention

100

1000

cycles

years

(5) SDA and SCL pins are 3.3-V tolerant.

7.6 Timing Requirements

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

UNIT

CLK_IN

PLL bypass mode

160

f_CLK

LVCMOS clock input frequency

MHz

PLL mode

t_rand t_f

Rise and fall time, CLK signal (20% to 80%)

Duty cycle of CLK at V_DD/ 2

40%

60%

I2C (SEE Figure 13)

Standard mode

Fast mode

100

400

f_SCL

SCL clock frequency

kHz

μs

Standard mode

Fast mode

4.7

0.6

t_su(START)START setup time (SCL high before SDA low)

t_h(START)START hold time (SCL low after SDA low)

Standard mode

Fast mode

μs

0.6

4.7

1.3

Standard mode

Fast mode

t_w(SCLL)

t_w(SCLH)

t_h(SDA)

SCL low-pulse duration

μs

Standard mode

Fast mode

SCL high-pulse duration

SDA hold time (SDA valid after SCL low)

SDA setup time

μs

0.6

Standard mode

Fast mode

3.45

0.9

μs

Standard mode

Fast mode

250

100

t_su(SDA)

Standard mode

Fast mode

1000

300

t_r

SCL-SDA input rise time

SCL-SDA input fall time

STOP setup time

μs

t_f

300

Standard mode

Fast mode

0.6

4.7

1.3

t_su(STOP)

Standard mode

Fast mode

t_BUS

Bus free time between a STOP and START condition

μs

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

7.7 Typical Characteristics

= 1.8 V

= 1.8 V,

= 3.3 V,

DDOUT

no load

3 Outputs on

1 PLL on

1 Output on

all PLL off

all Outputs off

10 30 50 70 90 110 130 150 170 190 210 230

- Output Frequency - MHz

110

160

210

- Frequency - MHz

OUT

VCO

Figure 2. CDCE813-Q1 Output Current

vs Output Frequency

Figure 1. CDCE813-Q1 Supply Current

vs PLL Frequency

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

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8 Parameter Measurement Information

CDCE813-Q1

1 kW

LVCMOS

10 pF

Figure 3. Test Load

CDCE813-Q1

LVCMOS

series

driver

impedance

~ 50 W

line impedance

termination

Zo = 50 W

(optional)

Figure 4. Test Load for 50-Ω Board Environment

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

9 Detailed Description

9.1 Overview

The CDCExxx-Q1 devices are modular PLL-based, low-cost, high-performance, programmable clock

synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency.

Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated

configurable PLL.

The CDCExxx-Q1 devices have separate output supply pins, V_DDOUT, with output of 2.5 V to 3.3 V.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load

capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.

Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control

signal, that is, the PWM signal.

The deep M / N divider ratio allows the generation of zero-ppm audio-video, networking (WLAN, Bluetooth,

Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input

frequency.

The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which

is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve high stability and optimized jitter transfer characteristics.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It

is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a

different application configuration before PCB assembly, or reprogrammed by in-system programming. All device

settings are programmable through the SDA-SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC

setting for lowering EMI, or control other features like outputs disable to low, outputs in Hi-Z state, power down,

PLL bypass, and so forth). For CDCE813-Q1, the S0 pin is unused by default. For the CDCE813R02-Q1, the S0

control input pin provides output enable (OE) control for output Y1 only.

The CDCE813-Q1 core operates in a 1.8-V environment. It operates in a temperature range of –40°C to 105°C.

9.2 Functional Block Diagram

GND

DDOUT

Input Clock

ctr

Pdiv1

10-Bit

CMOS

Xin/CLK

VCXO

CMOS

Pdiv2

PLL 1

LVCMOS

7-Bit

with SSC

Xout

Pdiv3

7-Bit

CMOS

PLL Bypass

EEPROM

Programming

and I2C

S1/SDA

S2/SCL

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9.3 Feature Description

9.3.1 Control Terminal Configuration

The CDCE813-Q1 device has three user-definable control terminals (S0, S1, and S2), which allow external

control of device settings. They can be programmed to any of the following functions:

•

Spread-spectrum clocking selection → spread type and spread amount selection

Frequency selection → switching between any of two user-defined frequencies

Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition

EXTERNAL CONTROL

PLL1 SETTING

Y1 SETTING

BITS

PLL frequency

selection

Output Y2 and Y3

selection

Control function

SSC selection

Output Y1 and power-down selection

(1)

Table 2. PLL1 Setting

SSCx [3 BITS]

SSC SELECTION (CENTER AND DOWN)

CENTER

DOWN

0% (off)

±0.25%

±0.5%

0% (off)

–0.25%

–0.5%

±0.75%

±1.0%

–0.75%

–1.0%

±1.25%

±1.5%

–1.25%

–1.5%

±2.0%

–2.0%

(1) Center and down-spread, Frequency0, Frequency1, State0, and State1 are user-definable in PLL1

configuration register.

(1)

Table 3. PLL1 Setting, Frequency Selection

FSx

FUNCTION

Frequency 0

Frequency 1

(1) Frequency0 and Frequency1 can be any frequency within the

specified f_VCOrange.

(1)

Table 4. PLL1 Setting, Output Selection (Y2, Y3)

Y2, Y3

FUNCTION

State 0

State 1

(1) State0 or State1 selection is valid for both outputs of the

corresponding PLL module and can be power down, Hi-Z state, low,

or active.

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(1)

Table 5. Y1 Setting

FUNCTION

State 0

State 1

(1) State0 and State1 are user definable in the generic configuration

The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration,

they are defined as SDA and SCL for the serial programming interface. They can be programmed as control pins

(S1 and S2) by setting the appropriate bits in the EEPROM.

NOTE

Changes to the control register (Bit [6] of byte 02h) have no effect until they are written

into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUTis

forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin; it is a control pin only.

9.3.2 Default Device Configuration

The internal EEPROM of the CDCE813-Q1 device is pre-configured with a factory default configuration as shown

in Figure 5 (the input frequency is routed through PLL1 to the outputs as a default). This mode can be used to

clean the jitter of an incoming clock signal. For the CDCE813-Q1, the outputs are disabled by default and must

be turned on through I2C. For the CDCE813R02-Q1, output Y1 is enabled through the S0 control pin (active

high), while outputs Y2 and Y3 are either in a tri-state condition or disabled by the register default. Y1 is enabled

when S0 is floating because S0 has an internal pullup.

The default setting appears either after power is supplied or after a power-down – power-up sequence until it is

reprogrammed by the user to a different application configuration. A new register setting is programmed through

the serial I2C interface.

V_DDOUT

V_DD

GND

Input Clock

Vctr

CMOS

Pdiv1 = 1

Y1 = 3-state

1.8V LVCMOS

CLK input

LVCMOS

CMOS

Pdiv2 = 0

PLL 1 enabled

F_IN= F_VCO

Y2 = 3-state

Y3 = 3-state

(disabled)

CMOS

Pdiv3 = 0

(disabled)

PLL Bypass

EEPROM

^1_ = outputs 3-State

^0_ = outputs 3-State

Programming

and

SDA/SCL Register

SDA

Programming Bus

SCL

Figure 5. CDCE813-Q1 Default Configuration

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V_DDOUT

V_DD

GND

Input Clock

Vctr

CMOS

Pdiv1 = 1

Y1 = enable

through S0 pin

1.8V LVCMOS

CLK input

LVCMOS

CMOS

Pdiv2 = 0

PLL 1 enabled

F_IN= F_VCO

Y2 = 3-state

Y3 = 3-state

(disabled)

CMOS

Pdiv3 = 0

(disabled)

PLL Bypass

EEPROM

Programming

^1_ = Y1 output enable

^0_ = Y1 output 3-state

and

SDA

SCL

Programming Bus

SDA/SCL Register

Figure 6. CDCE813R02-Q1 Default Configuration

Table 6 shows the factory default setting for the Control Terminal Register.

NOTE

Even though eight different register settings are possible, in the default configuration, only

the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as

programming pins in default mode.

(1)

Table 6. Factory Default Setting for Control Terminal Register

PLL1 SETTINGS

GPN

EXTERNAL CONTROL PINS

OUTPUT

SELECTION

FREQUENCY

SELECTION

SSC

SELECTION

OUTPUT

SELECTION

FS1

SSC1

Off

Y2Y3

3-state

SCL (I²C)

SDA (I²C)

3-state

Enabled

f_{VCO1_0}

CDCE813-Q1

Off

CDCE813R02-

Off

(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, I2C. They do not have any control-

pin function but they are internally interpreted as if S1 = 0 and S2 = 0. For the CDCE813-Q1, S0 is an unused control pin by default. For

the CDCE813R02-Q1, S0 provides output enable (OE) control output Y1 only.

9.3.3 I2C Serial Interface

The CDCE813-Q1 device operates as a slave device on the 2-wire serial I2C bus compatible with the popular

SMBus or I²C specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode transfer

(up to 400 kbps) and supports 7-bit addressing.

The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration,

they are used as the I2C serial programming interface. They can be reprogrammed as general-purpose control

pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

9.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with

most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of

bytes read out are defined by Byte Count in the generic configuration register. At the Block Read instruction, all

bytes defined in Byte Count must be read out to finish the read cycle correctly.

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Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to

each transferred byte, regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write

cycle, data is not accepted at the I2C bus until the write cycle is completed. However, data can be read out

during the programming sequence (Byte Read or Block Read). The programming status can be monitored by

EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 7.

Table 7. Slave Receiver Address (7 Bits)

DEVICE

A1⁽¹⁾

A0⁽¹⁾

R/W

1/0

CDCE813-Q1

CDCEx925

CDCEx937

CDCEx949

(1) Address bits A0 and A1 are programmable through the I2C bus (byte 01, bits [1:0]. This allows addressing up to 4 devices connected to

the same I2C bus. The least-significant bit of the address byte designates a write or read operation.

9.4 Device Functional Modes

9.4.1 SDA and SCL Hardware Interface

Figure 7 shows how the CDCE813-Q1 clock synthesizer is connected to the I2C serial interface bus. Multiple

devices can be connected to the bus, but it may be necessary to reduce the speed (400 kHz is the maximum) if

many devices are connected.

Note that the pullup resistors (R_P) depend on the supply voltage, bus capacitance, and number of connected

devices. The recommended pullup value is 4.7 kΩ. The resistor must meet the minimum sink current of 3 mA at

V_OLmax = 0.4 V for the output stages (for more details see the SMBus or I²C Bus specifications in the Timing

Requirements table).

CDCE813-Q1

R_p

Master

SDA

Slave

SCL

C_BUSC_BUS

Figure 7. I2C Hardware Interface

9.5 Programming

Table 8. Command Code Definition

BIT

DESCRIPTION

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

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Programming (continued)

Table 8. Command Code Definition (continued)

BIT

DESCRIPTION

(6:0)

Byte offset for Byte Read, Block Read, Byte Write, and Block Write operations

Slave Address

Data Byte

R/W

MSB

LSB

MSB

LSB

Start Condition

Sr Repeated Start Condition

1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx

Acknowledge (ACK = 0 and NACK =1)

Stop Condition

R/W

Master-to-Slave Transmission

Slave-to-Master Transmission

Figure 8. Generic Programming Sequence

Slave Address

CommandCode

Data Byte

Figure 9. Byte Write Protocol

Slave Address

CommandCode

Slave Address

Data Byte

Figure 10. Byte Read Protocol

Slave Address

CommandCode

Byte Count = N

Data Byte 0

Data Byte 1

…

Data Byte N-1

(1) Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and should not be overwritten.

Figure 11. Block Write Protocol

Slave Address

CommandCode

Slave Address

Byte Count N

Data Byte 0

…

Data Byte N-1

Figure 12. Block Read Protocol

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Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

w(SCLL)

w(SCLH)

SCL

su(START)

h(START)

su(SDA)

h(SDA)

su(STOP)

(BUS)

SDA

Figure 13. Timing Diagram for I2C Serial Control Interface

9.6 Register Maps

9.6.1 I2C Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCE813-Q1 device. All settings can be manually

written into the device through the I2C bus or easily programmed by using the TI ClockPro™ programming

software. The TI ClockPro™ programming software allows the user to make all settings quickly, and

automatically calculates the values for optimized performance at lowest jitter.

Table 9. I2C Registers

ADDRESS OFFSET

Generic configuration register

PLL1 configuration register

TABLE

Table 11

Table 12

00h

10h

The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the

control terminal register. The user can predefine up to eight different control settings. These settings then can be

selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.

Table 10. Configuration Register, External Control Terminals

PLL1 SETTINGS

EXTERNAL

CONTROL PINS

OUTPUT

SELECTION

OUTPUT SELECTION

FREQUENCY SELECTION

SSC SELECTION

FS1

SSC1

Y2Y3

Y1_0

Y1_1

Y1_2

Y1_3

Y1_4

Y1_5

Y1_6

Y1_7

04h

FS1_0

FS1_1

FS1_2

FS1_3

FS1_4

FS1_5

FS1_6

FS1_7

13h

SSC1_0

SSC1_1

SSC1_2

SSC1_3

SSC1_4

SSC1_5

SSC1_6

SSC1_7

10h–12h

Y2Y3_0

Y2Y3_1

Y2Y3_2

Y2Y3_3

Y2Y3_4

Y2Y3_5

Y2Y3_6

Y2Y3_7

15h

Address offset⁽¹⁾

(1) Address offset refers to the byte address in the configuration register in Table 11 and Table 12.

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Table 11. Generic Configuration Register

OFFSET⁽¹⁾BIT⁽²⁾

ACRONYM

E_EL

RID

DEFAULT⁽³⁾

DESCRIPTION

Device identification (read-only): 1 is CDCE813-Q1 (3.3 Vout)

00h

6:4

3:0

Revision identification number (read-only)

Vendor identification number (read-only)

Reserved – always write 0

VID

—

0 – EEPROM programming is completed.

1 – EEPROM is in programming mode.

EEPIP

EEPROM programming Status:⁽⁴⁾(read-only)

Permanently lock EEPROM data⁽⁵⁾

0 – EEPROM is not locked.

1 – EEPROM is permanently locked.

EELOCK

Device power down (overwrites S0, S1, and S2 settings; configuration register settings are unchanged)

Note: PWDN cannot be set to 1 in the EEPROM.

01h

PWDN

0 – Device active (PLL1 and all outputs are enabled)

1 – Device power down (PLL1 in power down and all outputs in Hi-Z state)

00 – Xtal

10 – LVCMOS

11 – Reserved

3:2

INCLK

10b

Input clock selection:

01 – VCXO

SLAVE_AD

1:0

01b

Address bits A0 and A1 of the slave receiver address

Clock source selection for output Y1:

0 – Input clock

1 – PLL1 clock

Operation mode selection for pins 12 and 13⁽⁶⁾

SPICON

0 – Serial programming interface SDA (pin 13) and SCL (pin 12)

1 – Control pins S1 (pin 13) and S2 (pin 12)

CDCE813-Q1: 01b

CDCE813R02-Q1:

11b

02h

5:4

3:2

Y1_ST1

Y1_ST0

Y1-State0/1 definition

00 – Device power down (all PLLs in power down and all

outputs in Hi-Z state)

10 – Y1 disabled to low

11 – Y1 enabled

01b

01 – Y1 disabled to Hi-Z state

1:0

7:0

Pdiv1 [9:8]

Pdiv1 [7:0]

Y1_7

0 – Divider reset and stand-by

1 to 1023 – Divider value

001h

10-bit Y1-output-divider Pdiv1:

03h

04h

Y1_6

Y1_5

Y1_4

0 – State0 (predefined by Y1_ST0)

1 – State1 (predefined by Y1_ST1)

Y1_x State selection⁽⁷⁾

Y1_3

Y1_2

CDCE813-Q1: 0b

CDCE813R02-Q1: 1b

Y1_1

Y1_0

00h

Crystal load capacitor selection⁽⁸⁾

00h – 0 pF

01h – 1 pF

02h – 2 pF

7:3

2:0

XCSEL

05h

:14h to 1Fh – 20 pF

Reserved – do not write other than 0

(1) Writing data beyond 20h may affect device function.

(2) All data transferred with the MSB first

(3) Unless customer-specific setting

(4) During EEPROM programming, no data is allowed to be sent to the device through the I2C bus until the programming sequence is

completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.

Data, however can still be written through the I2C bus to the internal register to change device function on the fly, but new data can no

longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.

(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no

longer available. However, if V_DDOUTis forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins

(SDA-SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

(7) These are the bits of the control terminal register (see Table 10 ). The user can predefine up to eight different control settings. These

settings then can be selected by the external control pins, S0, S1, and S2.

(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to

finely adjust C_Lby a few picofarads. The value of C_Lcan be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20

pF. For C_L> 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5

pF (6 pF//2 pF) to the selected C_L. For more about VCXO configuring and crystal recommendation, see application report VCXO

Application Guideline for CDCE(L)9xx Family (SCAA085).

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Table 11. Generic Configuration Register (continued)

ACRONYM

DEFAULT⁽³⁾

DESCRIPTION

7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes

must be read out to finish the read cycle correctly.

7:1

BCOUNT

00h

06h

0– No EEPROM write cycle

1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)

(4)(9)

EEWRITE

—

Initiate EEPROM write cycle

07h-0Fh

Unused address range

(9) The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The

EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out

EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

Table 12. PLL1 Configuration Register

OFFSET⁽¹⁾

BIT⁽²⁾

7:5

4:2

1:0

ACRONYM

SSC1_7 [2:0]

SSC1_6 [2:0]

SSC1_5 [2:1]

SSC1_5 [0]

SSC1_4 [2:0]

SSC1_3 [2:0]

SSC1_2 [2]

SSC1_2 [1:0]

SSC1_1 [2:0]

SSC1_0 [2:0]

FS1_7

DEFAULT⁽³⁾

DESCRIPTION

(4)

000b

SSC1: PLL1 SSC selection (modulation amount).

10h

000b

Down

000 (off)

Center

000 (off)

001 – 0.25%

010 – 0.5%

011 – 0.75%

100 – 1.0%

101 – 1.25%

110 – 1.5%

111 – 2.0%

001 ± 0.25%

010 ± 0.5%

011 ± 0.75%

100 ± 1.0%

101 ± 1.25%

110 ± 1.5%

111 ± 2.0%

000b

6:4

3:1

000b

11h

12h

000b

7:6

5:3

2:0

000b

(4)

FS1_x: PLL1 frequency selection

FS1_6

FS1_5

FS1_4

13h

14h

15h

0 – f_{VCO1_0}(predefined by PLL1_0 – multiplier/divider value)

1 – f_{VCO1_1}(predefined by PLL1_1 – multiplier/divider value)

FS1_3

FS1_2

FS1_1

FS1_0

0 – PLL1

MUX1

PLL1 multiplexer:

1 – PLL1 bypass (PLL1 is in power down)

0 – Pdiv1

1 – Pdiv2

Output Y2 multiplexer:

Output Y3 Multiplexer:

00 – Pdiv1-divider

01 – Pdiv2-divider

10 – Pdiv3-divider

11 – Reserved

5:4

10b

3:2

1:0

Y2Y3_ST1

Y2Y3_ST0

00b

01b

00 – Y2 and Y3 disabled to Hi-Z state (PLL1 is in power down)

01 – Y2 and Y3 disabled to Hi-Z state

10–Y2 and Y3 disabled to low

Y2, Y3-

State0/1definition:

11 – Y2 and Y3 enabled

(4)

Y2Y3_7

Y2Y3_6

Y2Y3_5

Y2Y3_4

Y2Y3_3

Y2Y3_2

Y2Y3_1

Y2Y3_0

Y2Y3_x output state selection.

0 – State0 (predefined by Y2Y3_ST0)

1 – State1 (predefined by Y2Y3_ST1)

(1) Writing data beyond 20h may adversely affect device function.

(2) All data is transferred MSB-first.

(3) Unless a custom setting is used

(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

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Table 12. PLL1 Configuration Register (continued)

OFFSET⁽¹⁾

BIT⁽²⁾

ACRONYM

DEFAULT⁽³⁾

DESCRIPTION

PLL1 SSC down or center

selection:

0 – Down

1 – Center

SSC1DC

16h

0 – Reset and standby

1 to 127 – Divider value

6:0

Pdiv2

—

00h

7-bit Y2-output-divider Pdiv2:

Reserved – do not write other than 0

7-bit Y3-output-divider Pdiv3:

17h

0 – Reset and standby

1 to 127 – Divider value

6:0

Pdiv3

00h

18h

19h

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_0N [11:4]

PLL1_0N [3:0]

PLL1_0R [8:5]

PLL1_0R[4:0]

PLL1_0Q [5:3]

PLL1_0Q [2:0]

PLL1_0P [2:0]

1FFh

000h

PLL1_0⁽⁵⁾: 30-bit multiplier or divider value for frequency f_{VCO1_0}

(for more information, see PLL Frequency Planning).

1Ah

10h

100b

1Bh

00 – f_{VCO1_0}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_0}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_0}< 175 MHz

1:0

VCO1_0_RANGE

00b

f_{VCO1_0}range selection:

11 – f_{VCO1_0}≥ 175 MHz

1Ch

1Dh

1Eh

7:0

7:4

3:0

7:3

2:0

7:5

4:2

PLL1_1N [11:4]

PLL1_1N [3:0]

PLL1_1R [8:5]

PLL1_1R[4:0]

PLL1_1Q [5:3]

PLL1_1Q [2:0]

PLL1_1P [2:0]

1FFh

000h

PLL1_1⁽⁵⁾: 30-bit multiplier or divider value for frequency f_{VCO1_1}

(for more information, see PLL Frequency Planning).

10h

1Fh

100b

00 – f_{VCO1_1}< 125 MHz

01 – 125 MHz ≤ f_{VCO1_1}< 150 MHz

10 – 150 MHz ≤ f_{VCO1_1}< 175 MHz

1:0

VCO1_1_RANGE

00b

f_{VCO1_1}range selection:

11 – f_{VCO1_1}≥ 175 MHz

(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The CDCE813-Q1 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer which

can be used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE813-Q1 device

features an on-chip loop filter and spread-spectrum modulation. Programming can be done through the I2C

interface, or previously saved settings can be loaded from on-chip EEPROM. The pins S0, S1, and S2 can be

programmed as control pins to select various output settings. This section shows some examples of using the

CDCE813-Q1 device in various applications.

10.2 Typical Application

Figure 14 shows the application example of CDCE813-Q1 in combination with an SoC processor and an FPD-

Link3 serializer, serving as a PCLK jitter cleaner.

VDD_1p8

VDDO_3p3

120 Q

0.1 …F

1000pF

0.1µF

0.01 …F

1000 pF

0.01µF

VDDOUT

VDD

VCTRL

XIN/CLK

XOUT

4.7k

GND

860 Q

18 Q

GND

PCLK

1 lQ

PCLK

GND

SDA

SCL

GND

CDCE813-Q1

SoC

To Display

GND

Serializer

Image Data

Figure 14. PCLK Jitter Cleaner Reference Design

10.2.1 Design Requirements

The CDCE813-Q1 device supports spread-spectrum clocking (SSC) with multiple control parameters:

•

Modulation amount (%)

Modulation frequency (>20 kHz)

Center spread or down spread (± or –)

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

www.ti.com.cn

Typical Application (continued)

Figure 15. Modulation Frequency (fm) and Modulation Amount

10.2.2 Detailed Design Procedure

10.2.2.1 Spread-Spectrum Clock (SSC)

Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread

spectrum can reduce electromagnetic interference (EMI) by reducing the level of emission from clock distribution

network.

CDCS502 with a 25-MHz Crystal, FS = 1, f_OUT= 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC

Figure 16. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock

Spread spectrum clocking can be used to help reduce EMI to meet design specifications. For example, a

specified EMI threshold of 55 dB/mV would require ±1% spread-spectrum clocking to meet this requirement.

CDCE813-Q1

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

Typical Application (continued)

10.2.2.2 PLL Frequency Planning

At a given input frequency (f_IN), the output frequency (f_OUT) of the CDCE813-Q1 device is calculated with

Equation 1.

ƒ_IN

ƒ_OUT

Pdiv

•

M (1 to 511) and N (1 to 4095) are the multiplier or divider values of the PLL,

and Pdiv (1 to 127) is the output divider.

•

(1)

(2)

The target VCO frequency (ƒ_VCO) of each PLL is calculated with Equation 2.

ƒ_VCO= ƒ_IN

The PLL internally operates as fractional divider and needs the following multiplier or divider settings:

•

P = 4 – int(log₂N / M); if P < 0 then P = 0

Q = int(N' / M)

R = N′ – M × Q

where

•

int(X) = integer portion of X

N′ = N × 2^P

N ≥ M

80 MHz ≤ ƒ_VCO≤ 230 MHz

16 ≤ Q ≤ 63

0 ≤ P ≤ 4

0 ≤ R ≤ 51

Example:

for ƒ_IN= 27 MHz; M = 1; N = 4; Pdiv = 2

→ f_OUT= 54 MHz

for ƒ_IN= 27 MHz; M = 2; N = 11; Pdiv = 2

→ f_OUT= 74.25 MHz

→ f_VCO= 108 MHz

→ f_VCO= 148.50 MHz

→ P = 4 – int(log₂4) = 4 – 2 = 2

→ N' = 4 × 2²= 16

→ P = 4 – int(log₂5.5) = 4 – 2 = 2

→ N' = 11 × 2²= 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.

10.2.2.3 Crystal Oscillator Start-Up

When the CDCE813-Q1 device can be used as a crystal buffer, the crystal oscillator start-up dominates the start-

up time compared to the internal PLL lock time. Figure 17 shows the oscillator start-up sequence for a 27-MHz

crystal input with an 8-pF load. The start-up time for the crystal is on the order of approximately 250 µs

compared to approximately 10 µs of lock time. In general, lock time is an order of magnitude less compared to

the crystal start-up time.

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

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Typical Application (continued)

Figure 17. Crystal Oscillator Start-Up vs PLL Lock Time

10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling

The frequency for the CDCE813-Q1 device is adjusted for media and other applications with the VCXO control

input V_ctr. If a PWM-modulated signal is used as a control signal for the VCXO, an external filter is needed.

CDCE813-Q1

Vctrl

PWM

control

signal

Xin/CLK

Xout

Figure 18. Frequency Adjustment Using PWM Input to the VCXO Control

10.2.2.5 Unused Inputs and Outputs

If VCXO-pulling functionality is not required, V_ctrshould be left floating. All other unused inputs should be set to

GND. Unused outputs should be left floating.

If one output block is not used, TI recommends disabling it. However, TI recommends providing a supply for all

output blocks, even if they are disabled.

10.2.2.6 Switching Between XO and VCXO Mode

When the CDCE813-Q1 device is in the crystal-oscillator or VCXO configuration, the internal capacitors require

different internal capacitance. The following steps are recommended to switch to VCXO mode when the

configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:

1. While in XO mode, put V_ctr= V_DD/ 2

2. Switch from XO mode to VCXO mode

3. Program the internal capacitors to obtain 0 ppm at the output.

CDCE813-Q1

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

Typical Application (continued)

10.2.3 Application Curves

Figure 19, Figure 20, Figure 21, and Figure 22 show CDCE813-Q1 measurements with the SSC feature enabled.

Device configuration: 27-MHz input, 27-MHz output.

Figure 19. f_OUT= 27 MHz,

Figure 20. f_OUT= 27 MHz,

VCO frequency < 125 MHz, SSC (2% Center)

VCO frequency > 175 MHz, SSC (1%, Center)

Figure 22. Output Spectrum With SSC On,

2% Center

Figure 21. Output Spectrum With SSC Off

11 Power Supply Recommendations

There is no restriction on the power-up sequence. In case V_DDOUTis applied first, TI recommends grounding the

V_DD. In case V_DDOUTis powered while V_DDis floating, there is a risk of high current flowing on the V_DDOUTpins.

The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled

until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,

including the outputs. If a 3.3-V V_DDOUTis available before the 1.8-V, the outputs stay disabled until the 1.8-V

supply has reached a certain level.

CDCE813-Q1

ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

www.ti.com.cn

12 Layout

12.1 Layout Guidelines

When the CDCE813-Q1 device is used as a crystal buffer, any parasitic across the crystal affect the pulling

range of the VCXO. Therefore, take care in placing the crystal units on the board. Crystals must be placed as

close to the device as possible, ensuring that the routing lines from the crystal terminals to Xin and Xout have the

same length.

If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the

device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise

coupling.

Additional discrete capacitors can be required to meet the load capacitance specification of certain crystals. For

example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can

range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an

internal 10-pF capacitor.

To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the

device as possible and symmetrically with respect to Xin and Xout.

Figure 23 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors. For

component-side mounting, use 0402 body-size capacitors to facilitate signal routing. Keep the connections

between the bypass capacitors and the power supply on the device as short as possible. Ground the other side

of the capacitor using a low-impedance connection to the ground plane.

12.2 Layout Example

Place crystal with associated load

capacitors close to the chip.

Place series termination resistors at

clock outputs to improve signal integrity.

Place bypass capacitors close to the

Use ferrite beads to isolate the device

supply pins from board noise sources.

device pins; ensure wide frequency range.

Figure 23. Annotated Layout

CDCE813-Q1

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ZHCSG21C –JANUARY 2017–REVISED APRIL 2019

13 器件和文档支持

13.1 文档支持

13.1.1 相关文档

请参阅如下相关文档：

•

《面向 CDCE(L)9xx 系列的 VCXO 应用指南》（文献编号：SCAA085）

《针对 CDCE(L)9xx 系列选择晶振的实际问题》（文献编号：SLEA071）

《针对 CDCE(L)9xx 系列的 I2C/EEPROM 常规使用》（文献编号：SCAA104）

《使用硅器件替代晶体或晶体振荡器》（文献编号：SNAA217）

《I²C 在 CDCE(L)949、CDCE(L)937、CDCE(L)925、CDCE(L)813 中的应用》(SCAA105)

《使用低频字时钟为音频数据转换器生成低相位噪声时钟》（文献编号：SCAA088）

13.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.4 商标

DaVinci, OMAP, ClockPro, E2E are trademarks of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

13.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CDCE813QPWRQ1

ACTIVE

TSSOP

2000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 105

CE813Q

E813Q02

CDCE813R02TPWRQ1

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCE813QPWRQ1

TSSOP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

CDCE813R02TPWRQ1 TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCE813QPWRQ1

TSSOP

2000

356.0

35.0

CDCE813R02TPWRQ1

Pack Materials-Page 2

重要声明和免责声明

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCE813QPWRQ1 [TI]

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