CDCE949 [TI]
Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs; 可编程4 -PLL VCXO时钟合成器与1.8V ， 2.5V和3.3V LVCMOS输出
| 型号： | CDCE949 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs |
| 文件： | 总31页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCE949
CDCEL949
www.ti.com
SCAS844–JUNE 2007
Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs
FEATURES
–
Three User-Definable Control Inputs
[S0/S1/S2] e.g. SSC-Selection, Frequency
Switching, Output Enable or Power Down
•
Member of Programmable Clock Generator
Family
–
–
–
Programmable SSC Modulation
Enables 0-PPM Clock Generation
–
–
–
–
CDCE949/CDCEL949: 4 PLLs, 9 Outputs
CDCE937/CDCEL937: 3 PLLs, 7 Outputs
CDCE925/CDCEL925: 2 PLLs, 5 Outputs
CDCE913/CDCEL913: 1 PLLs, 3 Outputs
Generates Common Clock Frequencies
Used with TI DaVinci™, OMAP™, DSPs
–
Generates Highly-Accurate Clocks for
Video, Audio, USB, IEEE1394, RFID,
BlueTooth™, WLAN, Ethernet and GPS
•
•
In-System Programmability and EEPROM
–
–
Serial Programmable Volatile Register
Non-Volatile EEPROM to Store Customer
Settings
•
•
1.8 V Device Power Supply
Separate Output Supply Pins
Very Flexible Input Clocking Concept
–
–
CDCE949: 3.3 V and 2.5 V
CDCEL949: 1.8 V
–
–
–
External Crystal: 8 to 32 MHz
On-Chip VCXO: Pull-Range ±150 ppm
Single-Ended LVCMOS up to 160 MHz
•
•
•
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
•
•
Selectable Output Frequency up to 230 MHz
Very Low-Noise PLL Core
Development and Programming Kit for Ease
PLL Design and Programming (TI-Pro Clock)
–
–
Integrated PLL Loop Filter Components
Very Low Period Jitter (typ 60 ps)
APPLICATIONS
•
D-TV, HD-TV, STB, IP-STB, DVD-Player,
DVD-Recorder, Printer
•
Highly Flexible Clock Driver
•
General Purpose Frequency Synthesizing
VDDOUT
VDD
GND
Vctr
LV
CMOS
Y1
VCXO
XO
LV
CMOS
LVCMOS
Y2
PLL1
EEPROM
with SSC
3
LV
CMOS
Programming
and
Control Register
Y3
S2/S1/S0 or
SDA/SCL
Xin/Clk
S0
Vdd
1
2
3
4
5
6
7
8
9
24 Xout
23 S1/SDA
22 S2/SCL
21 Y1
LV
CMOS
Y4
Y5
Y6
Y7
Y8
Y9
Vctr
PLL2
GND
Vddout
Y4
20 GND
19 Y2
Divider
and
with SSC
LV
CMOS
Output
Control
18 Y3
Y5
GND
17 Vddout
16 Y6
LV
CMOS
Vddout 10
Y8 11
Y9 12
15 Y7
PLL3
14 GND
13 Vdd
with SSC
LV
CMOS
LV
CMOS
PLL4
with SSC
LV
CMOS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, OMAP, Pro Clock are trademarks of Texas Instruments.
BlueTooth is a trademark of Bluetooth SIG, Inc.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
CDCE949
CDCEL949
www.ti.com
SCAS844–JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock
synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent
configurable PLLs.
The CDCx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for
CDCE949.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external
control signal, i.e. a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as
27-MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration (see the Default Device Configuration section). It can be
reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system
programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation
including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and
choosing between low level or 3-state for the output-disable function.
The CDCx949 operates in a 1.8-V environment. It is characterized for operation from –40°C to 85°C.
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
NAME
NO. (TSSOP24)
21, 19, 18, 7, 8,
16, 15, 11, 12
Y1, Y2, ...Y9
O
LVCMOS outputs
Xin/CLK
Xout
1
24
I
O
I
Crystal oscillator input or LVCMOS clock input (selectable via SDA/SCL bus)
Crystal oscillator output (leave open or pull up when not used)
VCXO control voltage (leave open or pull up when not used)
VCtrl
4
VDD
3, 13
Power 1.8V power supply for the device
CDCEL949: 1.8 V supply for all outputs
Power
VDDOUT
6, 10, 17
CDCE949: 3.3 V or 2.5 V supply for all outputs
GND
S0
5, 9, 14, 20
2
Ground Ground
I
User-programmable control input S0; LVCMOS inputs; internal pull-up 500 kΩ
SDA: Bi-directional serial data input/output (default configuration), LVCMOS; internal
pull-up 500 kΩ; or
S1: User-programmable control input; LVCMOS inputs; internal pull-up 500 kΩ
SDA / S1
SCL / S2
23
22
I/O / I
SCL: Serial clock input (default configuration), LVCMOS; internal pull-up 500 kΩ; or
S2: User-programmable control input; LVCMOS inputs; internal pull-up 500 kΩ
I
2
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CDCEL949
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SCAS844–JUNE 2007
FUNCTIONAL BLOCK DIAGRAM
VDDOUT
VDD
GND
Input Clock
Vctr
LV
CMOS
Pdiv1
10-Bit
Y1
Xin/CLK
VCXO
XO
LV
CMOS
Pdiv2
7-Bit
Y2
Y3
PLL 1
LVCMOS
with SSC
Xout
LV
CMOS
Pdiv3
7-Bit
PLL Bypass
EEPROM
Programming
and
S0
S1/SDA
S2/SCL
LV
CMOS
SDA/SCL
Register
Pdiv4
7-Bit
Y4
Y5
PLL 2
with SSC
LV
CMOS
Pdiv5
7-Bit
PLL Bypass
LV
CMOS
Pdiv6
7-Bit
Y6
Y7
PLL 3
with SSC
LV
CMOS
Pdiv7
7-Bit
PLL Bypass
LV
CMOS
Pdiv8
7-Bit
Y8
Y9
PLL 4
with SSC
LV
CMOS
Pdiv9
7-Bit
PLL Bypass
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.5 to 2.5
UNIT
V
VDD
VI
Supply voltage range
Input voltage range(2)
–0.5 to VDD + 0.5
V
VO
II
Output voltage range(2)
Input current (Vi < 0, Vi > VDD
Continuous output current
Storage temperature range
–0.5 to VDDOUT + 0.5
V
)
20
50
mA
mA
°C
IO
Tstg
TJ
–65 to 150
125
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
3
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CDCEL949
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SCAS844–JUNE 2007
THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE(1)
AIRFLOW
(lfm)
TSSOP24
°C/W
PARAMETER
0
85
150
250
500
—
80
TJA
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
78
76
TJC
26
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
RECOMMENDED OPERATING CONDITIONS
MIN
1.7
2.3
1.7
NOM
MAX
1.9
UNIT
VDD
Device supply voltage
1.8
V
CDCE949
3.6
Output Yx supply
voltage
VDD(OUT)
V
CDCEL949
1.9
VIL
Low level input voltage LVCMOS
High level input voltage LVCMOS
Input voltage threshold LVCMOS
Input voltage range S0
0.3 × VDD
V
V
V
VIH
0.7 × VDD
VI(thresh)
0.5 × VDD
0
0
0
1.9
3.6
VIS
V
Input voltage range S1, VIthresh = 0.5 VDD
S2, SDA, SCL
VICLK
Input voltage range CLK
VDDout = 3.3 V
1.9
±12
±10
±8
V
mA
mA
mA
pF
IOH /IOL
Output current
VDDout = 2.5 V
VDDout = 1.8 V
CL
TA
Output load LVCMOS
10
Operating free-air temperature
–40
85
°C
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1)
MIN
NOM
MAX
32
UNIT
MHz
Ω
fXtal
Crystal Input frequency range (fundamental mode)
Effective series resistance
Pulling range (0 V ≤ VCtrl ≤ 1.8 V)(2)
8
27
ESR
fPR
100
±120
±150
ppm
V
V(Ctrl)
C0/C1
CL
Frequency control voltage
0
VDD
220
20
Pullability ratio
On-chip load capacitance at Xin and Xout
0
pF
(1) For more information about VCXO configuration and crystal recommendation see application report SCAA085.
(2) Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report SCAA085.
EEPROM SPECIFICATION
MIN
1000
10
TYP
MAX
UNIT
cycles
years
EEcyc
EEret
EEcyc programming cycles of EEPROM
EEret data retention
4
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CDCEL949
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SCAS844–JUNE 2007
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load and operating free-air temperature
CLK_IN Requirements
MIN
0
NOM
MAX
160
160
3
UNIT
MHz
ns
PLL Bypass Mode
f(CLK)
LVCMOS clock input frequency
PLL Mode
8
tr / tf
Rise and fall time CLK signal (20% to 80%)
Duty cycle CLK at VDD / 2
dutyCLK
40%
60%
STANDARD
MODE
FAST
MODE
SDA/SCL TIMING REQUIREMENTS (see Figure 12)
UNIT
MIN
0
MAX
MIN MAX
f(SCL)
SCL clock frequency
100
0
0.6
0.6
1.3
0.6
0
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
tsu(START)
th(START)
tw(SCLL)
tw(SCLH)
th(SDA)
tsu(SDA)
tr
START setup time (SCL high before SDA low)
START hold time (SCL low after SDA low)
SCL low-pulse duration
4.7
4
4.7
4
SCL high-pulse duration
SDA hold time (SDA valid after SCL low)
SDA setup time
0
3.45
0.9
250
100
SCL/SDA input rise time
1000
300
300
300
tf
SCL/SDA input fall time
tsu(STOP)
tBUF
STOP setup time
4.0
4.7
0.6
1.3
Bus free time between a STOP and START condition
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
OVERALL PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
All PLLs on
Per PLL
38
9
All outputs off, fCLK = 27
MHz, fVCO= 135 MHz;
IDD
Supply current (see Figure 3)
mA
CDCE949
VDDOUT=3.3 V
4
Supply current (see Figure 4 and
Figure 5)
No load, all outputs on,
fout = 27 MHz
IDD(OUT)
mA
CDCEL949
VDDOUT=1.8 V
2
Power down current. Every circuit
powered down except SDA/SCL
IDD(PD)
V(PUC)
fIN = 0 MHz, VDD = 1.9 V
50
μA
Supply voltage Vdd threshold for power
up control circuit
0.85
1.45
230
V
fVCO
fOUT
VCO frequency range of PLL
LVCMOS output frequency
80
MHz
MHz
230
LVCMOS PARAMETER
VIK
II
LVCMOS input voltage
VDD = 1.7 V; II = –18 mA
VI = 0 V or VDD; VDD = 1.9 V
VI = VDD; VDD = 1.9 V
VI = 0 V; VDD = 1.9 V
VICLK = 0 V or VDD
–1.2
±5
5
V
LVCMOS input current
μA
μA
μA
IIH
IIL
LVCMOS input current for S0/S1/S2
LVCMOS input current for S0/S1/S2
Input capacitance at Xin/Clk
Input capacitance at Xout
–4
6
2
3
CI
VIXout = 0 V or VDD
pF
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
(1) All typical values are at respective nominal VDD
.
5
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DEVICE CHARACTERISTICS (Continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CDCE949 – LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VDDOUT = 3 V, IOH = –0.1 mA
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
2.9
2.4
2.2
VOH
LVCMOS high-level output voltage
VDDOUT = 3 V, IOH = –8 mA
VDDOUT = 3 V, IOH = –12 mA
VDDOUT = 3 V, IOL = 0.1 mA
VDDOUT = 3 V, IOL = 8 mA
VDDOUT = 3 V, IOL = 12 mA
V
V
0.1
0.5
0.8
VOL
LVCMOS low-level output voltage
tPLH
tPHL
,
Propagation delay
Rise and fall time
PLL bypass
3.2
ns
ns
tr/tf
VDDOUT = 3.3 V (20%–80%)
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
fOUT = 50 MHz; Y1-to-Y3
0.6
60
90
170
100
180
60
tjit(cc)
Cycle-to-cycle jitter(2)(3)
ps
ps
120
70
(2)(3)
tjit(per)
Peak-to-peak period jitter
130
tsk(o)
odc
Output skew(4)
ps
%
fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9
fVCO = 100 MHz; Pdiv = 1
160
55
Output duty cycle(5)
45
CDCE949 – LVCMOS PARAMETER FOR VDDOUT = 2.5 V – MODE
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
1.7
1.6
VOH
LVCMOS high-level output voltage
VDDOUT = 2.3 V, IOH = –6 mA
VDDOUT = 2.3 V, IOH = –10 mA
VDDOUT = 2.3 V, IOL = 0.1 mA
VDDOUT = 2.3 V, IOL = 6 mA
VDDOUT = 2.3 V, IOL = 10 mA
V
0.1
0.5
0.7
VOL
LVCMOS low-level output voltage
V
tPLH
tPHL
,
Propagation delay
Rise and fall time
PLL bypass
3.4
ns
tr/tf
VDDOUT = 2.5 V (20%–80%)
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
fOUT = 50 MHz; Y1-to-Y3
0.8
60
ns
ps
90
170
100
180
60
(2)(3)
tjit(cc)
Cycle-to-cycle jitter
120
70
ps
(2)(3)
tjit(per)
Peak-to-peak period jitter
130
tsk(o)
odc
Output skew(4)
ps
%
fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9
fVCO = 100 MHz; Pdiv = 1
160
55
Output duty cycle(5)
45
(1) All typical values are at respective nominal VDD
.
(2) 10000 cycles.
(3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data
sampled on rising edge (tr).
(5) odc depends on output rise- and fall-time (tr/tf).
6
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DEVICE CHARACTERISTICS (Continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
SAVE THIS CDCEL949 – LVCMOS PARAMETER FOR VDDOUT = 1.8 V – MODE
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
1.4
1.1
VOH
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –4 mA
VDDOUT = 1.7 V, IOH = –8 mA
VDDOUT = 1.7 V, IOL = 0.1 mA
VDDOUT = 1.7 V, IOL = 4 mA
VDDOUT = 1.7 V, IOL = 8 mA
V
0.1
0.3
0.6
VOL
V
tPLH
tPHL
,
Propagation delay
Rise and fall time
PLL bypass
2.6
ns
tr/tf
VDDOUT = 1.8 V (20%–80%)
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
1 PLL switching, Y2-to-Y3
4 PLLs switching, Y2-to-Y9
fOUT = 50 MHz; Y1-to-Y3
0.7
70
ns
ps
120
170
140
190
60
tjit(cc)
Cycle-to-cycle jitter(2) (3)
120
90
ps
ps
%
(2)(3)
tjit(per)
Peak-to-peak period jitter
130
tsk(o)
odc
Output skew(4)
fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9
fVCO = 100 MHz; Pdiv = 1
160
55
Output duty cycle(5)
45
SDA/SCL PARAMETER
VIK
IIH
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
VI = VDD; VDD = 1.9 V
–1.2
V
μA
V
SCL and SDA input current
SDA/SCL input high voltage(6)
±10
VIH
0.7 VDD
0.3
VDD
VIL
SDA/SCL input low voltage(6)
V
0.2
VDD
VOL
CI
SDA low-level output voltage
SCL/SDA input capacitance
IOL = 3 mA, VDD = 1.7 V
V
VI = 0 V or VDD
.
3
10
pF
(1) All typical values are at respective nominal VDD
(2) 10000 cycles.
(3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from same divider; data
sampled on rising edge (tr).
(5) odc depends on output rise- and fall-time (tr/tf).
(6) SDA and SCL pins are 3.3-V tolerant.
PARAMETER MEASUREMENT INFORMATION
CDCE949
CDCEL949
CDCE949
CDCEL949
1 kW
1 kW
LVCMOS
LVCMOS
LVCMOS
10 pF
Series
Termination
(Optional)
Driver
Impedance
~ 50 W
Line Impedance
Zo = 50 W
Figure 1. Test Load
Figure 2. Test Load for 50 Ω Board Environment
7
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CDCEL949
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TYPICAL CHARACTERISTICS
CDCE949 AND CDCEL949 SUPPLY CURRENT
CDCE949 OUTPUT CURRENT
vs
vs
PLL FREQUENCY
OUTPUT FREQUENCY
100
90
35
30
25
20
V
V
= 1.8 V,
DD
V
= 1.8 V
DD
= 3.3 V,
9 outputs on
7 outputs on
5 outputs on
DDOUT
No Load
80
4 PLL on
3 PLL on
2 PLL on
1 PLL on
all PLL off
70
60
50
40
30
3 outputs on
1 output on
15
10
5
all outputs off
20
10
0
0
10
60
110
160
210
10 30 50 70 90 110 130 150 170 190 210 230
PLL - Frequency - MHz
f
- Output Frequency - MHz
OUT
Figure 3.
Figure 4.
CDCEL949 OUTPUT CURRENT
vs
OUTPUT FREQUENCY
12
V
= 1.8 V,
DD
9 outputs on
V
= 1.8 V,
DDOUT
No Load
7 outputs on
10
8
5 outputs on
3 outputs on
1 output on
6
all outputs off
4
2
0
10 30 50 70 90 110 130 150 170 190 210 230
f
- Output Frequency - MHz
OUT
Figure 5.
8
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APPLICATION INFORMATION
Control Terminal Configuration
The CDCE949/CDCEL949 has three user-definable control terminals (S0, S1 and S2) which allow external
control of device settings. They can be programmed to perform any of the following functions:
•
•
•
Spread-Spectrum Clocking selection: Spread-type and spread-amount selection
Frequency selection: Switching between any of two user-defined frequencies
Output-State selection: Output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
External Control-Bits
PLL1 Setting
PLL2 Setting
PLL3 Setting
PLL4 Setting
Y1 Setting
Control Function
Table 2. PLLx Setting (can be selected for each PLL individual)(1)
SSC Selection (Center/Down)
SSCx [3-bits]
Center
0% (off)
±0.25%
±0.5%
Down
0% (off)
–0.25%
–0.5%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
±0.75%
±1.0%
–0.75%
–1.0%
±1.25%
±1.5%
–1.25%
–1.5%
±2.0%
–2.0%
FREQUENCY SELECTION(2)
FSx
0
FUNCTION
Frequency0
Frequency1
1
OUTPUT SELECTION(3) (Y2 ... Y9)
YxYx
FUNCTION
0
1
State0
State1
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
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CDCEL949
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Table 3. Y1 Setting(1)
Y1 SELECTION
Y1
0
FUNCTION
State 0
State 1
1
(1) State0 and State1 are user-definable in Generic Configuration
Register and can be power down, 3-state, low or active.
The S1/SDA and S2/SCL pins of the CDCE949/CDCEL949 are dual-function pins. In the default configuration
they are defined as SDA/SCL for the serial interface. They can be programmed as control pins (S1/S2) by
setting the appropriate bits in the EEPROM. Note that changes to the Control register (Bit [6] of Byte 02) have
no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control-pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE949/CDCEL949 is preconfigured as shown in Figure 6. (The input frequency is
passed through to the output as a default.) This allows the device to operate in default mode without the extra
production step of programming it. The default setting appears after power is supplied or after a power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL Interface.
VDDOUT
VDD
GND
Input Clock
LV
CMOS
Pdiv1 =1
Y1 = 27MHz
Xin
27 MHz
Crystal
X-tal
LV
CMOS
Y2 = 27 MHz
Y3 = 27 MHz
PLL 1
power down
Pdiv2 = 1
Xout
S0
LV
CMOS
Pdiv3 = 1
PLL Bypass
EEPROM
“1” = outputs enabled
“0” = outputs 3-State
Programming Bus
Programming
and
SDA
SCL
LV
CMOS
SDA/SCL
Register
Y4 = 27 MHz
Y5 = 27 MHz
PLL 2
Pdiv4 = 1
Pdiv5 = 1
power down
LV
CMOS
PLL Bypass
LV
CMOS
Y6 = 27 MHz
Y7 = 27 MHz
PLL 3
Pdiv6 = 1
Pdiv7 = 1
power down
LV
CMOS
PLL Bypass
LV
CMOS
Y8 = 27 MHz
Y9 = 27 MHz
PLL 4
Pdiv8 = 1
Pdiv9 = 1
power down
LV
CMOS
PLL Bypass
Figure 6. Default Configuration
A different default setting can be programmed upon customer request. Contact Texas Instruments sales or
marketing representative for more information.
Table 4 shows the default setting for the Control Terminal Register (external control pins). In normal operation,
all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be
selected with S0, as S1 and S2 are configured as programming pins in default mode.
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Table 4. Factory Default Setting for Control Terminal Register
Y1
PLL1 SETTING
PLL2 SETTING
PLL3 SETTING
PLL4 SETTING
EXTERNAL
CONTROL-PINS(1)
Output
Select
Freq.
SSC
Sel.
Output
Freq.
SSC
Sel.
Output
Freq.
SSC
Sel.
Output
Freq.
SSC
Sel.
Output
Select
Select
Select
Select
Select
Select
Select
Select
S2
S1
S0
0
Y1
FS1
SSC1
off
Y2Y3
FS2
SSC2
off
Y4Y5
FS3
SSC3
off
Y6Y7
FS4
SSC4
off
Y8Y9
3-State
enabled
SCL (I2C) SDA (I2C)
SCL (I2C) SDA (I2C)
3-State
fVCO1_0
3-State
fVCO2_0
3-State
fVCO3_0
3-State
fVCO4_0
1
enabled fVCO1_0
off
enabled fVCO2_0
off
enabled fVCO3_0
off
enabled fVCO4_0
off
(1) In default mode or when programmed respectively, S1 and S2 act as a serial programming interface, SDA/SCL. In this mode, they have
no control-pin function, but are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as pre-defined above).
SDA/SCL SERIAL INTERFACE
The CDCE949/CDCEL949 operates as a slave device on the 2-wire serial SDA/SCL bus, compatible with the
popular SMBus or I2C™ specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode
transfer (up to 400 kbps) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDC9xx are dual-function pins. In the default configuration they are used
as SDA/SCL serial programming interface. They can be reprogrammed as general purpose control pins, S1 and
S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].
DATA PROTOCOL
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The number of
bytes read out is defined by the Byte Count field in the Generic Configuration Register. During a Block Read
instruction, the entire number of bytes defined in Byte Count must be read out to correctly finish the read cycle.
When a byte is sent to the device, it is written into the internal register and immediately takes effect. This applies
to each transferred byte, whether in a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During
this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can
be read during the programming sequence (Byte Read or Block Read). The programming status can be
monitored by reading EEPIP, Byte 01–Bit [6].
The offset of the indexed byte is encoded in the command code, as described in Table 6.
Table 5. Slave Receiver Address (7 bits)
Device
A6
1
A5
1
A4
0
A3
0
A2
1
A1(1)
A0(1)
R/W
1/0
1/0
1/0
1/0
CDCE913/CDCEL913
CDCE925/CDCEL925
CDCE937/CDCEL937
CDCE949/CDCEL949
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
(1) Address bits A0 and A1 are programmable via the SDA/SCL bus (Byte 01, Bit [1:0]. This allows addressing up to 4 devices connected to
the same SDA/SCL bus. The least significant bit of the address byte designates a write or read operation.
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CDCEL949
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Table 6. Command Code Definition
BIT
7
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
(6:0)
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
7
1
1
8
1
1
S
Slave Address
A
Data Byte
A
P
R/W
LSB
MSB
MSB
LSB
S
Start Condition
Sr Repeated Start Condition
R/W 1 = Read (Rd) from CDCE9xx device; 0 = Write (Wr) to the CDCE9xxx
A
P
Acknowledg (ACK = 0 and NACK =1)
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 7. Generic Programming Sequence
Byte Write Programming Sequence
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
CommandCode
A
Data Byte
A
P
Figure 8. Byte Write Protocol
Byte Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
S
Slave Address
Rd
A
8
1
1
Data Byte
A
P
Figure 9. Byte Read Protocol
Block Write Programming Sequence
1
7
1
1
8
1
8
1
S
Slave Address
Wr
A
CommandCode
A
Byte Count = N
A
8
1
8
1
8
1
1
Data Byte 0
A
Data Byte 1
A
…
Data Byte N-1
A
P
NOTE: Data Byte 0 Bits [7:0] is reserved for Revision Code and Vendor Identification. Also it is used for internal test purpose
and should not be overwritten.
Figure 10. Block Write Programming
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CDCEL949
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Block Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
Sr
Slave Address
Rd
A
8
1
8
1
8
1
1
Byte Count N
A
Data Byte 0
A
…
Data Byte N-1
A
P
Figure 11. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
Bit 7 (MSB)
Bit 6
Bit 0 (LSB)
P
S
A
P
t
t
t
r
t
f
w(SCLL)
w(SCLH)
V
IH
SCL
V
IL
t
t
h(START)
SU(START)
t
t
t
SU(STOP)
h(SDA)
SU(SDA)
t
t
(BUS)
r
t
f
V
IH
SDA
V
IL
Figure 12. Timing Diagram for the SDA/SCL Serial Control Interface
SDA/SCL Hardware Interface
Figure 13 shows how the CDCE949/CDCEL949 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the
maximum) if many devices are connected.
Note that the pull-up resistor value (RP) depends on the supply voltage, bus capacitance and number of
connected devices. The recommended pull-up value is 4.7 kΩ. It must meet the minimum sink current of 3 mA
at VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification).
CDCE949
CDCEL949
R
R
Master
SDA
P
P
Slave
SCL
C
C
BUS
BUS
Figure 13. SDA/SCL Hardware Interface
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SDA/SCL CONFIGURATION REGISTERS
The clock input, control pins, PLLs and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE949/CDCEL949. All settings can be manually
written to the device via the SDA/SCL bus, or are easily programmable by using the TI Pro Clock software. TI
Pro Clock software allows the user to quickly make all settings and automatically calculates the values for
optimized performance at lowest jitter.
Table 7. SDA/SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
Generic Configuration Register
PLL1 Configuration Register
PLL2 Configuration Register
PLL3 Configuration Register
PLL4 Configuration Register
TABLE
Table 9
00h
10h
20h
30h
40h
Table 10
Table 11
Table 12
Table 13
The grey-highlighted Bits described in the Configuration Registers tables on the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings can then
be selected by the external control pins, S0, S1, and S2 (See the Control Terminal Configuration section).
Table 8. Configuration Register, External Control Terminals
Y1
PLL1 SETTING
PLL2 SETTING
PLL3 SETTING
PLL4 SETTING
EXTERNAL
CONTROL
PINS
Output
Select
Freq.
SSC
Output
Freq.
SSC
Output
Freq.
SSC
Output
Freq.
SSC
Output
Select
Select
Select
Select
Select
Select
Select
Select
Select
Select
Select
Select
S2 S1 S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
FS4
SSC4
Y8Y9
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y1_0
Y1_1
Y1_2
Y1_3
Y1_4
Y1_5
Y1_6
Y1_7
FS1_0
FS1_1
FS1_2
FS1_3
FS1_4
FS1_5
FS1_6
FS1_7
SSC1_0 Y2Y3_0
SSC1_1 Y2Y3_1
SSC1_2 Y2Y3_2
SSC1_3 Y2Y3_3
SSC1_4 Y2Y3_4
SSC1_5 Y2Y3_5
SSC1_6 Y2Y3_6
SSC1_7 Y2Y3_7
FS2_0
FS2_1
FS2_2
FS2_3
FS2_4
FS2_5
FS2_6
FS2_7
SSC2_0 Y4Y5_0
SSC2_1 Y4Y5_1
SSC2_2 Y4Y5_2
SSC2_3 Y4Y5_3
SSC2_4 Y4Y5_4
SSC2_5 Y4Y5_5
SSC2_6 Y4Y5_6
SSC2_7 Y4Y5_7
FS3_0
FS3_1
FS3_2
FS3_3
FS3_4
FS3_5
FS3_6
FS3_7
SSC3_0 Y6Y7_0
SSC3_1 Y6Y7_1
SSC3_2 Y6Y7_2
SSC3_3 Y6Y7_3
SSC3_4 Y6Y7_4
SSC3_5 Y6Y7_5
SSC3_6 Y6Y7_6
SSC3_7 Y6Y7_7
FS4_0
FS4_1
FS4_2
FS4_3
FS4_4
FS4_5
FS4_6
FS4_7
SSC4_0 Y8Y9_0
SSC4_1 Y8Y9_1
SSC4_2 Y8Y9_2
SSC4_3 Y8Y9_3
SSC4_4 Y8Y9_4
SSC4_5 Y8Y9_5
SSC4_6 Y8Y9_6
SSC4_7 Y8Y9_7
Addr.
04h
13h
10h-12h
15h
23h
20h-22h
25h
33h
30h-32h
35h
43h
40h-42h
45h
Offset(1)
(1) Address Offset refers to the byte address in the Configuration Register on following pages.
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CDCEL949
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Table 9. Generic Configuration Register
OFFSET(1)
Bit(2)
7
Acronym
E_EL
RID
Default(3)
DESCRIPTION
00h
xb
0h
1h
0b
Device Identification (read only): ‘1’ is CDCE949 (3.3V), ‘0’ is CDCEL949 (1.8V)
Revision Identification Number (read only)
6:4
3:0
7
VID
Vendor Identification Number (read only)
01h
–
Reserved - always write 0
EEPROM Programming
Status(4): (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
6
5
EEPIP
0b
0b
Permanently Lock EEPROM
0 – EEPROM is not locked
1 – EEPROM will be permanently locked
EELOCK
Data(5)
:
Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
4
PWDN
0b
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-State)
Input clock selection:
00 – X-tal
01 – VCXO
10 – LVCMOS
11 – reserved
3:2
1:0
7
INCLK
SLAVE_ADR
M1
00b
00b
1b
Programmable Address Bits A0 and A1 of the Slave Receiver Address
02h
Clock source selection for output Y1:
0 – input clock
1 – PLL1 clock
Operation mode selection for pin 22/23(6)
6
SPICON
Y1_ST1
0b
0 – serial programming interface SDA (pin 23) and SCL (pin 22)
1 – control pins S1 (pin 23) and S2 (pin 22)
5:4
11b
Y1-State0/1 Definition (applies to Y1_ST1 and Y1_ST0)
00 – device power down (all PLLs in power down and all outputs in 3-state)
01 – Y1 disabled to 3-state
10 – Y1 disabled to low
3:2
Y1_ST0
01b
11 – Y1 enabled (normal operation)
1:0
7:0
7
Pdiv1 [9:8]
Pdiv1 [7:0]
Y1_7
10-Bit Y1-Output-Divider Pdiv1:
0 – divider reset and stand-by
1-to-1023 – divider value
001h
03h
04h
0b
0b
0b
0b
0b
0b
1b
0b
Y1_x State Selection(7)
6
Y1_6
0 – State0 (predefined by Y1-State0 Definition [Y1_ST0])
1 – State1 (predefined by Y1-State1 Definition [Y1_ST1])
5
Y1_5
4
Y1_4
3
Y1_3
2
Y1_2
1
Y1_1
0
Y1_0
Vctr
Xin
05h
Crystal load capacitor
selection(8)
00h → 0 pF
01h → 1 pF
02h → 2 pF
14h-to-1Fh → 20 pF
:
VCXO
XO
20pF
20pF
i.e.
XCSEL = 10pF
7:3
2:0
XCSEL
—
0Ah
0b
Xout
Reserved - do not write others than 0
(1) Writing data beyond ‘50h’ may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless custom setting is used.
(4) During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read during the programming sequence (Byte Read or Block Read).
(5) If this bit is set high in the EEPROM, the actual data in the EEPROM is permanently locked, and no further programming is possible.
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no
longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM
(6) Selection of control-pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. These settings can
then be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to do
a fine adjustment of CL by few pF. The value of CL can be programmed with a resolution of 1 pF for a total crystal load range of 0 pF to
20 pF. For CL > 20 pF use additional external capacitors. Also, the device input capacitance must be considered; this adds 1.5 pF
(6pF//2pF) to the selected CL. For more information about VCXO configuration and crystal recommendations, see application report
SCAA085
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CDCEL949
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Table 9. Generic Configuration Register (continued)
OFFSET(1)
Bit(2)
Acronym
Default(3)
DESCRIPTION
06h
7-Bit Byte Count (Defines the number of Bytes which will be sent from this device at the next Block
Read transfer; all bytes must be read out to correctly finish the read cycle.)
7:1
BCOUNT
50h
(9)
Initiate EEPROM Write Cycle(4)
0
EEWRITE
—
0b
0h
0 – no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register are saved to the EEPROM)
07h-0Fh
—
Reserved – do not write others than 0
(9) NOTE: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are written into the EEPROM.
The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle.
The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP.
If EELOCK is set high, no EEPROM programming will be possible.
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CDCEL949
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Table 10. PLL1 Configuration Register
OFFSET(1)
Bit(2)
7:5
4:2
1:0
7
Acronym
SSC1_7 [2:0]
SSC1_6 [2:0]
SSC1_5 [2:1]
SSC1_5 [0]
SSC1_4 [2:0]
SSC1_3 [2:0]
SSC1_2 [2]
SSC1_2 [1:0]
SSC1_1 [2:0]
SSC1_0 [2:0]
FS1_7
Default(3)
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount)(4)
10h
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
11h
6:4
3:1
0
000b
000b
000b
12h
13h
7:6
5:3
2:0
7
000b
000b
0b
FS1_x: PLL1 Frequency Selection(4)
6
FS1_6
0b
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
14h
PLL1 Multiplexer:
0 – PLL1
7
6
MUX1
M2
1b
1b
1 – PLL1 Bypass (PLL1 is in power down)
Output Y2 Multiplexer:
Output Y3 Multiplexer:
0 – Pdiv1
1 – Pdiv2
00 – Pdiv1-Divider
01 – Pdiv2-Divider
10 – Pdiv3-Divider
11 – reserved
5:4
M3
10b
3:2
1:0
Y2Y3_ST1
Y2Y3_ST0
11b
01b
Y2,
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
Y3-State0/1definition:
11 – Y2/Y3 enabled (normal operation, PLL1 on)
Y2Y3_x Output State Selection(4)
15h
7
6
5
4
3
2
1
0
Y2Y3_7
Y2Y3_6
Y2Y3_5
Y2Y3_4
Y2Y3_3
Y2Y3_2
Y2Y3_1
Y2Y3_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
16h
17h
PLL1 SSC down/center selection:
7-Bit Y2-Output-Divider Pdiv2:
0 – down
1 – center
7
SSC1DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv2
—
01h
0b
Reserved – do not write others than 0
7-Bit Y3-Output-Divider Pdiv3:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv3
01h
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET(1)
18h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL1_0N [11:4
PLL1_0N [3:0]
PLL1_0R [8:5]
PLL1_0R[4:0]
PLL1_0Q [5:3]
PLL1_0Q [2:0]
PLL1_0P [2:0]
PLL1_0: 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information see PLL Multiplier/Divider Definition)
004h
19h
000h
1Ah
1Bh
10h
010b
fVCO1_0 range selection:
00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1:0
VCO1_0_RANGE
00b
1Ch
1Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL1_1N [11:4]
PLL1_1N [3:0]
PLL1_1R [8:5]
PLL1_1R[4:0]
PLL1_1Q [5:3]
PLL1_1Q [2:0]
PLL1_1P [2:0]
PLL1_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
1Eh
1Fh
10h
010b
fVCO1_1 range selection:
00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
1:0
VCO1_1_RANGE
00b
18
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 11. PLL2 Configuration Register
OFFSET(1)
Bit(2)
7:5
4:2
1:0
7
Acronym
SSC2_7 [2:0]
SSC2_6 [2:0]
SSC2_5 [2:1]
SSC2_5 [0]
SSC2_4 [2:0]
SSC2_3 [2:0]
SSC2_2 [2]
SSC2_2 [1:0]
SSC2_1 [2:0]
SSC2_0 [2:0]
FS2_7
Default(3)
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount)(4)
20h
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
21h
6:4
3:1
0
000b
000b
000b
22h
23h
7:6
5:3
2:0
7
000b
000b
0b
FS2_x: PLL2 Frequency Selection(4)
6
FS2_6
0b
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
24h
PLL2 Multiplexer:
0 – PLL2
7
6
MUX2
M4
1b
1b
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4 Multiplexer:
Output Y5 Multiplexer:
0 – Pdiv2
1 – Pdiv4
00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
5:4
M5
10b
3:2
1:0
Y4Y5_ST1
Y4Y5_ST0
11b
01b
Y4,
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
Y5-State0/1definition:
11 – Y4/Y5 enabled (normal operation, PLL2 on)
Y4Y5_x Output State Selection(4)
25h
7
6
5
4
3
2
1
0
Y4Y5_7
Y4Y5_6
Y4Y5_5
Y4Y5_4
Y4Y5_3
Y4Y5_2
Y4Y5_1
Y4Y5_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
26h
27h
PLL2 SSC down/center selection:
7-Bit Y4-Output-Divider Pdiv4:
0 – down
1 – center
7
SSC2DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv4
—
01h
0b
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv5
01h
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
19
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 11. PLL2 Configuration Register (continued)
OFFSET(1)
28h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL2_0N [11:4
PLL2_0N [3:0]
PLL2_0R [8:5]
PLL2_0R[4:0]
PLL2_0Q [5:3]
PLL2_0Q [2:0]
PLL2_0P [2:0]
PLL2_0: 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
29h
000h
2Ah
2Bh
10h
010b
fVCO2_0 range selection:
00 – fVCO2_0 < 125 MHz
01 – 125 MHz ≤ fVCO2_0 < 150 MHz
10 – 150 MHz ≤ fVCO2_0 < 175 MHz
11 – fVCO2_0 ≥ 175 MHz
1:0
VCO2_0_RANGE
00b
2Ch
2Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL2_1N [11:4]
PLL2_1N [3:0]
PLL2_1R [8:5]
PLL2_1R[4:0]
PLL2_1Q [5:3]
PLL2_1Q [2:0]
PLL2_1P [2:0]
PLL2_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
2Eh
2Fh
10h
010b
fVCO2_1 range selection:
00 – fVCO2_1 < 125 MHz
01 – 125 MHz ≤ fVCO2_1 < 150 MHz
10 – 150 MHz ≤ fVCO2_1 < 175 MHz
11 – fVCO2_1 ≥ 175 MHz
1:0
VCO2_1_RANGE
00b
20
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 12. PLL3 Configuration Register
OFFSET(1)
Bit(2)
7:5
4:2
1:0
7
Acronym
SSC3_7 [2:0]
SSC3_6 [2:0]
SSC3_5 [2:1]
SSC3_5 [0]
SSC3_4 [2:0]
SSC3_3 [2:0]
SSC3_2 [2]
SSC3_2 [1:0]
SSC3_1 [2:0]
SSC3_0 [2:0]
FS3_7
Default(3)
DESCRIPTION
SSC3: PLL3 SSC Selection (Modulation Amount)(4)
30h
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
31h
6:4
3:1
0
000b
000b
000b
32h
33h
7:6
5:3
2:0
7
000b
000b
0b
FS3_x: PLL3 Frequency Selection(4)
6
FS3_6
0b
0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
5
FS3_5
0b
4
FS3_4
0b
3
FS3_3
0b
2
FS3_2
0b
1
FS3_1
0b
0
FS3_0
0b
34h
PLL3 Multiplexer:
0 – PLL3
7
6
MUX3
M6
1b
1b
1 – PLL3 Bypass (PLL3 is in power down)
Output Y6 Multiplexer:
Output Y7 Multiplexer:
0 – Pdiv4
1 – Pdiv6
00 – Pdiv4-Divider
01 – Pdiv6-Divider
10 – Pdiv7-Divider
11 – reserved
5:4
M7
10b
3:2
1:0
Y6Y7_ST1
Y6Y7_ST0
11b
01b
Y6,
00 – Y6/Y7 disabled to 3-State (PLL3 is in power down)
01 – Y6/Y7 disabled to 3-State (PLL3 on)
10 –Y6/Y7 disabled to low (PLL3 on)
Y7-State0/1definition:
11 – Y6/Y7 enabled (normal operation, PLL3 on)
Y6Y7_x Output State Selection(4)
35h
7
6
5
4
3
2
1
0
Y6Y7_7
Y6Y7_6
Y6Y7_5
Y6Y7_4
Y6Y7_3
Y6Y7_2
Y6Y7_1
Y6Y7_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
36h
37h
PLL3 SSC down/center selection:
7-Bit Y6-Output-Divider Pdiv6:
0 – down
1 – center
7
SSC3DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv6
—
01h
0b
Reserved – do not write others than 0
7-Bit Y7-Output-Divider Pdiv7:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv7
01h
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
21
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 12. PLL3 Configuration Register (continued)
OFFSET(1)
38h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL3_0N [11:4
PLL3_0N [3:0]
PLL3_0R [8:5]
PLL3_0R[4:0]
PLL3_0Q [5:3]
PLL3_0Q [2:0]
PLL3_0P [2:0]
PLL3_0: 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
39h
000h
3Ah
3Bh
10h
010b
fVCO3_0 range selection:
00 – fVCO3_0 < 125 MHz
01 – 125 MHz ≤ fVCO3_0 < 150 MHz
10 – 150 MHz ≤ fVCO3_0 < 175 MHz
11 – fVCO3_0 ≥ 175 MHz
1:0
VCO3_0_RANGE
00b
3Ch
3Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL3_1N [11:4]
PLL3_1N [3:0]
PLL3_1R [8:5]
PLL3_1R[4:0]
PLL3_1Q [5:3]
PLL3_1Q [2:0]
PLL3_1P [2:0]
PLL3_1: 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
3Eh
3Fh
10h
010b
fVCO3_1 range selection:
00 – fVCO3_1 < 125 MHz
01 – 125 MHz ≤ fVCO3_1 < 150 MHz
10 – 150 MHz ≤ fVCO3_1 < 175 MHz
11 – fVCO3_1 ≥ 175 MHz
1:0
VCO3_1_RANGE
00b
22
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 13. PLL4 Configuration Register
OFFSET(1)
Bit(2)
7:5
4:2
1:0
7
Acronym
SSC4_7 [2:0]
SSC4_6 [2:0]
SSC4_5 [2:1]
SSC4_5 [0]
SSC4_4 [2:0]
SSC4_3 [2:0]
SSC4_2 [2]
SSC4_2 [1:0]
SSC4_1 [2:0]
SSC4_0 [2:0]
FS4_7
Default(3)
DESCRIPTION
SSC4: PLL4 SSC Selection (Modulation Amount)(4)
40h
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
41h
6:4
3:1
0
000b
000b
000b
42h
43h
7:6
5:3
2:0
7
000b
000b
0b
FS4_x: PLL4 Frequency Selection(4)
6
FS4_6
0b
0 – fVCO4_0 (predefined by PLL4_0 – Multiplier/Divider value)
1 – fVCO4_1 (predefined by PLL4_1 – Multiplier/Divider value)
5
FS4_5
0b
4
FS4_4
0b
3
FS4_3
0b
2
FS4_2
0b
1
FS4_1
0b
0
FS4_0
0b
44h
PLL4 Multiplexer:
0 – PLL4
7
6
MUX4
M8
1b
1b
1 – PLL4 Bypass (PLL4 is in power down)
Output Y8 Multiplexer:
Output Y9 Multiplexer:
0 – Pdiv6
1 – Pdiv8
00 – Pdiv6-Divider
01 – Pdiv8-Divider
10 – Pdiv9-Divider
11 – reserved
5:4
M9
10b
3:2
1:0
Y8Y9_ST1
Y8Y9_ST0
11b
01b
Y8,
00 – Y8/Y9 disabled to 3-State (PLL4 is in power down)
01 – Y8/Y9 disabled to 3-State (PLL4 on)
10 –Y8/Y9 disabled to low (PLL4 on)
Y9-State0/1definition:
11 – Y8/Y9 enabled (normal operation, PLL4 on)
Y8Y9_x Output State Selection(4)
45h
7
6
5
4
3
2
1
0
Y8Y9_7
Y8Y9_6
Y8Y9_5
Y8Y9_4
Y8Y9_3
Y8Y9_2
Y8Y9_1
Y8Y9_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y8Y9_ST0)
1 – state1 (predefined by Y8Y9_ST1)
46h
47h
PLL4 SSC down/center selection:
7-Bit Y8-Output-Divider Pdiv8:
0 – down
1 – center
7
SSC4DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv8
—
01h
0b
Reserved – do not write others than 0
7-Bit Y9-Output-Divider Pdiv9:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv9
01h
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
23
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CDCE949
CDCEL949
SCAS844–JUNE 2007
Table 13. PLL4 Configuration Register (continued)
OFFSET(1)
48h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL4_0N [11:4
PLL4_0N [3:0]
PLL4_0R [8:5]
PLL4_0R[4:0]
PLL4_0Q [5:3]
PLL4_0Q [2:0]
PLL4_0P [2:0]
PLL4_0: 30-Bit Multiplier/Divider value for frequency fVCO4_0
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
49h
000h
4Ah
4Bh
10h
010b
fVCO4_0 range selection:
00 – fVCO4_0 < 125 MHz
01 – 125 MHz ≤ fVCO4_0 < 150 MHz
10 – 150 MHz ≤ fVCO4_0 < 175 MHz
11 – fVCO4_0 ≥ 175 MHz
1:0
VCO4_0_RANGE
00b
4Ch
4Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL4_1N [11:4]
PLL4_1N [3:0]
PLL4_1R [8:5]
PLL4_1R[4:0]
PLL4_1Q [5:3]
PLL4_1Q [2:0]
PLL4_1P [2:0]
PLL4_1: 30-Bit Multiplier/Divider value for frequency fVCO4_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
4Eh
4Fh
10h
010b
fVCO4_1 range selection:
00 – fVCO4_1 < 125 MHz
01 – 125 MHz ≤ fVCO4_1 < 150 MHz
10 – 150 MHz ≤ fVCO4_1 < 175 MHz
11 – fVCO4_1 ≥ 175 MHz
1:0
VCO4_1_RANGE
00b
24
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CDCE949
CDCEL949
SCAS844–JUNE 2007
PLL MULTIPLIER/DIVIDER DEFINITION
At a given input frequency (fIN), the output frequency (fOUT) of the CDCE949/CDCEL949 can be calculated by:
ƒ
IN
N
M
ƒ
+
OUT
Pdiv
where
M (1 to 511) and N (1 to 4095) are the multiplier/divider values of the PLL;
Pdiv (1 to 127) is the output divider.
The target VCO frequency (fVCO) of each PLL can be calculated:
N
M
ƒ
+ ƒ
VCO
IN
The PLL operates as fractional divider and needs following multiplier/divider settings
N
N
P = 4 - int(log2
)
M
{if P < 0 then P = 0}
N'
Q = int(
)
M
R = N'-M´ Q
Where:
N’ = N × 2P;
N ≥ M;
80 MHz < fVCO > 230 MHz.
Example 1: for fIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
→ fOUT = 54 MHz;
Example 2: for fIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 75.25 MHz;
→ fVCO = 108 MHz;
→ fVCO = 148.50 MHz;
→ P = 4 – int(log24) = 4 –2 = 2;
→ N’ = 4 × 22 = 16;
→ P = 4 – int(log25.5) = 4 – 2 = 2;
→ N’ = 11 × 22 = 44;
→ Q = int(16) = 16;
→ Q = int(22) = 22;
→ R = 16 – 16 = 0;
→ R = 44 – 44 = 0;
The values for P, Q, R and N’ are automatically calculated when using TI Pro Clock™ Software.
25
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CDCE949
CDCEL949
SCAS844–JUNE 2007
HISTORY
Data sheet
Revision
Modified by
Date
Modified Content
0.10
Georg Becke
Georg Becke
Georg Becke
Georg Becke
18, May 2006
26, May 2006
31, May 2006
9, Jun 2006
Created initial Specification;
0.11
Added updates according the Spec’ Review Meeting held 5/19/2006;
Version for Plan-DPR;
0.20
0.21
Updated SDA/SCL 2-wire interface specification; block-diagrams, pin-assignments
register configuration bitmap; control terminal pin descriptions;
0.22
Georg Becke
20, Jul 2006
Updated control register setting; change pull-up value of S0, S1, S2 to 500Kohm to be
conform with I2C spec’; updated Register Configuration Bitmap; added default device
configuration;
0.25
0.26
0.27
Georg Becke
Georg Becke
Georg Becke
24, Jul 2006
28, Jul 2006
15, Sep 2006
Created CDCE949 datasheet from CDCE9xx version 0.22;
Added SDA/SCL Configuration Register definition and bit assignment;
Added low/high-speed VCO mode to configuration register (2-bit = 4 options); added
CDCEL949; modified Configuration Register; updated address bits and PLL dividers in
conf reg.; added 50 Ohm termination load;
0.28
0.29
0.30
Georg Becke
Georg Becke
Georg Becke
25, Oct 2006
21, Nov 2006
8, Dec 2006
Add 1.8V outputs to head-line; updated Iil for S0/1/2 to -4uA; modified configuration
registers and changed “acronym” to be more readable; re-arranged bits/bytes in
generic configuration register; added PLL frequency calculation; described that
EELOCK and SPICON is valid only if written into the EEPROM; changed block
diagrams to show “EEPROM-Block”;
Added 500K pull-up to SDA/SCL input; added div-by-0 (=reset) to post-dividers
function; corrected calculation of “R” for 30-bit PLL divider; corrected default setting for
Yn on page 12; change order of freq-select and SSC-select in the tables (ETC
request) → no change in Control registers; add 1 bit for E vs EL identification; made
some word adjustment to some text sections;
Added “not write beyond 50h” (note 1); added CL description (note 8); change note 9
– EEWRITE; modified Yx default setting; added Vdd pin 13 to Terminal Functions;
added “not overwrite” to reserved bits; changed acronyms for Yx_STy;
0.31
0.32
Georg Becke
Georg Becke
19, Dec 2006
15. Feb 2007
Updated first three pages; forwarded version 0.31 to TIS;
General Update at feature block, terminal function, Vi, X-tal-Spec, SDA-Hold-time,
Ctrl-terminal Register, bit-map description (generic, PLL1, PLL2, PLL3, PLL4), load
cap drawing and relevant note, PLL frequency calculation
0.33
0.4
Georg Becke
Georg Becke
11. Apr 2007
11. May 2007
Added "Block Read" comment; changed slave adr bits;
Char&ATE Review
26
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2007
PACKAGING INFORMATION
Orderable Device
CDCE949PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCE949PWG4
CDCE949PWR
CDCE949PWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
CDCE949PWR
PW
24
MLA
330
16
6.95
8.3
1.6
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
MLA
Length (mm) Width (mm) Height (mm)
CDCE949PWR
PW
24
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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相关型号：
CDCE949QPWRQ1
PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS
TI
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