CDCEL925PWRG4 [TI]
PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS; 采用1.8 V, 2.5 V和3.3 V LVCMOS输出的可编程2 -PLL VCXO时钟合成器型号: | CDCEL925PWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS |
文件: | 总27页 (文件大小:484K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CDCE925
CDCEL925
www.ti.com
SCAS847F –JULY 2007–REVISED MARCH 2010
PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V
LVCMOS OUTPUTS
Check for Samples: CDCE925, CDCEL925
1
FEATURES
•
Flexible Input Clocking Concept
234
•
Member of Programmable Clock Generator
Family
–
–
–
External Crystal: 8 MHz to 32 MHz
On-Chip VCXO: Pull Range ±150 ppm
Single-Ended LVCMOS up to 160 MHz
–
–
–
–
CDCE913/CDCEL913: 1-PLL, 3 Outputs
CDCE925/CDCEL925: 2-PLL, 5 Outputs
CDCE937/CDCEL937: 3-PLL, 7 Outputs
CDCE949/CDCEL949: 4-PLL, 9 Outputs
•
•
Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
–
–
PLL Loop Filter Components Integrated
Low Period Jitter (Typ 60 ps)
•
Flexible Clock Driver
–
Three User-Definable Control Inputs
[S0/S1/S2] e.g., SSC Selection, Frequency
Switching, Output Enable or Power Down
•
•
1.8-V Device Power Supply
Separate Output Supply Pins
–
–
CDCE925: 3.3 V and 2.5 V
CDCEL925: 1.8 V
–
–
–
Programmable SSC Modulation
Enables 0-PPM Clock Generation
•
•
•
Temperature Range –40°C to 85°C
Packaged in TSSOP
Generates Common Clock Frequencies
Used With Texas Instruments DaVinci™,
OMAP™, DSPs
Development and Programming Kit for Easy
PLL Design and Programming (TI Pro-Clock™)
–
Generates Highly Accurate Clocks for
Video, Audio, USB, IEEE1394, RFID,
Bluetooth™, WLAN, Ethernet™, and GPS
APPLICATIONS
•
D-TV, STB, IP-STB, DVD-Player, DVD-Recorder,
Printer
•
In-System Programmability and EEPROM
–
–
Serial Programmable Volatile Register
Nonvolatile EEPROM to Store Customer
Setting
V
V
DDOUT
DD
GND
Vctr
LV
CMOS
Y1
VCXO
XO
Xin/Clk 1
S0 2
16 Xout
15 S1/SDA
14 S2/SCL
13 Y1
LV
CMOS
LVCMOS
Y2
Y3
Y4
Y5
PLL1
Vdd 3
Vctr 4
GND 5
Vddout 6
Y4 7
Divider
and
Output
Control
EEPROM
With SSC
3
LV
CMOS
Programming
and
Control Register
S2/S1/S0 or
SDA/SCL
12 GND
11 Y2
10 Y3
LV
CMOS
PLL2
Y5 8
9 Vddout
With SSC
LV
CMOS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG.
Ethernet is a trademark of Xerox Corporattion.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
CDCE925
CDCEL925
SCAS847F –JULY 2007–REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock
synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent
configurable PLLs.
The CDCx925 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for
CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth,
Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from a 27 MHz reference input frequency, for
example.
All PLLs supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is
a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be re-programmed to a different application configuration
before it goes onto the PCB or re-programmed by in-system programming. All device settings are programmable
through SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change
SSC setting for lowering EMI, or other control features like outputs disable to low, outputs 3-state, power down,
PLL bypass, etc.).
The CDCx925 operates in a 1.8 V environment. It operates in a temperature range of –40 °C to 85 °C.
Terminal Functions for CDCE925, CDCEL925
TERMINAL
I/O
DESCRIPTION
NAME
Y1, Y2, ... Y5
Xin/CLK
Xout
NO.
7, 8, 10, 11, 13
O
LVCMOS outputs
1
16
4
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)
Crystal oscillator output (leave open or pullup when not used)
VCXO control voltage (leave open or pullup when not used)
1.8-V power supply for the device
O
I
VCtrl
VDD
3
Power
CDCEL925: 1.8-V supply for all outputs
VDDOUT
6, 9
Power
CDCE925: 3.3-V or 2.5-V supply for all outputs
GND
S0
5, 12
2
Ground Ground
User-programmable control input S0; LVCMOS inputs; internal pullup
SDA: bidirectional serial data input/output (default configuration), LVCMOS; internal
I/O or I pullup; or
S1: user-programmable control input; LVCMOS inputs; internal pullup
I
SDA/S1
SCL/S2
15
14
SCL: serial clock input (default configuration), LVCMOS; internal pullup or
S2: user-programmable control input; LVCMOS inputs; internal pullup
I
2
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Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
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SCAS847F –JULY 2007–REVISED MARCH 2010
FUNCTIONAL BLOCK DIAGRAM for CDCE925, CDCEL925
V
V
GND
DDOUT
DD
Input Clock
Vctr
LV
CMOS
Pdiv1
10-Bit
Y1
Xin/CLK
VCXO
XO
LV
CMOS
Pdiv2
7-Bit
Y2
Y3
PLL 1
LVCMOS
With SSC
Xout
LV
CMOS
Pdiv3
7-Bit
PLL Bypass
EEPROM
Programming
and
SDA/SCL
Register
S0
S1/SDA
S2/SCL
LV
CMOS
Pdiv4
7-Bit
Y4
Y5
PLL 2
With SSC
LV
CMOS
Pdiv5
7-Bit
PLL Bypass
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.5 to 2.5
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
20
UNIT
V
VDD
VI
Supply voltage range
Input voltage range(2) (3)
Output voltage range(2)
Input current (VI < 0, VI > VDD
Continuous output current
Storage temperature range
V
VO
II
V
)
mA
mA
°C
°C
IO
50
Tstg
TJ
–65 to 150
125
Maximum junction temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
(3) SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.
PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE(1)
over operating free-air temperature range (unless otherwise noted)
AIRFLOW
(lfm)
TSSOP16
°C/W
PARAMETER
0
101
85
84
82
74
42
64
1.0
58
150
200
250
500
—
TJA
Thermal Resistance Junction to Ambient
TJC
Thermal Resistance Junction to Case
Thermal Resistance Junction to Board
Thermal Resistance Junction to Top
Thermal Resistance Junction to Bottom
TJB
—
RqJT
RqJB
—
—
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
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CDCEL925
SCAS847F –JULY 2007–REVISED MARCH 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
1.7
2.3
1.7
NOM
MAX
1.9
UNIT
VDD
Device supply voltage
1.8
V
Output Yx supply voltage for CDCE925
Output Yx supply voltage for CDCEL925
Low-level input voltage LVCMOS
High-level input voltage LVCMOS
Input voltage threshold LVCMOS
Input voltage range S0
3.6
VDDOUT
1.9
V
V
V
V
VIL
0.3 VDD
VIH
0.7 VDD
VI(thresh)
0.5 VDD
0
0
0
1.9
3.6
1.9
±12
±10
±8
VI(S)
V
V
Input voltage range S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD
Input voltage range CLK
VI(CLK)
Output current (VDDOUT = 3.3 V)
Output current (VDDOUT = 2.5 V)
Output current (VDDOUT = 1.8 V)
Output load LVCMOS
IOH /IOL
mA
CL
TA
15
pF
°C
Operating free-air temperature
–40
85
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1)
MIN
NOM
MAX
32
UNIT
MHz
Ω
fXtal
Crystal input frequency range (fundamental mode)
Effective series resistance
Pulling range (0 V ≤ VCtrl ≤ 1.8 V)(2)
8
27
ESR
fPR
100
±120
0
±150
ppm
V
VCtrl
C0/C1
CL
Frequency control voltage
VDD
220
20
Pullability ratio
On-chip load capacitance at Xin and Xout
0
pF
(1) For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
(2) Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report (SCAA085).
EEPROM SPECIFICATION
MIN
100
10
TYP
MAX
UNIT
cycles
years
EEcyc
EEret
Programming cycles of EEPROM
Data retention
1000
4
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
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SCAS847F –JULY 2007–REVISED MARCH 2010
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
UNIT
CLK_IN REQUIREMENTS
PLL bypass mode
0
8
160
160
3
fCLK
LVCMOS clock input frequency
MHz
ns
PLL mode
tr / tf
Rise and fall time CLK signal (20% to 80%)
Duty cycle CLK at VDD / 2
dutyCLK
40%
60%
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN MAX
SDA/SCL TIMING REQUIREMENTS (see Figure 12)
fSCL
SCL clock frequency
0
4.7
4
100
0
0.6
0.6
1.3
0.6
0
400
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
tsu(START)
th(START)
tw(SCLL)
tw(SCLH)
th(SDA)
tsu(SDA)
tr
START setup time (SCL high before SDA low)
START hold time (SCL low after SDA low)
SCL low-pulse duration
4.7
4
SCL high-pulse duration
SDA hold time (SDA valid after SCL low)
SDA setup time
0
3.45
0.9
250
100
SCL/SDA input rise time
1000
300
300
300
tf
SCL/SDA input fall time
tsu(STOP)
tBUS
STOP setup time
4
0.6
1.3
Bus free time between a STOP and START condition
4.7
Copyright © 2007–2010, Texas Instruments Incorporated
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CDCEL925
SCAS847F –JULY 2007–REVISED MARCH 2010
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DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
OVERALL PARAMETER
All outputs off, fCLK=27 MHz,
fVCO = 135 MHz; fOUT = 27
MHz
All PLLS on
Per PLL
20
9
IDD
Supply current (see Figure 3)
mA
mA
CDCE925 VDDOUT = 3.3 V
CDCEL925 VDDOUT = 1.8 V
2
1
No load, all outputs on,
fOUT = 27 MHz
IDDOUT
Supply current (see Figure 4 and Figure 5)
Power-down current. Every circuit powered
down except SDA/SCL
IDDPD
VPUC
fIN = 0 MHz,
VDD = 1.9 V
30
mA
Supply voltage VDD threshold for power-up
control circuit
0.85
1.45
230
V
fVCO
fOUT
VCO frequency range of PLL
LVCMOS output frequency
80
MHz
MHz
CDCE(L)925 VDDOUT = 1.8 V
230
LVCMOS PARAMETER
VIK
II
LVCMOS input voltage
VDD = 1.7 V; Is = –18 mA
VI = 0 V or VDD; VDD = 1.9 V
VI = VDD; VDD = 1.9 V
VI = 0 V; VDD = 1.9 V
VIClk = 0 V or VDD
–1.2
±5
5
V
LVCMOS Input current
mA
mA
mA
IIH
IIL
LVCMOS Input current for S0/S1/S2
LVCMOS Input current for S0/S1/S2
Input capacitance at Xin/Clk
Input capacitance at Xout
–4
6
2
3
CI
VIXout = 0 V or VDD
pF
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
CDCE925 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VDDOUT = 3 V, IOH = –0.1 mA
2.9
2.4
2.2
VOH
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 3 V, IOH = –8 mA
VDDOUT = 3 V, IOH = –12 mA
VDDOUT = 3 V, IOL = 0.1 mA
VDDOUT = 3 V, IOL = 8 mA
VDDOUT = 3 V, IOL = 12 mA
All PLL bypass
V
V
0.1
0.5
0.8
VOL
tPLH, tPHL Propagation delay
3.2
0.6
50
ns
ns
tr/tf
Rise and fall time
VDDOUT = 3.3 V (20%–80%)
1 PLL switching, Y2-to-Y3
2 PLL switching, Y2-to-Y5
1 PLL switching, Y2-to-Y3
2 PLL switching, Y2-to-Y5
fOUT = 50 MHz; Y1-to-Y3
fOUT = 50 MHz; Y2-to-Y5
fVCO = 100 MHz; Pdiv = 1
70
130
100
160
70
(3)
tjit(cc)
Cycle-to-cycle jitter(2)
ps
ps
ps
90
60
tjit(per)
Peak-to-peak period jitter(3)
100
(4)
tsk(o)
odc
Output skew
150
55%
(5)
Output duty cycle
45%
CDCE925 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
1.7
1.6
VOH
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 2.3 V, IOH = –6 mA
VDDOUT = 2.3 V, IOH = –10 mA
VDDOUT = 2.3 V, IOL = 0.1 mA
VDDOUT = 2.3 V, IOL = 6 mA
VDDOUT = 2.3 V, IOL = 10 mA
All PLL bypass
V
V
0.1
0.5
0.7
VOL
tPLH, tPHL Propagation delay
tr/tf Rise and fall time
3.6
0.8
ns
ns
VDDOUT = 2.5 V (20%–80%)
(1) All typical values are at respective nominal VDD
.
(2) 10000 cycles.
(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
(5) odc depends on output rise- and fall time (tr/tf);
6
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Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
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SCAS847F –JULY 2007–REVISED MARCH 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
70
UNIT
1 PLL switching, Y2-to-Y3
50
90
(6) (7)
tjit(cc)
Cycle-to-cycle jitter
ps
2 PLL switching, Y2-to-Y5
1 PLL switching, Y2-to-Y3
2 PLL switching, Y2-to-Y5
fOUT = 50 MHz; Y1-to-Y3
fOUT = 50 MHz; Y2-to-Y5
fVCO = 100 MHz; Pdiv = 1
130
100
160
70
60
(7)
tjit(per)
Peak-to-peak period jitter
ps
ps
100
(8)
tsk(o)
odc
Output skew
150
(9)
Output duty cycle
45%
55%
CDCEL925 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
1.4
1.1
VOH
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –4 mA
VDDOUT = 1.7 V, IOH = –8 mA
VDDOUT = 1.7 V, IOL = 0.1 mA
VDDOUT = 1.7 V, IOL = 4 mA
VDDOUT = 1.7 V, IOL = 8 mA
All PLL bypass
V
V
0.1
0.3
0.6
VOL
tPLH, tPHL Propagation delay
2.6
0.7
ns
ns
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
1 PLL switching, Y2-to-Y3
2 PLL switching, Y2-to-Y5
1 PLL switching, Y2-to-Y3
2 PLL switching, Y2-to-Y5
fOUT = 50 MHz; Y1-to-Y3
fOUT = 50 MHz; Y2-to-Y5
fVCO = 100 MHz; Pdiv = 1
80
110
200
130
220
50
(6) (7)
tjit(cc)
Cycle-to-cycle jitter
ps
ps
ps
130
100
150
(10)
tjit(per)
Peak-to-peak period jitter
(11)
tsk(o)
odc
Output skew
110
55%
(12)
Output duty cycle
45%
SDA/SCL PARAMETER
VIK
IIH
SCL and SDA input clamp voltage
SCL and SDA input current
SDA/SCL input high voltage(13)
SDA/SCL input low voltage(13)
SDA low-level output voltage
SCL/SDA Input capacitance
VDD = 1.7 V; II = –18 mA
VI = VDD; VDD = 1.9 V
–1.2
±10
V
mA
V
VIH
VIL
VOL
CI
0.7 VDD
0.3 VDD
0.2 VDD
10
V
IOL = 3 mA VDD = 1.7 V
VI = 0 V or VDD
V
3
pF
(6) 10000 cycles.
(7) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
(8) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
(9) odc depends on output rise- and fall time (tr/tf);
(10) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
(11) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
(12) odc depends on output rise- and fall time (tr/tf);
(13) SDA and SCL pins are 3.3 V tolerant.
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PARAMETER MEASUREMENT INFORMATION
CDCE925
CDEL925
1 kW
1 kW
LVCMOS
10 pF
Figure 1. Test Load
CDCE925
CDCEL925
LVCMOS
LVCMOS
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
Typical Driver
Impedance
~ 32 W
Figure 2. Test Load for 50-Ω Board Environment
8
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SCAS847F –JULY 2007–REVISED MARCH 2010
TYPICAL CHARACTERISTICS
CDCE925 AND CDCEL925 SUPPLY CURRENT
CDCE925 OUTPUT CURRENT
vs
vs
PLL FREQUENCY
OUTPUT FREQUENCY
25
20
60
50
V
V
= 1.8 V,
= 3.3 V,
DD
V
= 1.8 V
DD
DDOUT
No Load
5 outputs on
3 outputs on
40
30
20
15
10
2 PLL on
1 output on
all outputs off
1 PLL on
5
0
10
0
all PLL off
10 30 50 70 90 110 130 150 170 190 210 230
10
60
110 160
f - Frequency - MHz
210
f
- Output Frequency - MHz
OUT
Figure 3.
Figure 4.
CDCEL925 OUTPUT CURRENT
vs
OUTPUT FREQUENCY
8
V
= 1.8 V,
DD
V
= 1.8 V,
7
6
DDOUT
No Load
5 outputs on
3 outputs on
5
4
3
1 output on
all outputs off
2
1
0
10 30 50 70 90 110 130 150 170 190 210 230
f
- Output Frequency - MHz
OUT
Figure 5.
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SCAS847F –JULY 2007–REVISED MARCH 2010
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APPLICATION INFORMATION
CONTROL TERMINAL SETTING
The CDCE925/CDCEL925 has three user-definable control terminals (S0, S1, and S2) which allow external
control of device settings. They can be programmed to any of the following setting:
•
•
•
Spread spectrum clocking selection → spread type and spread amount selection
Frequency selection → switching between any of two user-defined frequencies
Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
External
Control Bits
PLL1 Setting
PLL2 Setting
Y1 Setting
Control
Function
PLL Frequency
Selection
SSC
Selection
Output Y2/Y3 PLL Frequency
Selection Selection
SSC
Selection
Output Y4/Y5
Selection
Output Y1 and
Power-Down Selection
Table 2. PLL Setting (Can Be Selected for Each PLL Individual)(1)
SSC SELECTION (CENTER/DOWN)
SSCx [3-Bits]
Center
0% (off)
±0.25%
±0.5%
Down
0% (off)
–0.25%
–0.5%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
±0.75%
±1.0%
–0.75%
–1.0%
±1.25%
±1.5%
–1.25%
–1.5%
±2.0%
–2.0%
FREQUENCY SELECTION(2)
FSx
0
FUNCTION
Frequency0
Frequency1
1
OUTPUT SELECTION(3) (Y2 ... Y5)
YxYx
FUNCTION
0
1
State0
State1
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Table 3. Y1 Setting(1)
Y1 SELECTION
Y1
0
FUNCTION
State 0
1
State 1
(1) State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
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SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In default configuration, they are
predefined as SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by
setting the relevant bits in the EEPROM. Note that the changes of the bits in the Control Register (bit [6] of byte
02h) have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi use pin; it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE925/CDCEL925 is preconfigured as shown in Figure 6 The input frequency is
passed through the output as a default. This allows the device to operate in default mode without the extra
production step of programming it. The default setting appears after power is supplied or after power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL interface.
V
V
DDOUT
DD
GND
Input Clock
LV
CMOS
Pdiv1 =1
Y1 = 27MHz
Xin
27-MHz
Crystal
Xtal
LV
CMOS
Y2 = 27 MHz
Y3 = 27 MHz
PLL1
Power Down
Pdiv2 = 1
Xout
S0
LV
CMOS
Pdiv3 = 1
PLL Bypass
EEPROM
“1” = Outputs Enabled
“0” = Outputs
-State
Programming Bus
Programming
and
SDA/SCL
Register
3
SDA
SCL
LV
CMOS
Y4 = 27 MHz
Y5 = 27 MHz
PLL2
Pdiv4 = 1
Pdiv5 = 1
Power Down
LV
CMOS
PLL Bypass
Figure 6. Preconfiguration of CDCE925/CDCEL925 Internal EEPROM
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). Note that even
though eight different register settings are possible, in default configuration, only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 are configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register(1)
Y1
PLL1 Settings
PLL2 Settings
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
External Control Pins
S2
S1
S0
0
Y1
FS1
SSC1
off
Y2Y3
3-state
enabled
FS2
SSC2
off
Y4Y5
3-state
enabled
SCL (I2C)
SCL (I2C)
SDA (I2C)
SDA (I2C)
3-state
enabled
fVCO1_0
fVCO1_0
fVCO2_0
fVCO2_0
1
off
off
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
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SDA/SCL SERIAL INTERFACE
This section describes the SDA/SCL interface of the CDCE925/CDCEL925 device. The CDCE925/CDCEL925
operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C
specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s)
and supports 7-bit addressing.
The SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In the default configuration
they are used as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control
pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].
DATA PROTOCOL
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
bytes read out are defined by byte count in the Generic Configuration Register. At Block Read instruction all
bytes defined in the byte count has to be read out to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write
Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read
out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
DEVICE
A6
1
A5
1
A4
0
A3
0
A2
1
A1(1)
A0(1)
R/W
1/0
1/0
1/0
1/0
CDCE913/CDCEL913
CDCE925/CDCEL925
CDCE937/CDCEL937
CDCE949/CDCEL949
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
(1) Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices connected
to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
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COMMAND CODE DEFINITION
Table 6. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0)
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
7
1
1
8
1
1
S
Slave Address
A
Data Byte
A
P
R/W
MSB
LSB
MSB
LSB
S
Start Condition
Sr Repeated Start Condition
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
Acknowledge (ACK = 0 and NACK =1)
Stop Condition
R/W
A
P
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 7. Generic Programming Sequence
Byte Write Programming Sequence
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
CommandCode
A
Data Byte
A
P
Figure 8. Byte Write Protocol
Byte Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
S
Slave Address
Rd
A
8
1
1
Data Byte
A
P
Figure 9. Byte Read Protocol
Block Write Programming Sequence
1
7
1
1
8
1
8
1
S
Slave Address
Wr
A
CommandCode
A
Byte Count = N
A
8
1
8
1
8
1
1
Data Byte 0
A
Data Byte 1
A
…
Data Byte N-1
A
P
(1) Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 10. Block Write Protocol
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Block Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
Sr
Slave Address
Rd
A
8
1
8
1
8
1
1
Byte Count N
A
Data Byte 0
A
…
Data Byte N-1
A
P
Figure 11. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
Bit 7 (MSB)
Bit 6
Bit 0 (LSB)
P
S
A
P
t
w(SCLL)
t
w(SCLH)
t
r
t
f
V
IH
SCL
V
IL
t
t
t
su(START)
h(START)
su(SDA)
t
t
h(SDA)
su(STOP)
t
f
t
t
r
(BUS)
V
IH
SDA
V
IL
Figure 12. Timing Diagram for SDA/SCL Serial Control Interface
SDA/SCL HARDWARE INTERFACE
Figure 13 shows how the CDCE925/CDCEL925 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the
maximum) if many devices are connected.
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax
=
0.4 V for the output stages (for more details see SMBus or I2C Bus specification).
CDCE925
CDCEL925
R
R
P
P
Master
SDA
Slave
SCL
C
C
BUS
BUS
Figure 13. SDA / SCL Hardware Interface
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SDA/SCL CONFIGURATION REGISTERS
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE925/CDCEL925. All settings can be manually
written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI
Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for
optimized performance at lowest jitter.
Table 7. SDA/SCL Registers
Address Offset
Register Description
Generic Configuration Register
PLL1 Configuration Register
PLL2 Configuration Register
Table
00h
10h
20h
Table 9
Table 10
Table 11
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2. Table 8 explains the corresponding bit assignment
between the Control Terminal Register and the Configuration Registers.
Table 8. Configuration Register, External Control Terminals
Y1
PLL1 Settings
PLL2 Settings
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
External Control Pins
S2
0
S1
0
S0
0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
0
1
2
3
4
5
6
7
Y1_0
Y1_1
Y1_2
Y1_3
Y1_4
Y1_5
Y1_6
Y1_7
04h
FS1_0
FS1_1
FS1_2
FS1_3
FS1_4
FS1_5
FS1_6
FS1_7
13h
SSC1_0
SSC1_1
SSC1_2
SSC1_3
SSC1_4
SSC1_5
SSC1_6
SSC1_7
10h–12h
Y2Y3_0
Y2Y3_1
Y2Y3_2
Y2Y3_3
Y2Y3_4
Y2Y3_5
Y2Y3_6
Y2Y3_7
15h
FS2_0
FS2_1
FS2_2
FS2_3
FS2_4
FS2_5
FS2_6
FS2_7
23h
SSC2_0
SSC2_1
SSC2_2
SSC2_3
SSC2_4
SSC2_5
SSC2_6
SSC2_7
20h–22h
Y4Y5_0
Y4Y5_1
Y4Y5_2
Y4Y5_3
Y4Y5_4
Y4Y5_5
Y4Y5_6
Y4Y5_7
25h
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Address Offset(1)
(1) Address Offset refers to the byte address in the Configuration Register in Table 9, Table 10, and Table 11.
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Table 9. Generic Configuration Register
Offset(1)
00h
Bit(2)
7
Acronym
E_EL
RID
Default(3)
Description
Device identification (read-only): 1 is CDCE925 (3.3 V out), 0 is CDCEL925 (1.8 V out)
Revision Identification Number (read only)
Xb
Xb
1h
0b
6:4
3:0
7
VID
Vendor Identification Number (read only)
01h
–
Reserved – always write 0
EEPROM Programming Status4:(4) (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
6
5
EEPIP
0b
0b
Permanently Lock EEPROM Data(5)
0 – EEPROM is not locked
1 – EEPROM will be permanently locked
EELOCK
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
4
PWDN
0b
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-state)
3:2
1:0
7
INCLK
SLAVE_ADR
M1
00b
00b
1b
Input clock selection:
00 – Xtal 01 – VCXO
10 – LVCMOS 11 – reserved
Address Bits A0 and A1 of the Slave Receiver Address
Clock source selection for output Y1:
0 – input clock
1 – PLL1 clock
Operation mode selection for pin 14/15(6)
6
SPICON
0b
0 – serial programming interface SDA (pin 15) and SCL (pin 14)
1 – control pins S1 (pin 15) and S2 (pin 14)
02h
5:4
3:2
Y1_ST1
Y1_ST0
11b
01b
Y1-State0/1 Definition
00 – device power down (all PLLs in power down and all
outputs in 3-State)
10 – Y1 disabled to low
11 – Y1 enabled
01 – Y1 disabled to 3-state
1:0
7:0
7
Pdiv1 [9:8]
Pdiv1 [7:0]
Y1_7
10-Bit Y1-Output-Divider Pdiv1:
0 – divider reset and stand-by
1-to-1023 – divider value
001h
03h
04h
0b
0b
0b
0b
0b
0b
0b
0b
Y1_ST0/Y1_ST1 State Selection(7)
6
Y1_6
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
5
Y1_6
4
Y1_6
3
Y1_6
2
Y1_6
1
Y1_6
0
Y1_6
Vctr
Xin
05h
06h
Crystal Load Capacitor Selection(8)
Reserved – do not write other than 0
00h → 0 pF
01h → 1 pF
02h → 2 pF
:
VCXO
XO
20pF
20pF
i.e.
XCSEL = 10pF
7:3
XCSEL
0Ah
14h-to-1Fh → 20 pF
Xout
2:0
7:1
0b
7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes
have to be read out to correctly finish the read cycle.)
BCOUNT
EEWRITE
30h
0– no EEPROM write cycle
Initiate EEPROM Write Cycle(9)
0
0b
1 – start EEPROM write cycle (internal register are saved to the EEPROM)
(1) Writing data beyond ‘30h’ may affect device function.
(2) All data transferred with the MSB first.
(3) Unless customer-specific setting.
(4) During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no
longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.
(6) Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.
(7) These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then
can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20
pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which
always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see
application report SCAA085.
(9) Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
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Table 9. Generic Configuration Register (continued)
Offset(1)
Bit(2)
Acronym
Default(3)
Description
07h-0Fh
—
0h
Reserved – do not write other than 0
Table 10. PLL1 Configuration Register
OFFSET(1)
Bit(2)
Acronym
Default(3)
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount)(4)
10h
7:5
4:2
1:0
7
SSC1_7 [2:0]
SSC1_6 [2:0]
SSC1_5 [2:1]
SSC1_5 [0]
SSC1_4 [2:0]
SSC1_3 [2:0]
SSC1_2 [2]
SSC1_2 [1:0]
SSC1_1 [2:0]
SSC1_0 [2:0]
FS1_7
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
11h
6:4
3:1
0
000b
000b
000b
12h
13h
7:6
5:3
2:0
7
000b
000b
0b
FS1_x: PLL1 Frequency Selection(4)
6
FS1_6
0b
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
14h
PLL1 Multiplexer:
0 – PLL1
7
6
MUX1
M2
1b
1b
1 – PLL1 Bypass (PLL1 is in power down)
Output Y2 Multiplexer:
Output Y3 Multiplexer:
0 – Pdiv1
1 – Pdiv2
00 – Pdiv1-Divider
01 – Pdiv2-Divider
10 – Pdiv3-Divider
11 – reserved
5:4
M3
10b
3:2
1:0
Y2Y3_ST1
Y2Y3_ST0
11b
01b
Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
11 – Y2/Y3 enabled (normal operation, PLL1 on)
Y2Y3_x Output State Selection(4)
15h
7
6
5
4
3
2
1
0
Y2Y3_7
Y2Y3_6
Y2Y3_5
Y2Y3_4
Y2Y3_3
Y2Y3_2
Y2Y3_1
Y2Y3_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
16h
17h
PLL1 SSC down/center selection:
7-Bit Y2-Output-Divider Pdiv2:
0 – down
1 – center
7
SSC1DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv2
—
01h
0b
Reserved – do not write others than 0
7-Bit Y3-Output-Divider Pdiv3:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv3
01h
(1) Writing data beyond 30h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET(1)
18h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL1_0N [11:4
PLL1_0N [3:0]
PLL1_0R [8:5]
PLL1_0R[4:0]
PLL1_0Q [5:3]
PLL1_0Q [2:0]
PLL1_0P [2:0]
PLL1_0(5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see paragraph PLL Multiplier/Divider Definition).
004h
19h
000h
1Ah
1Bh
10h
010b
fVCO1_0 range selection:
00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1:0
VCO1_0_RANGE
00b
1Ch
1Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL1_1N [11:4]
PLL1_1N [3:0]
PLL1_1R [8:5]
PLL1_1R[4:0]
PLL1_1Q [5:3]
PLL1_1Q [2:0]
PLL1_1P [2:0]
PLL1_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
1Eh
1Fh
10h
010b
fVCO1_1 range selection:
00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
1:0
VCO1_1_RANGE
00b
(5) PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096
18
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SCAS847F –JULY 2007–REVISED MARCH 2010
Table 11. PLL2 Configuration Register
OFFSET(1)
Bit(2)
7:5
4:2
1:0
7
Acronym
SSC2_7 [2:0]
SSC2_6 [2:0]
SSC2_5 [2:1]
SSC2_5 [0]
SSC2_4 [2:0]
SSC2_3 [2:0]
SSC2_2 [2]
SSC2_2 [1:0]
SSC2_1 [2:0]
SSC2_0 [2:0]
FS2_7
Default(3)
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount)(4)
20h
000b
000b
Down
Center
000 (off)
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
000b
21h
6:4
3:1
0
000b
000b
000b
22h
23h
7:6
5:3
2:0
7
000b
000b
0b
FS2_x: PLL2 Frequency Selection(4)
6
FS2_6
0b
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
24h
PLL2 Multiplexer:
0 – PLL2
7
6
MUX2
M4
1b
1b
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4 Multiplexer:
Output Y5 Multiplexer:
0 – Pdiv2
1 – Pdiv4
00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
5:4
M5
10b
3:2
1:0
Y4Y5_ST1
Y4Y5_ST0
11b
01b
Y4,
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
Y5-State0/1definition:
11 – Y4/Y5 enabled (normal operation, PLL2 on)
Y4Y5_x Output State Selection(4)
25h
7
6
5
4
3
2
1
0
Y4Y5_7
Y4Y5_6
Y4Y5_5
Y4Y5_4
Y4Y5_3
Y4Y5_2
Y4Y5_1
Y4Y5_0
0b
0b
0b
0b
0b
0b
1b
0b
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
26h
27h
PLL2 SSC down/center selection:
7-Bit Y4-Output-Divider Pdiv4:
0 – down
1 – center
7
SSC2DC
0b
0 – reset and stand-by
1-to-127 – divider value
6:0
7
Pdiv4
—
01h
0b
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
1-to-127 – divider value
6:0
Pdiv5
01h
(1) Writing data beyond 30h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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www.ti.com
Table 11. PLL2 Configuration Register (continued)
OFFSET(1)
28h
Bit(2)
7:0
7:4
3:0
7:3
2:0
7:5
4:2
Acronym
Default(3)
DESCRIPTION
PLL2_0N [11:4
PLL2_0N [3:0]
PLL2_0R [8:5]
PLL2_0R[4:0]
PLL2_0Q [5:3]
PLL2_0Q [2:0]
PLL2_0P [2:0]
PLL2_0(5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
29h
000h
2Ah
2Bh
10h
010b
fVCO2_0 range selection:
00 – fVCO2_0 < 125 MHz
01 – 125 MHz ≤ fVCO2_0 < 150 MHz
10 – 150 MHz ≤ fVCO2_0 < 175 MHz
11 – fVCO2_0 ≥ 175 MHz
1:0
VCO2_0_RANGE
00b
2Ch
2Dh
7:0
7:4
3:0
7:3
2:0
7:5
4:2
PLL2_1N [11:4]
PLL2_1N [3:0]
PLL2_1R [8:5]
PLL2_1R[4:0]
PLL2_1Q [5:3]
PLL2_1Q [2:0]
PLL2_1P [2:0]
PLL2_1(5): 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information see paragraph PLL Multiplier/Divider Definition)
004h
000h
2Eh
2Fh
10h
010b
fVCO2_1 range selection:
00 – fVCO2_1 < 125 MHz
01 – 125 MHz ≤ fVCO2_1 < 150 MHz
10 – 150 MHz ≤ fVCO2_1 < 175 MHz
11 – fVCO2_1 ≥ 175 MHz
1:0
VCO2_1_RANGE
00b
(5) PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096.
20
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CDCE925
CDCEL925
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SCAS847F –JULY 2007–REVISED MARCH 2010
PLL Multiplier/Divider Definition
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE925/CDCEL925 can be calculated:
ƒ
IN
N
M
ƒ
+
OUT
Pdiv
(1)
where
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output
divider.
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
M
ƒ
+ ƒ
VCO
IN
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
N
NȀ
ǒlog Ǔ[if P t 0 then P + 0]
ǒ Ǔ
2 M
M
NP = 4 – int
where
Q = int
R = N′ – M × Q
N′ = N × 2PN ≥ M100 MHz < ƒVCO > 200 MHz
16 ≤ q ≤63
0 ≤ p ≤ 7
0 ≤ r ≤ 511
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
→ fOUT = 54 MHz
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ N′’ = 4 × 22 = 16
→ P = 4 – int(log25.5) = 4 – 2 = 2
→ N′’ = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ is automatically calculated when using TI Pro-Clock™ software.
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SCAS847F –JULY 2007–REVISED MARCH 2010
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REVISION HISTORY
Changes from Original (July 2007) to Revision A
Page
•
Changed the data sheet status From: Product Preview To: Production data. ..................................................................... 1
Changes from Revision A (August 2007) to Revision B
Page
•
•
•
•
•
•
•
•
•
Changed IDDPD Power-down current Typ value From: 20 To: 30 .......................................................................................... 6
Changed II LVCMOS Input current value From: ±5 Typ To: ±5 Max .................................................................................... 6
Changed IIH LVCMOS Input current for S0/S1/S2 value From: 5 Typ To: 5 Max ................................................................ 6
Changed IIL LVCMOS Input current for S0/S1/S2 value From: -4 Typ To: -4 Max .............................................................. 6
Changed text of Note 4 in the DEVICE CHARACTERISTIC table ....................................................................................... 7
Changed Figure 2, Test Load for 50-Ω Board Environment ................................................................................................. 8
Changed Table 2 header From: OUTPUT SELECTION (Y2 ... Y9) To: OUTPUT SELECTION (Y2 ... Y5) ...................... 10
Changed Table 9 - 01h Bit 7 From: For interla use – always write To: Reserved – always write ..................................... 16
Changed Table 9 - PLL2_1N [11:4] description From: fVCO1_1 To: fVCO2_1 .......................................................................... 20
Changes from Revision B (August 2007) to Revision C
Page
•
•
•
Changed the PACKAGE THERMAL RESISTANCE for TSSOP table ................................................................................. 3
Changed Table 9 - RID From: 0h To: Xb ........................................................................................................................... 16
Added note to the PWDN description, Table 9 ................................................................................................................... 16
Changes from Revision C (December 2007) to Revision D
Page
•
Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. .................. 3
Changes from Revision D (September 2009) to Revision E
Page
•
Deleted sectence - A different default setting can be programmed on customer request. Contact Texas Instruments
sales or marketing representative for more information. .................................................................................................... 11
Changes from Revision E (October 2009) to Revision F
Page
•
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 to PLL1 and PLL2 Configure Register tables ............. 18
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<511 to PLL Multiplier/Divder Definition Section .................... 21
22
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2010
PACKAGING INFORMATION
Orderable Device
CDCE925PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCE925PWG4
CDCE925PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCE925PWRG4
CDCEL925PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCEL925PWG4
CDCEL925PWR
CDCEL925PWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCE925PWR
CDCEL925PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCE925PWR
CDCEL925PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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