概述
数据手册
替代型号CDCF5801 概述
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT 的时延控制和相位校准时钟乘法器
CDCF5801 数据手册
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
FEATURES
APPLICATIONS
•
•
•
•
•
Video Graphics
Gaming Products
Datacom
•
Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
•
Programmable Bidirectional Delay Steps of
1.3 mUI
Telecom
•
•
Output Frequency Range of 25 MHz to
280 MHz
Noise Cancellation Created by FPGAs
Input Frequency Range of 12.5 MHz to
240 MHz
DBQ PACKAGE
(TOP VIEW)
•
•
Low Jitter Generation
1
24
23
22
21
20
19
18
17
16
15
14
13
VDDREF
REFCLK
VDDP
P0
P1
Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and
LVPECL)
2
3
VDDO
GNDO
CLKOUT
NC
CLKOUTB
GNDO
VDDO
MULT0
MULT1
P2
4
GNDP
GND
5
•
•
•
Differential/Single-Ended Output
6
LEADLAG
DLYCTRL
GNDPA
VDDPA
VDDPD
STOPB
PWRDNB
Output Can Drive LVPECL, LVDS, and LVTTL
7
Three Power Operating Modes to Minimize
Power
8
9
•
•
Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
10
11
12
Packaged in a Shrink Small-Outline Package
(DBQ)
•
•
No External Components Required for PLL
Spread Spectrum Clock Tracking Ability to
Reduce EMI (SSC)
DESCRIPTION
The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability
to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising
edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input
detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin
the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This
unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other
CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it
provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,
while strapping the LEADLAG pin to dc high or low. Further possible applications are:
•
•
•
•
Aligning the rising edge of the output clock signal to the input clock rising edge
Avoiding PLL instability in applications that require very long PLL feedback lines
Isolation of jitter and digital switching noise
Limitation of jitter in systems with good ppm frequency stability
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
CDCF5801
www.ti.com
SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal. The device is
optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider
pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB
frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to
240 MHz. See Table 1 for detailed frequency support. The selection of pins MULT[0:1] and P[1:2] determines the
multiplication value of 1, 2, 4, or 8. The CDCF5801 offers several power-down/ high-impedance modes,
selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801 is the high sensitivity
and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The
clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals.
The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDS,
LVPECL, or HSTL/SSTL signaling. The CDCF5801 is characterized for operation over free-air temperatures of
-40°C to 85°C.
2
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
3
CDCF5801
www.ti.com
SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CLKOUT
CLKOUTB
DLYCTRL
2018
O
I
Output CLK signal (low-noise CMOS) Complementary output CLK signal (low-noise CMOS)
7
Every rising edge on this pin delays/advances the CLKOUT/CLKOUTB signal by 1/768th of the
CLKOUT/CLKOUTB period (1.3 mUI). (E.g., for a 90-degree delay or advancement one needs to
provide 192 rising edges). See Table 3.
GND
5
17, 21
4
GND for VDDREF and VDDPD
GNDO
GNDP
GND for the output pins (CLKOUT, CLKOUTB)
GND for the PLL
GNDPA
LEADLAG
8
GND for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB, PWRDNB
Controls whether the output CLK is delayed or advanced relative to REFCLK. See Table 3.
PLL multiplication factor select. See Table 1.
MULT[0:1] = 10: ×16
6
I
I
MULT0
MULT1
15
14
MULT[0:1] = 11: ×8
MULT[0:1] = 00: ×4
MULT[0:1] = 01: ×2
NC
P0
19
24
Not connected; leave pin floating or tied to GND.
Mode control pins (see Table 1)
0 - Normal operation
I
I
1 - High-Z outputs and other special settings
Post divider control (see Table 1)
P[1:2] = 11: div2
P1
23
P[1:2] = 10: div4
P2
13
12
P[1:2] = 01: div8
PWRDNB
I
Active-low power-down state. CLKOUT/CLKOUTB goes low, See Table 2).
0 - IC in power down
1 - Normal operation
REFCLK
STOPB
2
I
I
Reference input clock
11
Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as
listed in Table 2.
0 - Outputs disabled
1 - Normal operation
VDDO
16, 22
VDD for the output pin (CLKOUT, CLKOUTB) and power down circuit
VDD for PLL and input buffer
VDDP
3
9
VDDPA
VDDPD
VDDREF
VDD for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], and STOPB
Reference voltage for inputs LEADLAG and DLYCTRL
Reference voltage for REFCLK
10
1
4
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
Table 1. Input-to-Output Settings
INPUT FRE-
QUENCY (MHz)
OUTPUT FRE-
QUENCY (MHz)
PREDIVIDER
MULT0 MULT1
POST DIVIDER
INPUT-TO-OUTPUT MULTIPLI-
CATION-RATIO
NOTE
FROM
12.5
12.5
25
TO
35
FROM
100
50
TO
280
156
280
78
P0
P1
1
P2
1
8
4
1
0
39
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
1
0
70
100
25
1
1
12.5
25
39
0
1
2
1
78
50
156
280
78
0
1
0
Normal operation(1)
50
140
78
100
25
1
1
25
0
1
50
156
240
50
156
240
1
0
100
100
1
1
CLKOUT high-impedance
CLOUOTB high-impedance
CLKOUT = high
X
X
X
X
X
X
0
0
1
0
1
1
Special mode of operation
CLKOUTB = high
CLKOUT = P2
X
CLKOUTB = P2
(1) There is some overlapping of the input frequency ranges for multiplication ratios of 1, 2, and 4. For example, an input frequency of 30
MHz for a multiplication ratio of four falls within both the 12.5 to 39-MHz range and the 25 to 70-MHz range. For best device operation in
a case such as this, always select the input frequency range nearer to the top of the table.
PLL DIVIDER/MULITPLIER SELECTION
Table 2. Power Down Modes
STATE
Power down
Clock stop
Normal
PWRDNB
STOPB
CLKOUT and CLKOUTB
GNDO
0
1
1
X
0
1
VO, STOP
See Table 1
Table 3. Programmable Delay and Phase Alignment
DLYCTR
NOTE
LEADLAG
CLKOUT and CLKOUTB
Advanced by one step:
For every 32 edges, there are one or two
Each rising
edge+
step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01
HI
edges for which the phase aligner does not
update the phase. Therefore, CLKOUT
phase is not updated for every 32nd edge.
The frequency of the DLYCTRL pin should
always be equal to or less than the
Delayed by one step:
Each rising
edge+
step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01
LO
frequency of the LEADLAG pin.
5
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)(1)
(2)
VDDx
Supply voltage range
-0.5 V to 4 V
Voltage range at any output terminal
Voltage range at any input terminal
Storage temperature range
-0.5 V to VDD + 0.5 V
-0.5 V to VDD + 0.5 V
-65°C to 150°C
260°C
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
POWER DISSIPATION RATING TABLE
TA≤ 25°C POWER DERATING FAC-
TA = 85°C
PACK-
AGE
RATING
TOR(1) ABOVE TA POWER RATING
= 25°C
DBQ
830 mW
8.3 mW/°C
332 mW
(1) This is the inverse of the junction-to-ambient thermal resistance
when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
VDDP, VDDPA, VDDO
VIH (CMOS)
Supply voltage
3
3.3
3.6
V
V
V
High-level input voltage
Low-level input voltage
0.7 VDD
VIL (CMOS)
0.3 VDD
VDDPD
VIL (DLYCTRL, LEADLAG)
VIH (DLYCTRL, LEADLAG)
Input signal low voltage
Input signal high voltage
V
* 0.2
2
VDDPD
V
V
) 0.2
2
(VDDPD)
IOH
Input reference voltage for DLYCNTRL and LEADLAG
High-level output current
1.2
VDD
-16 mA
IOL
Low-level output current
16
mA
(VDDREF) (see Application
section)
Input reference voltage for REFCLK
REFCLK input low voltage
1.2
VDD
V
VIL (see Application section)
VDDREF
2
V
* 0.2
VDDREF
2
VIH (see Application section)
TA
REFCLK input high voltage
V
) 0.2
Operating free-air temperature
-40
85
°C
TIMING REQUIREMENTS
PARAMETER
MIN
MAX UNIT
Fmod
SR
Input frequency of modulation, (if driven by SSC CLKIN)
Modulation index, nonlinear maximum 0.5%
Input slew rate
33
0.6%
4
kHz
1
40%
12.5
25
V/ns
Input duty cycle on REFCLK
60%
240
280
240
Input frequency on REFCLK
MHz
MHz
MHz
Output frequency on CLKOUT and CLKOUTB
Allowable frequency on DLYCTRL
6
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
TIMING REQUIREMENTS (continued)
PARAMETER
MIN
MAX UNIT
Allowable frequency on LEADLAG
280
MHz
Allowable duty cycle on DLYCTRL and LEADLAG pins
25%
75%
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN TYP(2)
MAX UNIT
VO(STOP)
VO(X)
Output voltage during Clkstop mode See Figure 1
1.1
2
V
VDDO
2
VDDO
2
Output crossing-point voltage
See Figure 1 and Figure 4
V
*0.2
) 0.2
VO
Output voltage swing (VOH - VOL
)
See Figure 1
VDD = 3 V,
1.7
2.9
V
V
VIK
Input clamp voltage
II = -18 mA
-1.2
VDD = 3 to 3.6 V, See Figure 1
VDD = 3 V, IOH = -16 mA
VDD = 3 to 3.6 V, See Figure 1
2
2.5
0.4
VOH
High-level output voltage
Low-level output voltage
V
V
2.2
0.6
0.5
VOL
VDD = 3 V,
IOH = 16 mA
VO = 1 V
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
-32
43
-52
-51
IOH
High-level output current
Low-level output current
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
P1 = P2 = 0
mA
mA
-14.5
61.5
65
-21
IOL
25.5
40
IOZ
High-impedance-state output current P0 = 1,
±10
µA
µA
High-impedance-state output current
Stop = 0,
IOZ(STOP)
VO = GND or VDD
±100
during Clk Stop
High-impedance-state output current
IOZ(PD)
IIH
PWRDNB = 0,
VO = GND or VDD
VI = VDD
-10
100
10
µA
µA
in power-down state
REFCLK; STOPB;
PWRDNB; P[0:2];
input current MULT[0:1];
DLYCTRL; LEADLAG
High state
VDD = 3.6 V,
VDD = 3.6 V,
High-level
IIL
VI =0
-10
50
35
µA
Output
RI at IO-14.5 mA to -16.5 mA
RI at IO 14.5 mA to 16.5 mA
15
10
35
17
impedance
(single
ended)
ZO
Ω
Low state
PWRDNB = 0
PWRDNB = 1
50
µA
mA
pF
Reference
current
IREF
VDDREF; VDDPD
VDD = 3.6 V
0.5
CI
Input capacitance
Output capacitance
VI = VDD or GND
VO = GND or VDD
2
3
CO
pF
REFCLK = 0 MHz to 280 MHz;
PWRDNB = 0; STOPB = 1
IDD(PD)
Supply current in power-down state
4
44
75
mA
mA
mA
IDD(CLKSTOP) Supply current in CLK stop state
BUSCLK configured for 280 MHz
Supply current (normal operation
BUSCLK 280 MHz, MULT[0:1] = 10;
P[0:2] = 011; Load , See Figure 1
IDD(NORMAL)
mode)
(1) VDD refers to any of the following; VDDP, VDDREF, VDDO, VDDPD, and VDDPA
(2) All typical values are at VDD = 3.3 V, TA = 25°C.
7
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
JITTER SPECIFICATION
over recommended free-air temperature range and VCC range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TYP (ps)
MAX (ps)
REFCLK
(MHz)
CLKOUT
(MHz)
MULT[0:1] P[0:2]
NOTES
Period rms (1-sigma jitter, full
frequency band)
25
25
11
11
00
00
01
001
001
010
010
011
20
48
Period p-p
120
70
225
165
165
160
Cycle to cycle +
Cycle to cycle -
70
RMS phase jitter (accumulated,
100 kHz-12.5 MHz)
80
Period rms (1-sigma jitter, full
frequency band)
50
50
7
15
Period p-p
37
27
27
27
75
55
55
65
Cycle to cycle +
Cycle to cycle -
Phase
aligner run-
ning
(CLKOUT
tight to
LEADLAG;
REFCLK
tight to
DLYCTRL).
All typical
values are
at
VDD = 3.3
V,
RMS phase jitter (accumulated,
100 kHz-25 MHz)
Period rms (1-sigma jitter, full
frequency band)
100
156
200
100
156
200
5
14
Period p-p
30
24
24
35
65
55
55
65
t(jitter)
Cycle to cycle +
Cycle to cycle -
RMS phase jitter (accumulated,
100 kHz-40 MHz)
Period rms (1-sigma jitter, full
frequency band)
4
8
TA = 25°C.
Period p-p
20
17
17
15
40
40
40
35
Cycle to cycle +
Cycle to cycle -
RMS phase jitter (accumulated,
100 kHz-40 MHz)
Period rms (1-sigma jitter, full
frequency band)
8
15
Period p-p
38
5
60
55
55
60
Cycle to cycle +
Cycle to cycle -
35
30
RMS phase jitter (accumulated,
100 kHz-40 MHz)
8
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
JITTER SPECIFICATION (continued)
over recommended free-air temperature range and VCC range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TYP (ps)
MAX (ps)
REFCLK
(MHz)
CLKOUT
(MHz)
MULT[0:1] P[0:2]
NOTES
Period rms (1-sigma jitter, full
frequency band)
25
25
200
100
280
50
10
10
11
10
11
00
011
010
011
001
010
011
4
11
Period p-p
20
16
16
4
48
45
45
11
Cycle to cycle +
Cycle to cycle -
Period rms (1-sigma jitter, full
frequency band)
Period p-p
22
15
15
4
55
45
45
11
Cycle to cycle +
Cycle to cycle -
Period rms (1-sigma jitter, full
frequency band)
70
Phase
aligner
not running
(LEADLAG
= 0,
DLYCTRL =
0). All typi-
cal
values are
at
VDD = 3.3
Period p-p
18
15
15
6
48
45
45
16
Cycle to cycle +
Cycle to cycle -
t(jitter)
Period rms (1-sigma jitter, full
frequency band)
25
Period p-p
34
20
20
3
75
65
65
11
Cycle to cycle +
Cycle to cycle -
V, TA
=
25°C.
Period rms (1-sigma jitter, full
frequency band)
78
156
125
Period p-p
15
13
13
6
44
40
40
20
Cycle to cycle +
Cycle to cycle -
Period rms (1-sigma jitter, full
frequency band)
62.5
Period p-p
35
25
25
80
75
75
Cycle to cycle +
Cycle to cycle -
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 3
MIN
TYP
MAX UNIT
t(DC)
tr, tf
Output duty cycle over 1000 cycles
42%
150
58%
Output rise and fall times (measured at 20%-80% of output voltage
See Figure 5
250
350
ps
STATE TRANSITION LATENCY SPECIFICATIONS
TEST
CONDITION
PARAMETER
FROM
TO
MIN
TYP
MAX UNIT
Delay time, PWRDNB↑ to CLKOUT /
CLKOUTB settled
3
t(powerup)
Power down Normal
See Figure 6
ms
3
Delay time, PWRDNB↑ to internal PLL
and clock are on and settled
9
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
STATE TRANSITION LATENCY SPECIFICATIONS (continued)
TEST
CONDITION
PARAMETER
FROM
TO
MIN
TYP
MAX UNIT
Delay time, power up to CLKOUT
output settled
3
t(VDDpowerup)
VDD
Normal
See Figure 6
ms
3
Delay time, power up to internal PLL
and clock are on and settled
MULT0 and MULT1 change to
CLKOUT output resettled
t(MULT)
Normal
Normal
Normal
See Figure 7
See Figure 8
1
ms
ns
STOPB↑ to CLKOUT glitch-free clock
edges
t(CLKON)
CLK stop
10
STOPB↑ to CLKOUT output settled to
within 50 ps of the phase before
STOPB was disabled
t(CLKSETL)
CLK stop
Normal
See Figure 8
See Figure 8
20 cycles
t(CLKOFF)
STOPB↓ to CLKOUT output disabled
Normal
Normal
CLK stop
5
1
ns
Delay time, PWRDNB↓ to the device in
the power-down mode
t(powerdown)
Power down See Figure 6
ms
Maximum time in CLKSTOP (STOPB =
0) before reentering normal mode
(STOPB = 1)
t(STOP)
STOPB
Normal
Normal
See Figure 8
See Figure 8
100
100
µs
Minimum time in normal mode (STOPB
= 1) before reentering CLKSTOP
(STOPB = 0)
t(ON)
CLK stop
ms
PARAMETER MEASUREMENT INFORMATION
TESTING CONDITIONS
CLKOUT
50 Ω
V
CM
10 pF
50 Ω
CLKOUTB
Figure 1. Test Load and Voltage Definitions VOH, VOL, VO(STOP)
CLKOUT
CLKOUTB
t (i)
CYCLE
t (i+1)
CYCLE
Cycle-to-Cycle Jitter (t ) = | t (i) - t (i+1) | over 1000 consecutive cycles
(jitter) CYCLE CYCLE
Figure 2. Cycle-to-Cycle Jitter
10
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
CLKOUT
CLKOUTB
t
PW+
t
CYCLE
Duty Cycle = (t
/t
)
PW+ CYCLE
Figure 3. Output Duty Cycle
CLKOUT
V
V
V
O(X)+
O(X), nom
O(X)-
CLKOUTB
Figure 4. Crossing Point Voltage
V
OH
80%
20%
V
OL
t
r
t
f
Figure 5. Voltage Waveforms
PWRDNB
t
(powerdown)
t
(powerup)
CLKOUT
CLKOUTB
Figure 6. PWRDNB Transition Timings
MULT0
and/or
MULT1
t
(MULT)
CLKOUT
CLKOUTB
Figure 7. MULT Transition Timings
11
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
t
(ON)
t
(STOP)
STOPB
t
(CLKSETL)
t
(CLKOFF)
t
(CLKON)
(see Note A)
(see Note A)
CLKOUT
CLKOUTB
Output clock
not specified
glitches ok
Clock output settled
within 50 ps of the
phase before disabled
Clock enabled
and glitch free
A. Vref = VO±200 mV
Figure 8. STOPB Transition Timings
12
CDCF5801
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SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION
APPLICATION EXAMPLE
The following figure shows an example of using the CDCF5801 as a ×4 multiplier with the phase aligner
de-skewing the unknown buffer delay of the two CDCV304s in the circuit. This circuitry would not be possible
with a simple PLL because the feedback of the PLL would have the second CDCV304 in the loop, causing
instability of the PLL due to a long delay.
Z = 50 Ω; Length = L1
30 Ω
25 MHz
CDCV304
Clock Buffer
25 MHz
Z = 50 Ω
CLK
Outputs are Phase Aligned
Between the Two Buffers
CDCF5801
VDDREF
P0
P1
3.3 V
3.3 V
REFCLK
VDDP
CDCV304
3.3 V
VDDO
GNDO
Clock Buffer
25 MHz
25 MHz
Z = 50 Ω
GNDP
GND
CLKOUT
CLK
35 Ω
LEADLAG
DLYCTRL
GNDPA
VDDPA
VDDPD
STOPB
PWRDNB
NC
CLKOUTB
GNDO
VDDO
3.3 V
3.3 V
MULT0
MULT1
P2
Z = 50 Ω; Length = L1
Figure 9. Application Example
NOTE:
If an active element (microcontroller, ASIC, DSP< FPYA, DSP, etc.) is used in the
CDCF5801 CLKOUT to DLYCTRL feedback loop, see application report SCAA075.
SELECTING VDDREF
Generally, VDDREF can be set to any value between 1.2 V and VDD. The setting of VDDREF directly influences
the trigger voltage of the input. Special care must be taken when using small signal swings to drive the
CVDCF5801 input (e.g., PECL). It is recommended to connect VDDREF directly to VDD, ac-couple the REFCLK
input, and rebias the signal.
The following circuit is recommended to drive the CDCF5801 from a differential clock signal like PECL.
13
CDCF5801
www.ti.com
SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION (continued)
3.3 V ± 10%
R1
150 Ω
100 Ω
CDCF5801
VDDREF
Z = 50 Ω
REFCLK
PECL
R2
100 Ω
GNDP
GND
150 Ω
A. NOTE: If more signal swing is required and an unterminated transmission is on option, then R1 and R2 can both be
replaced with 10-kΩ resistors.
14
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
CDCF5801DBQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
24
24
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
CDCF5801DBQR
CDCF5801DBQRG4
SSOP/
QSOP
DBQ
DBQ
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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CDCF5801 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CDCF5801A | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 功能相似 |
|
CDCF5801 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CDCF5801A | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801ADBQ | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801ADBQG4 | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801ADBQR | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801ADBQRG4 | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801DBQ | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801DBQG4 | TI | Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps 24-SSOP -40 to 85 | 获取价格 |
|
| CDCF5801DBQR | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801DBQRG4 | TI | CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT | 获取价格 |
|
| CDCF5801_14 | TI | CLOCK MULTIPLIER | 获取价格 |
|
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