CDCL1810 [TI]
1.8V, 10 Output, High-Performance Clock Distributor; 1.8V ， 10路输出，高性能时钟经销商
| 型号： | CDCL1810 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.8V, 10 Output, High-Performance Clock Distributor |
| 文件： | 总25页 (文件大小：545K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCL1810
www.ti.com
SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
1.8V, 10 Output, High-Performance Clock Distributor
FEATURES
•
•
•
•
Output Enable Control for Each Output
SDA/SCL Device Management Interface
48-pin QFN (RGZ) Package
•
Single 1.8V Supply
•
High-Performance Clock Distributor with 10
Outputs
Industrial Temperature Range: –40°C to +85°C
•
Low Input-to-Output Additive Jitter:
As Low As 10fs RMS
APPLICATIONS
•
Clock Synthesis and Distribution for
High-Speed SERDES
Synthesis and Distribution of SERDES
Reference Clocks for 1G/10G Ethernet,
1X/2X/4X/10X Fibre Channel, PCI Express,
Serial ATA, SONET, CPRI, OBSAI, etc.
•
•
Output Group Phase Adjustment
Low-Voltage Differential Signaling (LVDS)
Input, 100Ω Differential On-Chip Termination,
Up to 650MHz Frequency
•
•
Differential Current Mode Logic (CML)
Outputs, 50Ω Single-Ended On-Chip
Termination, Up to 650MHz Frequency
•
Up to 1-to-10 Clock Buffering and Fan-out
•
•
•
•
Two Groups of Five Outputs Each with
Independent Frequency Division Ratios
Output Frequency Derived with Divide Ratios
of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS
Standard Requirements
Power Consumption: 410mW Typical
5 Differential
CML Outputs
Up to 650MHz
DIVIDER
Differential
LVDS Input
Up to 650MHz
5 Differential
CML Outputs
Up to 650MHz
DIVIDER
SDA/SCL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
CDCL1810
www.ti.com
SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
DESCRIPTION
The CDCL1810 is
distributor. The programmable dividers, P0 and P1,
give a high flexibility to the ratio of the output
frequency to the input frequency:
a
high-performance clock
The phase of one output group relative to the other
can be adjusted through the SDA/SCL interface. For
post-divide ratios (P0, P1) that are multiples of 5, the
total number of phase adjustment steps (n) equals
the divide-ratio divided by 5. For post-divide ratios
(P0, P1) that are not multiples of 5, the total number
of steps (n) is the same as the post-divide ratio. The
phase adjustment step (∆Φ) in time units is given as:
FOUT = FIN/P
Where:
P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
∆Φ = 1/(n × FOUT
)
The CDCL1810 supports one differential LVDS clock
input and a total of 10 differential CML outputs. The
CML outputs are compatible with LVDS receivers if
they are ac-coupled.
where FOUT is the respective output frequency.
The device operates in a 1.8V supply environment
and is characterized for operation from –40°C to
+85°C. The CDCL1810 is available in a 48-pin QFN
(RGZ) package.
With careful observation of the input voltage swing
and common-mode voltage limits, the CDCL1810
can support a single-ended clock input as outlined in
the Pin Description Table.
All device settings are programmable through the
SDA/SCL, serial two-wire interface.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
AVAILABLE OPTIONS(1)
TA
PACKAGED DEVICES
CDCL1810RGZT
FEATURES
48-pin QFN (RGZ) Package, small tape and reel
48-pin QFN (RGZ) Package, tape and reel
–40°C to +85°C
–40°C to +85°C
CDCL1810RGZR
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
–0.3 to 2.5
–0.3 to 4.0
–0.3 to 3.0
2
UNIT
V
VDD, AVDD
VLVDS
VI
Supply voltage(2)
Voltage range at LVDS input pins(2)
Voltage range at all non-LVDS input pins(2)
Electrostatic discharge (HBM)
Junction temperature
V
V
ESD
TJ
kV
°C
°C
+125
TSTG
Storage temperature range
–65 to +150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN
1.7
NOM
1.8
MAX UNIT
VDD
Digital supply voltage
1.9
1.9
V
V
AVDD Analog supply voltage
1.7
1.8
TA
TJ
Ambient temperature (no airflow, no heatsink)
–40
+85
°C
°C
Junction temperature
Junction-to-ambient thermal resistance(1)
airflow = 0 lfm
+105
θJA
:
28.3
22.4
°C/W
airflow = 50 lfm
(1) No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board.
3
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DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
All outputs enabled; VDD = VDD,typ
650MHz LVDS input
IVDD
Total current from digital 1.8V supply
212
mA
All outputs enabled; AVDD = VDD,typ
650MHz LVDS input
IAVDD
Total current from analog 1.8V supply
16
mA
VIL,CMOS
VIH,CMOS
IIL,CMOS
IIH,CMOS
Low level CMOS input voltage
High level CMOS input voltage
Low level CMOS input current
High level CMOS input current
VDD = 1.8V
–0.2
0.6
VDD
–120
65
V
V
VDD = 1.8V
VDD –0.6
VDD = VDD,max, VIL = 0.0V
VDD = VDD,max, VIH = 1.9V
µA
µA
Low level CMOS output voltage for the
SDA pin
VOL,SDA
IOL,CMOS
Sink current = 3 mA
0
0.2VDD
8
V
Low level CMOS output current
mA
AC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
90
TYP
MAX
132
UNIT
Ω
Differential input impedance for
the LVDS input terminals
ZD,IN
VCM,IN
Common-mode voltage, LVDS
input
1125
1200
1375
mV
Single-ended LVDS input voltage
swing
VS,IN
VD,IN
100
200
600
mVPP
mVPP
Differential LVDS input voltage
swing
1200
tR,OUT
tF,OUT
,
Output signal rise/fall time
20%–80%
100
ps
V
VCM,OUT
VS,OUT
VD,OUT
Common-mode voltage, CML
outputs
VDD – 0.31 VDD – 0.23 VDD – 0.19
Single-ended CML output voltage ac-coupled
swing
180
360
230
460
280
560
mVPP
mVPP
Differential CML output voltage
swing
ac-coupled
FIN
Clock input frequency
Clock output frequency
650
650
MHz
MHz
FOUT
4
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AC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
JOUT
Additive clock output jitter
FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 200mVPP
10Hz–1MHz offset
1MHz–5MHz offset
12kHz–5MHz offset
188
480
514
fs RMS
fs RMS
fs RMS
FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 1200mVPP
10Hz–1MHz offset
1MHz–5MHz offset
12kHz–5MHz offset
257
500
570
fs RMS
fs RMS
fs RMS
FIN = 650MHz, FOUT = 650MHz
VD,IN = 200mVPP
10Hz–1MHz offset
1MHz–20MHz offset
12kHz–20MHz offset
27
66
72
fs RMS
fs RMS
fs RMS
FIN = 650MHz, FOUT = 650MHz
VD,IN = 1200mVPP
10Hz–1MHz offset
1MHz–20MHz offset
12kHz–20MHz offset
12
23
27
fs RMS
fs RMS
fs RMS
TP
Input-to-output delay
Clock output skew
FIN = 30.72MHz, FOUT = 30.72MHz
YP[9:0] outputs
3
ns
ps
FIN = 30.72MHz, FOUT = 30.72MHz
YP[9:0] outputs relative to YP[0]
TSOUT
–64
64
AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE(1)
PARAMETER
MIN
TYP
MAX
UNIT
kHz
µs
fSCL
SCL frequency
400
th(START)
tw(SCLL)
tw(SCLH)
tsu(START)
th(SDATA)
tsu(DATA)
tr(SDATA)
tf(SDATA)
tsu(STOP)
tBUS
START hold time
SCL low-pulse duration
SCL high-pulse duration
START setup time
SDA hold time
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
SDA setup time
0.6
µs
SCL / SDA input rise time
SCL / SDA input fall time
STOP setup time
0.3
0.3
µs
µs
0.6
1.3
µs
bus free time
µs
(1) See Figure 3 for the timing behavior.
5
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DEVICE INFORMATION
48-PIN QFN (RGZ)
(TOP VIEW)
36 ADD0
35 VDD
34 YN7
33 YP7
32 VDD
31 YN6
30 YP6
29 VDD
28 YN5
27 YP5
26 VDD
25 SDA
NC
AVDD
CLKP
CLKN
AVDD
YP0
1
2
3
4
5
6
7
8
9
CDCL1810
YN0
VDD
YP1
YN1 10
VDD 11
VSS 12
NOTE: Exposed thermal pad must be soldered to VSS
.
The CDCL1810 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad
serves both thermal and electrical grounding purposes.
NOTE:
The device must be soldered to ground (VSS) using as many ground vias as possible.
The device performance will be severely impacted if the exposed thermal pad is not
grounded appropriately.
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SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME
PIN NO.
TYPE
DESCRIPTION
8, 11, 14, 17,
20, 23, 26,
29, 32, 35,
38, 41
VDD
Power
1.8V digital power supply.
AVDD
VSS
2, 5, 44, 47
Power
Power
1.8V analog power supply.
Ground reference.
Exposed
thermal pad
and pin 12
1, 13, 45, 46,
48
NC
I
I
Not connected; leave open.
Differential LVDS input. Single-ended 1.8-V input can be dc-coupled to pin 3 with pin 4
either tied to pin 3 (recommended) or left open.
CLKP, CLKN
3, 4
YP0, YN0
YP1, YN1
YP2, YN2
YP3, YN3
YP4, YN4
YP5, YN5
YP6, YN6
YP7, YN7
YP8, YN8
YP9, YN9
6, 7
9, 10
15, 16
18, 19
21, 22
27, 28
30, 31
33, 34
40, 39
43, 42
O
10 differential CML outputs.
SCL
SDA
24
25
I
SDA/SCL serial clock pin. Open drain. Always connect to a pull-up resistor.
I/O
SDA/SCL bidirectional serial data pin. Open drain. Always connect to a pull-up resistor.
Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed
most significant bits (ADD[6:2]) of the 7-bit device address are 11010.
ADD1, ADD0
37, 36
I
7
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FUNCTIONAL BLOCK DIAGRAM
VDD
Divider
P1
YP[9:5]
YN[9:5]
CML
CML
CLKP
LVDS
CLKN
Divider
P0
YP[4:0]
YN[4:0]
Divider Setting
SDA/SCL
Control
Outputs Disable to Low or 3-State
VSS
8
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TYPICAL CHARACTERISTICS
Typical operating conditions are at VDD = 1.8V and TA = +25°C, VD,IN = 200mVPP (unless otherwise noted).
TRANSIENT PERFORMANCE:
FIN = 30.72MHz, FOUT = 30.72MHz
300
200
100
0
-100
-200
-300
0
20
40
60
80
100
t - Time - ns
Figure 1.
TRANSIENT PERFORMANCE:
FIN = 650MHz, FOUT = 650MHz
300
200
100
0
-100
-200
-300
0
1
2
3
4
5
t - Time - ns
Figure 2.
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SDA/SCL INTERFACE
This section describes the SDA/SCL interface of the
CDCL1810 device. The CDCL1810 operates as a
slave device of the industry standard 2-pin SDA/SCL
bus. It operates in the fast-mode at a bit-rate of up to
400 kbit/s and supports 7-bit addressing compatible
with the popular 2-pin serial interface standard.
The device address is made up of the fixed internal
address, 11010 (A6:A2), and configurable external
pins ADD1 (A1) and ADD0 (A0). Four different
devices with addresses 1101000, 1101001, 1101010
and 1101011, can be addressed via the same
SDA/SCL bus interface. The least significant bit of
the address byte designates
operation.
a write or read
SDA/SCL Bus Slave Device Address
A6
A5
A4
A3
A2
A1
A0
R/W
R/W Bit:
1
1
0
1
0
ADD1 ADD0
0/1
0 = write to CDCL1810 device
1 = read from CDCL1810 device
Command Code Definition
BIT
C7
DESCRIPTION
1 = Byte Write / Read or Word Write / Read operation
Byte Offset for Byte Write / Read and Word Write / Read operation.
(C6:C0)
Command Code for Byte Write / Read
Hex
Operation
Code
C7
1
C6
0
C5
0
C4
0
C3
0
C2
0
C1
0
C0
0
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
byte 6
80h
81h
82h
83h
84h
85h
86h
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
Command Code for Word Write / Read
Hex
Operation
Code
C7
1
C6
0
C5
0
C4
0
C3
0
C2
0
C1
0
C0
0
word 0: byte 0 and byte 1
word 1: byte 1 and byte 2
word 2: byte 2 and byte 3
word 3: byte 3 and byte 4
word 4: byte 4 and byte 5
word 5: byte 5 and byte 6
word 6: byte 6 and byte 7
80h
81h
82h
83h
84h
85h
86h
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
10
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SDA/SCL Timing Characteristics
TIMING CHARACTERISTICS
P
S
Bit 7 (MSB)
tw(SCLH)
Bit 6
Bit 0 (LSB)
A
P
tr(SM)
tf(SM)
tw(SCLL)
VIH(SM)
VIL(SM)
SCL
tSU(START)
t(BUS)
tSU(SDATA)
tr(SM)
th(SDATA)
tSU(STOP)
th(START)
tf(SM)
VIH(SM)
VIL(SM)
SDA
Figure 3. Timing Diagram for the SDA/SCL Serial Control Interface
SDA/SCL Programming Sequence
LEGEND FOR PROGRAMMING SEQUENCE
1
7
1
1
8
1
1
Data Byte
S
Slave Address
Wr
A
A
P
S
Sr
Rd
Wr
A
Start condition
Repeated start condition
Read (bit value = 1)
Write (bit value = 0)
Acknowledge (bit value = 0)
Not acknowledge (bit value = 1)
Stop condition
N
P
Master to Slave transmission
Slave to Master transmission
Byte Write Programming Sequence:
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
Byte Read Programming Sequence:
1
7
1
1
8
1
1
7
1
1
8
1
1
Wr
Command
Code
S
Slave Address
A
A
S
Slave Address
Rd
A
Data Byte
N
P
11
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Word Write Programming Sequence:
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
A
P
Word Read Programming Sequence:
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
Slave
Address
Command
Code
Slave
Address
S
Wr
A
A
S
Rd
A
Data Byte
A
Data Byte
N
P
SDA/SCL Bus Configuration Command Bitmap
Byte 0:
Power Up
Bit
7
Bit Name
MANF[7]
MANF[6]
MANF[5]
MANF[4]
MANF[3]
MANF[2]
MANF[1]
MANF[0]
Description/Function
Type
R
Condition
Reference To
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
Manufacturer reserved
6
R
5
R
4
R
3
R
2
R
1
R
0
R
Byte 1:
Power Up
Condition
Bit
7
Bit Name
RES
Description/Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reference To
Reserved
0
0
1
0
0
0
0
0
6
RES
Reserved
5
ENPH
PH1[4]
PH1[3]
PH1[2]
PH1[1]
PH1[0]
Phase select enable
4
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Phase select for YP[9:5] and YN[9:5]
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
3
2
1
0
Byte 2:
Power Up
Condition
Bit
7
Bit Name
RES
Description/Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reference To
Reserved
Reserved
0
0
1
1
0
0
0
0
6
RES
5
ENP1
RES
Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled
Reserved
4
3
SELP1[3] Divide ratio select for post-divider P1
SELP1[2] Divide ratio select for post-divider P1
SELP1[1] Divide ratio select for post-divider P1
SELP1[0] Divide ratio select for post-divider P1
Table 1
Table 1
Table 1
Table 1
2
1
0
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Byte 3:
Bit
Power Up
Bit
7
Name
Description/Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Condition Reference To
RES
Reserved
Reserved
Reserved
0
0
0
6
RES
5
RES
4
PH0[4]
PH0[3]
PH0[2]
PH0[1]
PH0[0]
Phase select for YP[4:0] and YN[4:0]
Phase select for YP[4:0] and YN[4:0]
Phase select for YP[4:0] and YN[4:0]
Phase select for YP[4:0] and YN[4:0]
Phase select for YP[4:0] and YN[4:0]
0
0
0
0
0
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
Table 2, Table 3
3
2
1
0
Byte 4:
Power Up
Bit
7
Bit Name
RES
Description/Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Condition Reference To
Reserved
0
0
1
1
6
RES
Reserved
5
ENP0
RES
Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled
Reserved
4
3
SELP0[3] Divide ratio select for post-divider P0
SELP0[2] Divide ratio select for post-divider P0
SELP0[1] Divide ratio select for post-divider P0
SELP0[0] Divide ratio select for post-divider P0
0
0
0
0
Table 1
Table 1
Table 1
Table 1
2
1
0
Byte 5:
Power Up
Bit
7
Bit Name
EN
Description/Function
Type
R/W
R
Condition Reference To
Chip enable; if 0 chip is in Iddq mode
Reserved
1
1
1
1
1
1
1
1
6
RES
5
ENDRV9
ENDRV8
ENDRV7
ENDRV6
ENDRV5
ENDRV4
YP[9], YN[9] enable; if 0 output is disabled
YP[8], YN[8] enable; if 0 output is disabled
YP[7], YN[7] enable; if 0 output is disabled
YP[6], YN[6] enable; if 0 output is disabled
YP[5], YN[5] enable; if 0 output is disabled
YP[4], YN[4] enable; if 0 output is disabled
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
Byte 6:
Power Up
Bit
7
Bit Name
ENDRV3
ENDRV2
ENDRV1
ENDRV0
RES
Description/Function
YP[3], YN[3] enable; if 0 output is disabled
YP[2], YN[2] enable; if 0 output is disabled
YP[1], YN[1] enable; if 0 output is disabled
YP[0], YN[0] enable; if 0 output is disabled
Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Condition Reference To
1
1
1
1
0
0
0
0
6
5
4
3
2
RES
Reserved
1
RES
Reserved
0
RES
Reserved
13
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CDCL1810
www.ti.com
SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
Table 1. Divide Ratio Settings for Post-Divider P0 or P1
Divide
Ratio
SELP1[3] or
SELP0[3]
SELP1[2] or
SELP0[2]
SELP1[1] or
SELP0[1]
SELP1[0] or
SELP0[0]
Notes
1
2
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Default
4
5
8
10
16
20
32
40
80
Table 2. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80
With PH0[4:0] = 00000
PH1
Divide
Ratio
Phase Lead
(radian)
[4]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
[3]
X
X
X
X
X
X
X
0
[2]
X
X
X
0
[1]
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes
5
0
0
Phase setting not available
10
(2π/2)
0
20
0
(2π/4)
2(2π/4)
3(2π/4)
0
1
1
40
0
0
0
(2π/8)
2(2π/8)
3(2π/8)
4(2π/8)
5(2π/8)
6(2π/8)
7(2π/8)
0
1
0
1
1
0
1
0
1
1
1
1
14
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CDCL1810
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SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
Table 2. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80 (continued)
With PH0[4:0] = 00000
PH1
[2]
0
Divide
Ratio
Phase Lead
(radian)
[4]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
[3]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
[1]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes
80
0
0
(2π/16)
1
2(2π/16)
3(2π/16)
4(2π/16)
5(2π/16)
6(2π/16)
7(2π/16)
8(2π/16)
9(2π/16)
10(2π/16)
11(2π/16)
12(2π/16)
13(2π/16)
14(2π/16)
15(2π/16)
1
0
0
1
1
0
0
1
1
0
0
1
1
15
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CDCL1810
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SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
Table 3. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32
With PH0[4:0] = 00000
PH1
Divide
Ratio
Phase Lead
(radian)
[4]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
[3]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
[2]
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
[1]
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
[0]
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes
1
2
0
0
00000: Default Phase setting not available
(2π/2)
4
0
(2π/4)
2(2π/4)
3(2π/4)
0
8
(2π/8)
2(2π/8)
3(2π/8)
4(2π/8)
5(2π/8)
6(2π/8)
7(2π/8)
0
16
0
(2π/16)
2(2π/16)
3(2π/16)
4(2π/16)
5(2π/16)
6(2π/16)
7(2π/16)
8(2π/16)
9(2π/16)
10(2π/16)
11(2π/16)
12(2π/16)
13(2π/16)
14(2π/16)
15(2π/16)
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16
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CDCL1810
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SLLS781A–FEBRUARY 2007–REVISED MARCH 2007
Table 3. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32 (continued)
With PH0[4:0] = 00000
PH1
[2]
0
Divide
Ratio
Phase Lead
(radian)
[4]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes
32
0
0
(2π/32)
0
2(2π/32)
0
3(2π/32)
1
4(2π/32)
1
5(2π/32)
1
6(2π/32)
1
7(2π/32)
0
8(2π/32)
0
9(2π/32)
0
10(2π/32)
11(2π/32)
12(2π/32)
13(2π/32)
14(2π/32)
15(2π/32)
16(2π/32)
17(2π/32)
18(2π/32)
19(2π/32)
20(2π/32)
21(2π/32)
22(2π/32)
23(2π/32)
24(2π/32)
25(2π/32)
26(2π/32)
27(2π/32)
28(2π/32)
29(2π/32)
30(2π/32)
31(2π/32)
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
17
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
CDCL1810RGZR
CDCL1810RGZRG4
CDCL1810RGZT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
48
48
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
QFN
QFN
RGZ
RGZ
RGZ
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
CDCL1810RGZTG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
TAI
TAI
Reel
Diameter Width
(mm)
Reel
A0 (mm)
7.3
B0 (mm)
7.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
CDCL1810RGZR
CDCL1810RGZT
RGZ
RGZ
48
48
330
16
12
12
16 PKGORN
T2TR-MS
P
330
16
7.3
7.3
1.5
16 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CDCL1810RGZR
CDCL1810RGZT
RGZ
RGZ
48
48
TAI
TAI
342.9
342.9
336.6
336.6
28.58
28.58
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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相关型号：
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