CDCM6208V2GRGZR [TI]
2:8 超低功耗、低抖动时钟发生器,引脚模式型号 V2G | RGZ | 48 | -40 to 85;型号: | CDCM6208V2GRGZR |
厂家: | TEXAS INSTRUMENTS |
描述: | 2:8 超低功耗、低抖动时钟发生器,引脚模式型号 V2G | RGZ | 48 | -40 to 85 时钟 外围集成电路 晶体 时钟发生器 |
文件: | 总89页 (文件大小:3418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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CDCM6208V2G
ZHCSF03 –MARCH 2016
CDCM6208V2G 具有小数分频器的 2:8 时钟发生器/抖动消除器
1 特性
2 应用
1
•
低功耗出色性能:
•
•
•
•
•
基带时钟(无线基础设施)
网络和数据通信
–
低噪声合成器(265 fs-ms 典型抖动)或者低噪
声抖动清除器(1.6 ps-ms 典型抖动)
Keystone C66x 多核数字信号处理器 (DSP) 时钟
存储服务器、便携式测试设备、
医疗成像、高端 A/V
–
–
–
0.5W 典型功耗
高度通道到通道隔离和出色电源抑制比 (PSRR)
通过灵活的 1.8V,2.5V 和 3.3V 电源,可定制
器件性能,从而实现混合输出电压
3 说明
•
灵活的频率规划:
CDCM6208V2G 是一款多用途、低抖动低功耗频率合
成器,此频率合成器能够利用特有低频晶振或 CML、
LVPECL、LVDS 或 LVCMOS 信号的两路输入之一来
生成八路低抖动时钟输出(输出可在类似于 LVPECL
的高摆幅 CML、正常摆幅 CML、类似于 LVDS 的低
功耗 CML、HCSL 或 LVCMOS 中进行选择),广泛
适用于各类无线基础设施基带、有线数据通信、计算、
低功耗医疗成像以及便携式测试和测量应用。 应用。
另外,CDCM6208V2G 还 特有 一种用于其中四路输
出的创新型小数分频器架构,能够生成精度高于 1ppm
的任意频率。CDCM6208V2G 可通过 I2C 或串行外设
接口 (SPI) 编程接口轻松配置。在没有串行接口的情况
下,器件还可以利用自身提供的引脚模式通过控制引脚
设置为 32 种不同预编程配置中的一种。
–
–
–
–
支持与低压正射极耦合逻辑 (LVPECL) 相似
的、CML、或者与低压差分信号 (LVDS) 相似的
信令的 4x 整数向下分频差分时钟输出
支持主机时钟信号电平 (HCSL),与 LVDS 相似
的信令、或者 8 个 CMOS 输出的 4x 小数或者
整数分频差分时钟输出
小数输出分频器可实现 0ppm 至 <1ppm 的频率
误差并且免除了对于晶体振荡器和其它是时钟生
成器的需要
输出频率高达 800MHz
•
•
•
两个差分输入、XTAL 支持、智能开关功能
SPI, I2C™,和引脚可编程
用于快速设计周转时间的专业用户图形用户界面
(GUI)
•
•
7 x 7mm 48 引脚四方扁平无引线 (QFN) 封装
(RGZ)
器件信息(1)
器件型号
封装
封装尺寸(标称值)
-40 °C 85 °C 温度范围
CDCM6208V2G
VQFN (48)
7.00mm x 7.00mm
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
4 简化电路原理图
Timing
FBADC
RXADC
Core
SyncE
TXDAC
DR
Packet PCIe
Accel
Packet
1pps
GPS receiver
network
RF LO
CDCM6208
DPLL
APLL
IEEE1588
timing extract
1pps
RF LO
CDCM6208
Synthesizer
Mode
Ethernet
TMS320TCI6616/18
DSP
Pico Cell Clocking
AIF
ALT
SRIO
CORE
Base Band DSP
Clocking
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS682
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
目录
Characteristics ......................................................... 15
8.20 Device Individual Block Current Consumption...... 16
8.21 Worst Case Current Consumption........................ 17
8.22 I2C TIMING .......................................................... 18
8.23 SPI Timing Requirements ..................................... 19
8.24 Typical Characteristics ......................................... 20
Parameter Measurement Information ................ 22
9.1 Characterization Test Setup ................................... 22
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
8.1 Absolute Maximum Ratings ..................................... 6
8.2 ESD Ratings.............................................................. 6
8.3 Recommended Operating Conditions....................... 7
8.4 Thermal Information, Airflow = 0 LFM ..................... 7
8.5 Thermal Information, Airflow = 150 LFM ................. 8
8.6 Thermal Information, Airflow = 250 LFM ................. 8
8.7 Thermal Information, Airflow = 500 LFM ................. 8
8.8 Single Ended Input Characteristics .......................... 9
9
10 Detailed Description ........................................... 28
10.1 Overview ............................................................... 28
10.2 Functional Block Diagram ..................................... 28
10.3 Feature Description............................................... 29
10.4 Device Functional Modes...................................... 30
10.5 Programming......................................................... 38
10.6 Register Maps....................................................... 42
11 Application and Implementation........................ 54
11.1 Application Information.......................................... 54
11.2 Typical Applications .............................................. 54
12 Power Supply Recommendations ..................... 73
8.9 Single Ended Input Characteristics (PRI_REF,
SEC_REF) ................................................................. 9
8.10 Differential Input Characteristics (PRI_REF,
SEC_REF) ............................................................... 10
12.1 Power Rail Sequencing, Power Supply Ramp Rate,
and Mixing Supply Domains .................................... 73
8.11 Crystal Input Characteristics (SEC_REF)............. 10
13 Layout................................................................... 75
13.1 Layout Guidelines ................................................. 75
13.2 Layout Example .................................................... 75
14 器件和文档支持 ..................................................... 81
14.1 文档支持 ............................................................... 81
14.2 社区资源................................................................ 81
14.3 商标....................................................................... 81
14.4 静电放电警告......................................................... 81
14.5 Glossary................................................................ 81
15 机械、封装和可订购信息....................................... 81
8.12 Single Ended Output Characteristics (STATUS1,
STATUS0, SDO, SDA) ............................................ 11
8.13 PLL Characteristics............................................... 11
8.14 LVCMOS Output Characteristics .......................... 12
8.15 LVPECL (High-Swing CML) Output
Characteristics ......................................................... 13
8.16 CML Output Characteristics.................................. 13
8.17 LVDS (Low-Power CML) Output Characteristics. 14
8.18 HCSL Output Characteristics............................... 14
8.19 Output Skew and Sync to Output Propagation Delay
5 修订历史记录
日期
修订版本
注释
2016 年 3 月
*
首次发布。
2
版权 © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
6 说明 (续)
在合成器模式中,使用整数分频器的输出的总体输出抖动性能少于 0.5 ps-rms (10k-20MHz) 或者的 20ps-pp(释放
的)并且根据预分频输出频率,使用分数分频器的输出的总体输出抖动性能介于 50 至 220 ps-pp (10k-40MHz)。
在抖动清除器模式中,使用整数分频器的输出的总体输出抖动少于 2.1 ps-rms (10k-20MHz) 或者 40 ps-pp,使用
分数分频器的输出的总体输出抖动少于 70ps 至 240 ps-pp。CDCM6208V2G 采用小型 48 引脚 7mm × 7mm QFN
封装。
7 Pin Configuration and Functions
RGZ Package
48 Pin VQFN
Top View
DVDD
SI_MODE0
1
2
36 Y7_N
35 Y7_P
SDI/SDA/PIN1
VDD_Y7
3
SDO/AD0/PIN2
SCS/AD1/PIN3
SCL/PIN4
34
33
32
31
30
29
4
Y6_N
5
Y6_P
REF_SEL
6
VDD_Y6
VDD_Y5
Y5_P
VDD_PRI_REF
7
8
PRI_REFP
PRI_REFN
9
28 Y5_N
27
VDD_SEC_REF
10
VDD_Y4
SEC_REFP 11
26 Y4_P
SEC_REFN
25
12
Y4_N
VDD_Y0_Y1
VDD_Y2_Y3
Pin Functions
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
8
PRI_REFP
PRI_REFN
Input
Input
Universal
Universal
Primary Reference Input +
Primary Reference Input –
9
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to
VDD_SEC_REF.
VDD_PRI_REF
7
PWR
Analog
SEC_REFP
SEC_REFN
11
12
Input
Input
Universal
Universal
Secondary Reference Input +
Secondary Reference Input –
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to
VDD_SEC_REF 10
PWR
Analog
VDD_PRI_REF(1)
.
(1) If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.
Copyright © 2016, Texas Instruments Incorporated
3
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference
selection is also controlled through Register 4 bit 12.
REF_SEL = 0 (≤ VIL): selects PRI_REF
REF_SEL = 1 (≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See Table 35 for
detail.
LVCMOS
50kΩ pull-up
REF_SEL
6
Input
ELF
41
14
15
17
16
Output
Output
Output
Output
Output
Analog
External loop filter pin for PLL
Output 0 Positive Terminal
Output 0 Negative Terminal
Output 1 Positive Terminal
Output 1 Negative Terminal
Y0_P
Y0_N
Y1_P
Y1_N
Universal
Universal
Universal
Universal
VDD_Y0_Y1 (2
pins)
13,
18
PWR
Analog
Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V
Y2_P
Y2_N
Y3_P
Y3_N
20
21
23
22
Output
Output
Output
Output
Universal
Universal
Universal
Universal
Output 2 Positive Terminal
Output 2 Negative Terminal
Output 3 Positive Terminal
Output 3 Negative Terminal
VDD_Y2_Y3 (2
pins)
19,
24
PWR
Analog
Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V
Y4_P
Y4_N
26
25
27
29
28
30
32
33
31
35
36
34
Output
Output
PWR
Universal
Universal
Analog
Output 4 Positive Terminal
Output 4 Negative Terminal
VDD_Y4
Y5_P
Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V
Output 5 Positive Terminal
Output
Output
PWR
Universal
Universal
Analog
Y5_N
Output 5 Negative Terminal
VDD_Y5
Y6_P
Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V
Output 6 Positive Terminal
Output
Output
PWR
Universal
Universal
Analog
Y6_N
Output 6 Negative Terminal
VDD_Y6
Y7_P
Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V
Output 7 Positive Terminal
Output
Output
PWR
Universal
Universal
Analog
Y7_N
Output 7 Negative Terminal
VDD_Y7
Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V
Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The
supply of this pin and the VDD_PLL2 supply pin can be combined as they are both
analog and sensitive supplies
VDD_VCO
VDD_PLL1
VDD_PLL2
39
37
38
PWR
PWR
PWR
Analog
Analog
Analog
Analog Power Supply Connections
Analog Power Supply Connections; This pin is sensitive to power supply noise; The
supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both
power-sensitive, analog supply pins
Digital Power Supply Connections; This is also the reference supply voltage for all
control inputs and must match the expected input signal swing of control inputs.
DVDD
48
PWR
Analog
GND
PAD
46
PWR
Analog
Power Supply Ground and Thermal Pad
STATUS0
Output
LVCMOS
Status pin 0 (see Table 6 for details)
STATUS1: Status pin in SPI/I2C modes. For details see Table 4 for pin modes and
Table 6 for status mode.
PIN0: Control pin 0 in pin mode.
Output/
Input
LVCMOS
no pull resistor
STATUS1/PIN0
45
LVCMOS
50kΩ pull-up
Serial Interface Mode or Pin mode selection.
SI_MODE[1:0]=00: SPI mode;
SI_MODE1
SI_MODE0
47
1
Input
Input
SI_MODE[1:0]=01: I2C mode;
LVCMOS
50kΩ pull-down
SI_MODE[1:0]=10: Pin Mode (No serial programming);
SI_MODE[1:0]=11: RESERVED
LVCMOS in
SDI: SPI Serial Data Input
Input/
Output
Open drain out SDA: I2C Serial Data (Read/Write bi-directional), open drain output; requires a pull-
SDI/SDA/PIN1
2
LVCMOS in
up resistor in I2C mode;
no pull resistor
PIN1: Control pin 1 in pin mode
4
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
LVCMOS out
LVCMOS in
LVCMOS in
SDO: SPI Serial Data
Output/
Input
SDO/AD0/PIN2
3
AD0: I2C Address Offset Bit 0 input
PIN2: Control pin 2 in pin mode
no pull resistor
SCS: SPI Latch Enable
LVCMOS
no pull resistor
SCS/AD1/PIN 3
SCL/PIN4
4
5
Input
Input
AD1: I2C Address Offset Bit 1 input
PIN3: Control pin 3 in pin mode
LVCMOS
no pull resistor
SCL: SPI/I2C Clock
PIN4: Control pin 4 in pin mode
In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed via SPI while
RESETN is held low (this is useful to avoid any false output frequencies at power
up).
In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1
= 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not
possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3
V.
LVCMOS
50kΩ pull-up
(2)
RESETN/PWR
44
Input
Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at
frequencies above 100 kHz
REG_CAP
PDN
40
43
42
Output
Input
Analog
Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the
device is disabled and current consumption minimized. Exiting power down resets
the entire device and defaults all registers. It is recommended to connect a capacitor
to GND to hold the device in power-down until the digital and PLL related power
supplies are stable. See section on power down in the application section.
LVCMOS
50kΩ pull-up
LVCMOS
50kΩ pull-up
Active low. Device outputs are synchronized on a low-to-high transition on the
SYNCN pin. SYNCN held low disables all outputs.
SYNCN
Input
(2) Note: the device cannot be programmed in I2C while RESETN is held low.
Copyright © 2016, Texas Instruments Incorporated
5
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD
-0.5
4.6
V
4.6
and
V DVDD+ 0.5
Input Voltage Range CMOS control inputs, VIN
Input Voltage Range PRI/SEC inputs
-0.5
-0.5
-65
V
V
4.6
and
VVDDPRI.SEC+ 0.5
Output Voltage Range, VOUT
Input Current, IIN
VYxYy+ 0.5
V
20
50
mA
mA
°C
Output Current, IOUT
Junction Temperature, TJ
Storage temperature range, Tstg
125
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD_Yx_Yy
Output Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PLL1
VDD_PLL2
Core Analog Supply Voltage
1.71
1.71
1.71
1.8/2.5/3.3
1.8/2.5/3.3
1.8/2.5/3.3
3.465
3.465
3.465
V
V
V
DVDD
Core Digital Supply Voltage
VDD_PRI,
VDD_SEC
Reference Input Supply Voltage
VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight
together PDN low-high is delayed
ΔVDD/Δt
50 < tPDN
85
ms
°C
(1)
TA
Ambient Temperature
-40
SDA and SCL in I 2 C MODE (SI_MODE[1:0] = 01)
DVDD = 1.8 V
–0.5
–0.5
2.45
V
V
VI
Input Voltage
Data Rate
DVDD = 3.3 V
3.965
100
400
dR
kbps
V
0.7 x
DVDD
VIH
High-level input voltage
VIL
Low-level input voltage
0.3 x DVDD
400
V
CBUS_I2C
Total capacitive load for each bus line
pF
(1) For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.
For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,
VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly
Figure 57 for details.
8.4 Thermal Information, Airflow = 0 LFM(1) (2) (3) (4)
CDCM6208
THERMAL METRIC(1)
RGZ
48 PINS VQFN
30.27
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
16.58
6.83
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.23
ψJB
6.8
RθJC(bot)
1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
Copyright © 2016, Texas Instruments Incorporated
7
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
8.5 Thermal Information, Airflow = 150 LFM(1) (2) (3) (4)
CDCM6208
RGZ
THERMAL METRIC(1)
UNIT
48 PINS
21.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
6.61
0.37
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
8.6 Thermal Information, Airflow = 250 LFM(1) (2) (3) (4)
CDCM6208
THERMAL METRIC(1)
RGZ
48 PINS
19.5
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.45
ψJB
RθJC(bot)
1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
8.7 Thermal Information, Airflow = 500 LFM(1) (2) (3) (4)
CDCM6208
THERMAL METRIC(1)
RGZ
48 PINS
17.7
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
6.58
0.58
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
1.05
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
8
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
8.8 Single Ended Input Characteristics
(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN,
SYNCN, REF_SEL), DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = –40°C to 85°C
PARAMETER
Input High Voltage
Input Low Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
0.8 x DVDD
V
0.2 x DVDD
V
DVDD = 3.465V, VIH = 3.465 V (pull-up
resistor excluded)
IIH
Input High Current
Input Low Current
30
µA
µA
IIL
DVDD = 3.465V, VIL= 0 V
20% - 80%
-30
PDN, RESETN, SYNCN, REF_SEL Input
Edge Rate
ΔV/ΔT
0.75
10
V/ns
PDN, RESETN, SYNCN low pulse to
trigger proper device reset
minPulse
C IN
ns
Input Capacitance
2.25
50
pF
RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]:
Input Pullup and Pulldown Resistor
SDA and SCL in I 2 C Mode (SI_MODE[1:0]=01)
R
35
65
kΩ
DVDD = 1.8 V
DVDD = 2.5/3.3 V
VI = DVDD
0.1 VDVDD
0.05 VDVDD
–5
V
V
VHYS_I2C
Input hysteresis
IH
High-level input current
Output Low Voltage
5
0.2 x DVDD
5
µA
V
VOL
CIN
IOL= 3mA
Input Capacitance terminal
pF
8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
0.008
0.008
TYP
MAX
200
UNIT
MHz
MHz
VDD_PRI/SEC = 1.8 V
Reference and Bypass Input
Frequency
fIN
VDD_PRI/SEC = 3.3 V
250
0.8 x
VDD_PRI/V
DD_SEC
VIH
Input High Voltage
Input Low Voltage
V
V
0.2 x
VDD_PRI/V
DD_SEC
VIL
VHYST
IIH
Input hysteresis
20
65
150
30
mV
µA
Input High Current
Input Low Current
VDD_PRI/VDD_SEC = 3.465 V, VIH = 3.465 V
VDD_PRI/VDD_SEC = 3.465 V, VIL = 0 V
20% - 80%
IIL
-30
µA
ΔV/ΔT
Reference Input Edge Rate
0.75
40%
43%
V/ns
f
PRI ≤ 200MHz
60%
60%
IDC SE
CIN
Reference Input Duty Cycle
Input Capacitance
200 ≤ fPRI ≤ 250 MHz
2.25
pF
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8.10 Differential Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
0.008
0.2
TYP
MAX
UNIT
MHz
VPP
fIN
VI
Reference and Bypass Input Frequency
250
1.6
1
VDD_PRI/SEC = 2.5/3.3 V
VDD_PRI/SEC = 1.8 V
Differential Input Voltage Swing, Peak-to-
Peak
0.2
VPP
VDD_PRI/V
DD_SEC-
0.4
VDD_PRI/V
DD_SEC-
0.1
VICM
Input Common Mode Voltage
CML input signaling, R4[7:6] = 00
V
V
LVDS, VDD_PRI/SEC
= 1.8/2.5/3.3 V,
R4[7:6] = 01, R4.1 = d.c.,
R4.0 = d.c.
VICM
Input Common Mode Voltage
Input hysteresis
0.8
1.2
1.5
LVDS (Q4[7:6,4:3] = 01)
15
20
65
85
mVpp
mVpp
µA
VHYST
CML (Q4[7:6,4:3] = 00)
IIH
Input High Current
VDD_PRI/SEC = 3.465 V, VIH = 3.465 V
VDD_PRI/SEC = 3.465V, VIL = 0 V
20% - 80%
30
IIL
Input Low Current
-30
µA
ΔV/ΔT
IDCDIFF
CIN
Reference Input Edge Rate
Reference Input Duty Cycle
Input Capacitance
0.75
30%
V/ns
70%
2.7
pF
8.11 Crystal Input Characteristics (SEC_REF)
VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V,TA = –40°C to 85°C
PARAMETER
MODE OF OSCILLATION
MIN
TYP
MAX
UNIT
FUNDAMENTAL
10
(1)
(2)
See note
See note
10 MHz
25 MHz
50 MHz
30.72
50
150(3)
70(4)
30(5)
5.5
MHz
MHz
Frequency
30.73
Equivalent Series Resistance (ESR)
Ω
1.8 V / 3.3 V SEC_REFP
1.8 V SEC_REFN
3.5
5.5
6.5
4.5
7.25
7.34
On-chip load capacitance
Drive Level
8.5
pF
3.3 V SEC_REFN
8.5
(6)
See note
200
µW
(1) Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and
completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00A-
CG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA
30.72MHz EXS00A-CG02812 CRG.
(2) For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal
vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the
best choice of the XTAL was one with CL = 7pF instead of CL = 8pF.
(3) With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin)
(4) With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin)
(5) With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin)
(6) Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW
10
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
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ZHCSF03 –MARCH 2016
8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V;
TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Status 1, Status 0, and SDO only;
SDA is open drain and relies on
external pullup for high output; IOH
1 mA
0.8 x
DVDD
VOH
Output High Voltage
V
=
0.2 x
DVDD
VOL
Output Low Voltage
IOL = 1 mA
V
Vslew
IOZH
IOZL
Output slew rate
30% - 70%
0.5
V/ns
µA
3-stat Output High Current
3-stat Output Low Current
DVDD = 3.465 V, VIH = 3.465 V
DVDD = 3.465 V, VIL = 0 V
5
-5
µA
Status Loss of Signal Detection
Time
tLOS
LOS_REFfvco
1
2
1/f PFD
1/f PFD
Detect lock
2304
512
tLOCK
Status PLL Lock Detection Time
Detect unlock
8.13 PLL Characteristics
VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fVCO
VCO Frequency Range
2.39
2.55
GHz
2.39 GHz
178
204
213
KVCO
VCO Gain
2.50 GHz
2.55 GHz
MHz/V
fPFD
PFD Input Frequency
0.008
100
MHz
nA
High Impedance Mode Charge
Pump Leakage
ICP-L
±700
–224
Measured in-band phase noise at
the VCO output minus 20log(N-
divider) at the flat region
Estimated PLL Figure of Merit
(FOM)
fFOM
dBc/Hz
Power supply ramp time of 1ms from
0 V to 1.7 V, final frequency
accuracy of 10 ppm, fPFD = 25 MHz,
CPDN_to_GND = 22nF
tSTARTUP
Startup time (see Figure 41 )
w/ PRI input signal
12.8
ms
ms
w/ NDK 25 MHz crystal
12.85
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8.14 LVCMOS Output Characteristics
VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
TEST CONDITIONS
Fract Out divVDD_Yx_Yy = 2.5/3.3 V
Integer out divVDD_Yx_Yy = 2.5/3.3 V
Int or frac out divVDD_Yx_Yy = 1.8 V
Fractional Output Divider
MIN
TYP
MAX
UNIT
0.78
250
250
200
1
fOUT-F
Output Frequency
1.55
MHz
0.78/1.5
–1
(1)
fACC-F
VOH
Output Frequency Error
ppm
V
0.8 x
VDD_Yx_Yy
Output High Voltage (normal mode)
Output Low Voltage(normal mode)
Output High Voltage (slow mode)
Output Low Voltage(slow mode)
VDD_Yx = min to max, IOH = -1 mA
VDD_Yx = min to max, IOL = 100 µA
VDD_Yx = min to max, IOH = -100 µA
VDD_Yx = min to max, IOL = 100 µA
0.2 x
VDD_Yx_Yy
VOL
VOH
VOL
V
V
V
0.7 x
VDD_Yx_Yy
0.3 x
VDD_Yx_Yy
V OUT = VDD_Yx_Yy/2
Normal mode
IOH
Output High Current
Output Low Current
–50
–45
-8
-5
mA
mA
Slow mode
V OUT = VDD_Yx_Yy/2
Normal mode
IOL
10
5
55
40
mA
mA
Slow mode
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF
Output Rise/Fall Slew Rate (normal
mode)
5.37
2.62
4.17
V/ns
V/ns
V/ns
tSLEW-RATE-N
20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF
Output Rise/Fall Slew Rate (normal
mode)
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF
Output Rise/Fall Slew Rate (slow
mode)
tSLEW-RATE-S
20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF
Output Rise/Fall Slew Rate (slow
mode)
1.46
V/ns
PN-floor
ODC
Phase Noise Floor
Output Duty Cycle
fOUT = 122.88 MHz
Not in bypass mode
V OUT = VDD_Yx/2
–159.5
–154
55%
dBc/Hz
45%
ROUT
Output Impedance
Normal mode
Slow mode
30
45
50
74
90
130
Ω
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple 1 over 220, the actual output frequency error is 0.
Note: In LVCMOS Mode, positive and negative outputs are in phase.
12
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF03 –MARCH 2016
8.15 LVPECL (High-Swing CML) Output Characteristics
VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625
V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT-I
Output frequency
Integer Output Divider
1.55
800
MHz
VDD_Yx
_
Yy – 0.4
Output DC coupled common mode
voltage
VCM-DC
DC coupled with 50 Ω external termination to VDD_Yx_Yy
V
100 Ω diff load AC coupling (See Figure 11), fOUT ≤ 250 MHz
VDD_Yx_Yy ≤ 1.89 V
0.45
0.6
0.75
0.8
1.12
1.12
V
V
VDD_Yx_Yy ≥ 2.375 V
|VOD
|
Differential output voltage
100 Ω diff load AC coupling (See Figure 11), fOUT ≥ 250 MHz
VDD_Yx_Yy ≤ 1.89 V
0.73
0.75
V
V
VDD_Yx_Yy ≥ 2.375 V
0.55
1.12
Differential output peak-to-peak
voltage
VOUT
2 x |VOD
|
V
±200 mV around crossing point
20% to 80% VOD
109
3.7
217
7.3
ps
ps
tR/tF
tslew
Output rise/fall time
211
5.1
Output rise/fall slew rate
V/ns
dBc/Hz
PN-floor Phase noise floor
VDD_Yx_Yy = 3.3 V (See Figure 53)
Not in bypass mode
–161.4 –155.8
ODC
ROUT
Output duty cycle
Output impedance
47.5%
52.5%
50
measured from pin to VDD_Yx_Yy
Ω
8.16 CML Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V,
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fOUT-I
Output frequency
Integer Output Divider
1.55
800
MHz
V
Output AC coupled common
mode voltage
VCM-AC
AC coupled with 50 Ω receiver termination
VDD_Yx_Yy – 0.46
DC coupled with 50 Ω on-chip termination
to VDD_Yx_Yy
Output DC coupled common
mode voltage
VCM-DC
VDD_Yx_Yy – 0.2
0.45
V
V
V
|VOD
|
Differential output voltage
100 Ω diff load AC coupling, (See Figure 11)
0.3
0.58
Differential output peak-to-peak
voltage
VOUT
2 x |VOD
|
VDDYx = 1.8 V
20% to 80%
100
100
151
143
300
200
ps
ps
tR/tF
Output rise/fall time
VDDYx = 2.5 V/3.3 V
VDD_Yx_Yy = 1.8 V
–161.2
–161.2
–155.8 dBc/Hz
–153.8 dBc/Hz
52.5%
PN-floor
Phase noise floor at > 5 Hz offset fOUT = 122.88 MHz
VDD_Yx_Yy = 3.3 V
ODC
ROUT
Output duty cycle
Output impedance
Not in bypass mode
measured from pin to VDD_Yx_Yy
47.5%
50
Ω
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8.17 LVDS (Low-Power CML) Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to
3.465V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
1.55
0.78
-1
TYP
MAX
400
400
1
UNIT
MHz
MHz
ppm
fOUT-I
fOUT-F
fACC-F
Integer output divider
Output frequency
Fractional output divider
Fractional output divider
(1)
Output frequency error
Output AC coupled
common mode voltage
VCM-AC
VCM-DC
|VOD
AC coupled with 50 Ω receiver termination
VDD_Yx_Yy – 0.76
V
Output DC coupled
common mode voltage
DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy
VDD_Yx_Yy – 0.13
0.34
V
V
|
Differential output voltage 100 Ω diff load AC coupling, (See Figure 11)
0.247
0.454
300
Differential output peak-to-
peak voltage
VOUT
tR/tF
2 x |VOD
|
V
Output rise/fall time
±100mV around crossing point
ps
VDD_Yx = 1.8 V
–159.3
–159.1
–154.5 dBc/Hz
PN-floor
Phase noise floor
fOUT= 122.88 MHz
VDD_Yx = 2.5/3.3 V
Y[3:0]
–154.9 dBc/Hz
47.5%
45%
52.5%
55%
Ω
ODC
ROUT
Output duty cycle
Output impedance
Not in bypass mode
Y[7:4]
Measured from pin to VDD_Yx_Yy
167
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple of 1 over 220, the actual output frequency error is 0.
8.18 HCSL Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V,
TA = –40°C to 85°C
PARAMETER
Output frequency
Output Frequency Error
TEST CONDITIONS
Integer Output Divider
MIN
1.55
0.78
-1
TYP
MAX UNIT
fOUT-I
fOUT-F
fACC-F
400
400
1
MHz
MHz
ppm
V
Fractional Output Divider
Fractional Output Divider
VDD_Yx_Yy = 2.5/3.3 V
VDD_Yx_Yy = 1.8 V
(1)
0.2
0.2
0.4
0.4
1.0
0.34
0.33
0.67
0.65
0.55
0.55
1.0
VCM
Output Common Mode Voltage
Differential Output Voltage
V
VDD_Yx_Yy = 2.5/3.3 V
VDD_Yx_Yy = 1.8 V
V
|VOD
|
1.0
V
VDD_Yx_Yy = 2.5/3.3 V
VDD_Yx_Yy = 1.8 V
2.1
V
Differential Output Peak-to-peak
Voltage
VOUT
2 x|VOD
|
V
Measured from VDIFF= –100 mV to
VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V
100
120
167
192
250
295
tR/tF
Output Rise/Fall Time
ps
Measured from VDIFF= –100 mV to
VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V
VDD_Yx_Yy = 1.8 V
fOUT = 122.88 MHz
–158.8
–157.6
–153 dBc/Hz
–153 dBc/Hz
55%
PN-floor
ODC
Phase Noise Floor
Output Duty Cycle
VDD_Yx = 2.5/3.3 V
Not in bypass mode
45%
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of A 1/220 multiple, the actual output frequency error is 0.
14
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ZHCSF03 –MARCH 2016
8.19 Output Skew and Sync to Output Propagation Delay Characteristics
VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
PS_A = 4
MIN TYP MAX UNIT
9
9
9
10.5
10.2
10.0
11 1/fPS_A
11 1/fPS_A
11 1/fPS_A
Propagation delay SYNCN↑ to output
toggling high
tPD-PS
f VCO = 2.5 GHz
PS_A = 5
PS_A = 6
Part-to-Part Propagation delay
ΔtPD-PS
variation SYNCN↑ to output toggling Fixed supply voltage, temp, and device setting(1)
0
1 1/f PS_A
high(1)
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,LVDS
tSK,LVDS
tSK,LVDS
tSK,CML
tSK,PECL
tSK,HCSL
tSK,SE
Skew between Y[7:4] LVDS
Skew between Y[3:0] LVDS
Skew between Y[7:0] LVDS
Skew between Y[3:0] CML
Skew between Y[3:0] PECL
Skew between Y[7:4] HCSL
Skew between Y[7:4] CMOS
Y[7:4] = LVDS
Y[3:0] = LVDS
Y[7:0] = LVDS
Y[3:0] = CML
40
40
80
40
40
40
50
ps
ps
ps
ps
ps
ps
ps
Y[3:0] = LVPECL
Y[7:4] = HCSL
Y[7:4] = CMOS
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
Skew between Y[7:4] LVDS and
CMOS mixed
tSK,CMOS-LVDS
tSK,CMOS-PECL
tSK,PECL-LVDS
tSK,PECL-CML
tSK,LVDS-PECL
tSK,LVDS-HCSL
Y[4] = CMOS, Y[7:5] = LVDS
Y[7:4] = CMOS, Y[3:0] = LVPECL
Y[0] = LVPECL, Y[3:1] = LVDS
Y[0] = LVPECL, Y[3:1] = CML
Y[7:4] = LVDS, Y[3:0] = LVPECL
Y[4] = LVDS, Y[7:5] = HCSL
2.5
2.5
ns
ns
ps
ps
ps
ps
Skew between Y[7:0] CMOS and
LVPECL mixed
Skew between Y[3:0] LVPECL and
LVDS mixed
120
40
Skew between Y[3:0] LVPECL and
CML mixed
Skew between Y[7:0] LVDS and
LVPECL mixed
180
250
Skew between Y[7:4] LVDS and
HCSL mixed
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125
Skew between Y[7:4] LVDS using all
tSK,DIFF, frac
fractional divider with the same
divider setting
Y[7:4] = LVDS
200
ps
(1) SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).
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8.20 Device Individual Block Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output
Types = LVPECL/CML/LVDS/LVCMOS/HCSL
BLOCK
CONDITION
TYPICAL CURRENT CONSUMPTION (mA)
Core
CDCM6208V2G Core, active mode, PS_A = PS_B = 4
CML output, AC coupled w/ 100 Ω diff load
LVPECL, AC coupled w/ 100 Ω diff load
75
24.25
40
LVCMOS output, transient, 'C L' load, 'f' MHz output
frequency, 'V' output swing
Output Buffer
1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3
LVDS output, AC coupled w/ 100 Ω diff load
HCSL output, 50 Ω load to GND on each output pin
Integer Divider Bypass (Divide = 1)
19.7
31
3
Integer Divide Enabled, Divide > 1
8
Output Divide Circuitry
Fractional Divider Enabled
12
15
additional current when PS_A differs from PS_B
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
(excl. I termination_resistors
)
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
(1.8 V: 251 mA
2.5 V: 254 mA
3.3 V: 257 mA)
Total Device, CDCM6208V2G
(incl. I termination_resistors
)
(1.8 V: 310 mA
2.5 V: 313 mA
11. Output divider ratio = 5
3.3 V: 316 mA)
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384 MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz,
125 MHz, 50 MHz)
Total Device, CDCM6208V2G Power Down (PDN = '0')
0.35
Helpful Note: The CDCM6208V2G User GUI does an excellent job estimating the total device current
consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate
device power consumption.
16
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8.21 Worst Case Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA = T-40°C to 85°C, Output Types = maximum
swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation
BLOCK
CONDITION
CURRENT CONSUMPTION
TYP / MAX
All conditions over PVT, AC coupled outputs with all outputs
terminated, device configuration:
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
1.8 V: 310 mA / +21% (excl term)
3.3 V: 318 mA / +21% (excl term)
Total Device, CDCM6208V2G
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
11. Output divider ratio = 5
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384 MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125
MHz, 50 MHz)
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UNIT
8.22 I2C TIMING(1)
PARAMETER
STANDARD MODE
FAST MODE
MIN MAX
MIN
0
MAX
fSCL
SCL Clock Frequency
100
0
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
tsu(START)
th(START)
tw(SCLL)
tw(SCLH)
th(SDA)
tsu(SDA)
tr-in
START Setup Time (SCL high before SDA low)
START Hold Time (SCL low after SDA low)
SCL Low-pulse duration
4.7
4.0
4.7
4.0
0.6
0.6
1.3
0.6
0
SCL High-pulse duration
(2)
SDA Hold Time (SDA valid after SCL low)
SDA Setup Time
0
3.45
0.9
250
100
SCL / SDA input rise time
1000
300
300
300
250
tf-in
SCL / SDA input fall time
tf-out
SDA Output fall time from VIH min to VIL max with a bus
capacitance from 10 pF to 400 pF
250
tsu(STOP)
tBUS
STOP Setup Time
4.0
4.7
75
0.6
1.3
75
μs
μs
ns
Bus free time between a STOP and START condition
Pulse width of spikes suppressed by the input glitch filter
tglitch_filter
300
300
(1) For additional information, refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208V2G meets the switching
characteristics for standard mode and fast mode transfer.
(2) The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge
of SCL.
t4
t5
t1
SCL
SDI
t2
t3
A31
A30
D1
D0
DON‘T CARE
t6
SDO
tri-state
D15
D1
D0
DON‘T CARE
t7
SCS
t8
Figure 1. CDCM6208V2G SPI Port Timing
18
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8.23 SPI Timing Requirements
PARAMETER
MIN
NOM
MAX
UNIT
MHz
ns
fClock
t1
Clock Frequency for the SCL
SPI_LE to SCL setup time
SDI to SCL setup time
SDO to SCL hold time
SCL high duration
20
10
10
10
25
25
10
20
10
t2
ns
t3
ns
t4
ns
t5
SCL low duration
ns
t6
SCL to SCS Setup time
SCS Pulse Width
ns
t7
ns
t8
SDI to SCL Data Valid (First Valid Bit after SCS)
ns
ACK
STOP
STOP
START
tr(SM)
tf(SM)
tW(SCLL) tW(SCLH)
VIH(SM)
VIL(SM)
SCL
th(START)
tSU(START)
tBUS
tSU(SDATA)
tr(SM)
th(SDATA)
tSU(STOP)
tf(SM)
VIH(SM)
VIL(SM)
SDA
Figure 2. I2C Timing Diagram
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8.24 Typical Characteristics
Using Divide by x.73 Example
fFRAC = 300 MHz
Figure 4. Fractional Divider Input Frequency Impact on Jitter
Figure 3. Fractional Divider Bit Selection Impact on Jitter
200
180
200 ps-pp
all zero, (0) typ
MSB, (1/2) typ
180 ps-pp
MSB-1, (1/4) typ
MSB-9, (1/1024) max
160
160 ps-pp
140 ps-pp
120 ps-pp
100 ps-pp
80 ps-pp
60 ps-pp
40 ps-pp
20 ps-pp
0 ps-pp
MSB-2, (1/8) typ
MSB-3, (1/16) typ
MSB-4, (1/32) typ
MSB-5, (1/54) typ
MSB-6, (1/128) typ
MSB-9, (1/1024) typ
140
MSB-4, (1/32) max
120
100
80
60
40
20
0
MSB-13, (1/16384) max
MSB-13, (1/16384) typ
LSB, (1/1048576) max
LSB, (1/1048576) typ
MSB, (1/2) max
MSB-7, (1/256) typ
MSB-9, (1/1024) typ
MSB-13, (1/16384) typ
LSB, (1/1048576) typ
0x50A33D (÷x.315) typ
0x828F5 (÷x.51) typ
0xBAE14 (÷x.73) typ
MSB, (1/2) typ
all zero, (0) max
200 220 240 260 280 300 320 340 360 380 400
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
Figure 6. Fractional Divider Bit Selection Impact on TJ
(Maximum Jitter Across Process, Voltage & Temperature)
Figure 5. Fractional Divider Bit Selection Impact on TJ
(Typical)
-50
-55
9.2 ps
-60
-65
2.9 ps
-70
-75
-80
-85
0.92 ps
0.29 ps
-90
-95
0.092 ps
-100
100
1000
10K
100k
1M
10M
Frequency (Hz)
f OUT = 122 MHz
Figure 7. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format
20
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8.24.1 Fractional Output Divider Jitter Performance
The fractional output divider jitter performance is a function of the fraction output divider input frequency as well
as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least
number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 3, the
largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in
the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a
time window of 200 ms. The RJ impact on TJ is estimated for a BERT 10(–12) – 1. This measurement result is
overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW
limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.
8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
See Figure 7 for reference.
Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify
design and cost, the CDCM6208V2G has built in internal voltage regulation, improving the power supply noise
rejection over designs with no regulators. As a result, the following output rejection is achieved:
The DJ due to PSRR can be estimated using Equation 1:
2 x 10(spur/20)
p x f
Deterministic Jitter (ps ) =
x 10-12
p-p
CLK
(1)
Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the
according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.
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9 Parameter Measurement Information
9.1 Characterization Test Setup
This section describes the characterization test setup of each block in the CDCM6208V2G.
High impedance probe
LVCMOS
CDCM6208
Oscilloscope
5pF
Figure 8. LVCMOS Output AC Configuration During Device Test (VOH, VOL, tSLEW
)
High impedance probe
LVCMOS
CDCM6208
Oscilloscope
1mA
High impedance probe
VDD_Yx
1mA
CDCM6208
Oscilloscope
LVCMOS
Figure 9. LVCMOS Output DC Configuration During Device Test
Phase Noise/
Spectrum
LVCMOS
CDCM6208
50ꢀ
Analyzer
Figure 10. LVCMOS Output AC Configuration During Device Phase Noise Test
22
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Characterization Test Setup (continued)
YP
YN
50O
CDCM6208
50ꢀ
50ꢀ
Phase Noise/
Spectrum
Analyzer
Set to one of the following signaling
levels: LVPECL, CML, LVDS
50ꢀ Balun
Figure 11. LVDS, CML, and LVPECL Output AC Configuration During Device Test
High impedance differential probe
HCSL
CDCM6208
Oscilloscope
HCSL
50 ꢀ
50 ꢀ
Figure 12. HCSL Output DC Configuration During Device Test
HCSL
Phase Noise/
Balun
Spectrum
CDCM6208
HCSL
50 ꢀAnalyzer
50 ꢀ
50 ꢀ
Figure 13. HCSL Output AC Configuration During Device Test
Offset = VDD_PRI/SEC/2
LVCMOS
Signal
Generator
CDCM6208
50 ꢀ
Figure 14. LVCMOS Input DC Configuration During Device Test
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Characterization Test Setup (continued)
CML
CML
Signal
Generator
CDCM6208
50 ꢀ
50 ꢀ
VDD_PRI/SEC
Figure 15. CML Input DC Configuration During Device Test
LVDS
Signal
Generator
CDCM6208
100 ꢀ
LVDS
Figure 16. LVDS Input DC Configuration During Device Test
LVPECL
Signal
Generator
CDCM6208
LVPECL
50 ꢀ
50 ꢀ
VDD_PRI/SEC - 2
Figure 17. LVPECL Input DC Configuration During Device Test
VDD_PRI/SEC
100 ꢀ
100 ꢀ
Signal
Generator
Differential
CDCM6208
100 ꢀ
100 ꢀ
Figure 18. Differential Input AC Configuration During Device Test
24
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ZHCSF03 –MARCH 2016
Characterization Test Setup (continued)
Crystal
CDCM6208
Figure 19. Crystal Reference Input Configuration During Device Test
Sine wave
Modulator
Phase Noise/
Spectrum
Signal
Generator
Device Output
CDCM6208
Balun
50 ꢀAnalyzer
Reference
Input
50 ꢀ
50 ꢀ
Figure 20. Jitter transfer Test Setup
Sine wave
Modulator
Power Supply
Phase Noise/
Spectrum
Signal
Generator
CDCM6208
Device Output
Balun
50 ꢀAnalyzer
Reference
Input
50 ꢀ
50 ꢀ
Figure 21. PSNR Test Setup
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Characterization Test Setup (continued)
Yx_P
Yx_N
VOD
80%
0 V
VOUT,DIFF,PP = 2 x VOD
20%
tR
tF
Figure 22. Differential Output Voltage and Rise and Fall Time
80%
OUT_REFx/2
20%
VOUT,SE
tR
tF
Figure 23. Single Ended Output Voltage and Rise and Fall Time
26
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ZHCSF03 –MARCH 2016
Characterization Test Setup (continued)
VCXO_P
Single Ended
VCXO_P
VCXO_N
Differential
tPD,DIFF
Yx_P
Yx_N
Yx_P
Yx_N
Yx_P
Yx_N
Differential, Integer Divide
tSK,DIFF,INT
Differential, Integer Divide
tSK,DIFF,FRAC
Differential, Fractional Divide
tSK,SE-DIFF,INT
Single Ended, Integer Divide
Yx_P/N
Yx_P/N
tSK,SE,INT
tPD, SE
Single Ended, Integer Divide
tSK,SE,FRAC
Single Ended, Fractional Divide
Yx_P/N
Figure 24. Differential and Single Ended Output Skew and Propagation Delay
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10 Detailed Description
10.1 Overview
Supply Voltage: The CDCM6208V2G supply is internally regulated. Therefore each core and I/O supply can be
mixed and matched in any order according to the application needs. The device jitter performance is independent
of supply voltage.
Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and
VCO that operates from 2.39 GHz to 2.55 GHz.
Reference inputs: The primary and secondary reference inputs support differential and single ended signals from
8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is a 4-
bit reference divider available on the primary reference input. The input mux between the two references
supports simply switching or can be configured as Smart MUX and supports glitchless input switching.
Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the
output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent
prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then
be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an
output MUX. A total of 2 output MUXes are available.
Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz. The
charge pump gain is programmable and the loop filter consists of internal + partially external passive
components and supports bandwidths from a few Hz up to 400kHz.
10.2 Functional Block Diagram
REF_SEL
ELF
Y4
LVDS/
LVCMOS/
HCSL
Fractional Div
20-b
Y5
Y0
Y1
Y2
Y3
Fractional Div
20-b
Differential/
LVCMOS
Integer Div
8-b
PreScaler PS_A
÷4, ÷5, ÷6
R
4-b
PRI_REF
SEC_REF
M
14-b
LVPECL/
CML/
LVDS
Differential
LVCMOS/
XTAL
Φ
N
8-b,10-b
VCO:
(2.39-2.55) GHz
Integer Div
8-b
PreScaler PS_B
÷4, ÷5, ÷6
Fractional Div
20-b
Y6
Y7
Input
PLL
LVDS/
LVCMOS/
HCSL
Fractional Div
20-b
Control
Status/
Monitoring
Host
Interface
Power
Conditioning
Output
CDCM6208
Figure 25. High-Level Block Diagram of CDCM6208V2G
28
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ZHCSF03 –MARCH 2016
10.3 Feature Description
Phase Noise: The Phase Noise performance of the device can be summarized to:
Table 1. Synthesizer Mode (Loop filter BW >250 kHz)
RANDOM JITTER (ALL OUTPUTS)
TOTAL JITTER
MAXIMUM
Integer divider
DJ-unbound
RJ 10k-20MHz
TYPICAL
MAXIMUM
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
10k-20MHz
12k-20MHz
10k-100MHz
0.27 ps-rms (Integer division)
0.7ps-rms (fractional div)
50-220 ps-pp,
see Figure 3
(2)
0.3 ps-rms (int div)(1) 0.625 ps-rms (int div)
20 ps-pp
(1) Integrated Phase Noise (12kHz - 20 MHz) for 156.25 MHz output clock measured at room temperature using a 25 MHz Low Noise
reference source
(2) TJ = 20 pspp applies for LVPECL, CML, and LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over
PVT.
Table 2. Jitter Cleaner Mode (Loop filter BW < 1 kHz)
RANDOM JITTER (ALL OUTPUTS)
MAXIMUM
TOTAL JITTER
MAXIMUM
TYPICAL
Integer divider
DJ unbound
RJ 10k-20MHz
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
10k-20MHz
10k-20MHz
10k-100MHz
1.6 ps-rms (Integer division)
2.3 ps-rms (fractional div) 10k-20MHz
70-240 ps-pp,
see Figure 3
2.1 ps-rms (int div)
2.14 ps-rms (int div)
40 ps-pp
Spurious Performance: The spurious performance is as follows:
•
•
Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential
signaling level operated at 122.88 MHz output frequency in the Nyquist range.
Device outputs:
The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML),
low-swing CML (LVDS like), HCSL, and LVCMOS signaling.
Table 3. Device Outputs
FREQUENCY
Outputs
Y[3:0]
LVPECL
CML
LVDS
HCSL
LVCMOS
OUTPUT DIVIDER
RANGE
X
X
X
Integer only
Integer
1.55 - 800 MHz
1.55 - 800 MHz
1.00 - 400 MHz
Y[7:4]
X
X
X
Fractional
Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b
fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is
typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to
control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.
Device Configuration:32 distinct pin modes are available that cover many common use cases without the need
for any serial programming of the device. For maximum flexibility the device also supports SPI and I2C
programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.
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10G
PHY
PCIe
1G
PHY
DDR
CDCM6208
Synthesizer
Mode
DPLL
4x10G Ethernet ASIC
10G
PHY
10G
PHY
10G
PHY
10G
PHY
10GbE
Figure 26. Typical Use Case: CDCM6208V2G Example in Wireless Infrastructure Baseband Application
10.4 Device Functional Modes
10.4.1 Control Pins Definition
In the absence of a host interface, the CDCM6208V2G can be powered up in one of 32 pre-configured settings
when the pins are SI_MODE[1:0] = 10. The CDCM6208V2G has 5 control pins identified to achieve commonly
used networking frequencies, and change output types. The Smart Input MUX for the PLL is set in most
configurations to manual mode in pin mode. Based on the control pins settings for the on-chip PLL, the device
generates the appropriate frequencies and appropriate output signaling types at start-up. In the case of the PLL
loop filter, "JC" denotes PLL bandwidths of ≤ 1 kHz and "Synth" denotes PLL bandwidths of ≥ 100 kHz.
30
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Table 4. Pre-Configured Settings of CDCM6208V2G Accessible by PIN[4:0](1) (2)
Type
Type2
f(PFD) f(VCO)
SPI
Default
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
00
I/O
I/O
25
25
25
25
25
25
3000
3000
100
100
PECL
PECL
100
100
PECL
100
100
PECL
PECL
100
100
PECL
PECL
25
25
HCSL
HCSL
125
125
HCSL
HCSL
100
100
HCSL
HCSL
I2C
Default
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
01
11
10
PECL
RESERVED
PECL
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1-V2G
2-V2G
3-V2G
4-V2G
5-V2G
6-V2G
7-V2G
8-V2G
9-V2G
25
25
25
25
25
25
25
25
25
25
25
X
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
100
100
100
100
100
100
100
100
100
100
100
300
100
100
100
X
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
LVDS
CML
100
100
100
100
100
100
100
100
100
100
100
300
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
300
X
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
LVDS
Disable
Disable
Disable
Disable
100
100
100
100
100
100
100
100
100
100
100
X
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Disable
Disable
Disable
Disable
Disable
25
100
25
100
25
25
25
25
25
25
25
X
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
Disable
125
125
125
125
125
125
125
125
125
125
125
X
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
Disable
100
100
100
100
100
100
100
100
100
100
100
X
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
HCSL
Disable
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
LVDS
CML
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
HCSL
HCSL
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
10-
V2G
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
11-
V2G
LVCM
OS
LVCM
OS
MAN-
SEC
133.33
3333
LVCM
OS-P
12-
V2G
MAN-
SEC
Disable
Disable
Disable
Disable
Disable
Crystal
Crystal
Crystal
Crystal
Crystal
X
Disable
LVDS
13-
V2G
MAN-
SEC
LVCM
OS-PN
LVCM
OS-P
148.49
9954
LVCM
OS-PN
74.249
9773
X
X
25
25
25
X
50
14-
V2G
MAN-
SEC
LVCM
OS-PN
LVCM
OS-P
148.49
9954
LVCM
OS-PN
74.249
9773
X
CML
CML
X
X
50
LVDS
15-
V2G
MAN-
SEC
LVCM
OS-P
LVCM
OS-P
X
CML
CML
X
X
19.2
19.2
X
Disable
X
X
Disable
Disable
16-
V2G
MAN-
SEC
LVCM
OS-P
LVCM
OS-P
X
Disable
CML
X
X
Disable
32.768
(1) The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
(2) The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be "mixed and matched" as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8 V or 2.5/3.3 V supply. Exception: inputs configured
for LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44.
Copyright © 2016, Texas Instruments Incorporated
31
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
Table 4. Pre-Configured Settings of CDCM6208V2G Accessible by PIN[4:0](1) (2) (continued)
Type
Type2
f(PFD) f(VCO)
17-
V2G
MAN-
SEC
LVCM
OS-PN
LVCM
OS-P
148.49
9954
LVCM
OS-PN
74.499
LVDS
9874
10
10
10
10
10
10
10
10
10
10
10
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
X
Disable
Disable
Disable
Disable
Disable
Disable
Disable
25
25
25
25
25
25
25
25
25
Crystal
Crystal
Crystal
Crystal
Crystal
Crystal
Crystal
Crystal
25
25
3000
3000
3000
3000
3000
3000
3000
3125
3125
100
100
CML
CML
100
100
X
CML
CML
X
Disable
Disable
Disable
Disable
Disable
Disable
Disable
LVDS
X
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
LVDS
25
25
X
50
50
24
18-
V2G
MAN-
SEC
LVCM
OS-PN
LVCM
OS-P
148.49
9954
LVCM
OS-PN
74.499
LVDS
9874
X
X
X
X
19-
V2G
MAN-
SEC
LVCM
OS-P
X
X
25
100
CML
Disable
Disable
Disable
Disable
Disable
LVDS
X
Disable
X
Disable
X
X
Disable
Disable
Disable
Disable
Disable
LVDS
20-
V2G
MAN-
SEC
LVCM
OS-P
26.000 LVCM
846 OS-P
12.000
0117
LVCM
OS-P
25
100
CML
X
X
X
25
25
25
25
25
21-
V2G
MAN-
SEC
LVCM
OS-P
26.000 LVCM
846 OS-P
48.000
0468
X
25
X
Disable
CML
X
X
X
LVDS
X
22-
V2G
MAN-
SEC
LVCM
OS-P
26.000 LVCM
846 OS-P
12.000
0117
LVCM
OS-P
X
25
100
X
X
X
X
23-
V2G
MAN-
SEC
LVCM
OS-P
26.000 LVCM
48.000
0468
X
25
X
Disable
LVDS
LVDS
LVDS
LVDS
X
X
X
LVDS
LVDS
LVDS
LVDS
LVDS
X
846
OS-P
24-
V2G
LVCM
OS
MAN-
SEC
LVCM
OS-PN
25
6.25
6.25
35.328
35.328
156.25
156.25
52.992
52.992
156.25
156.25
52.992
52.992
156.25
156.25
52.992
52.992
X
X
100
LVDS
100
100
25-
V2G
LVCM
OS
MAN-
SEC
52.992
415
52.992
415
52.992
415
52.992
415
125
35.328
35.328
CML
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
26-
V2G
LVCM
OS
MAN-
SEC
2967.5
52
24.999
7799
LVCM
OS-PN
156.25
1195
156.25
1195
156.25
1195
35.328 Crystal
35.328 Crystal
LVDS
LVDS
X
LVDS
27-
V2G
LVCM
OS
MAN-
SEC
2967.5
52
24.999
7799
LVCM
OS-PN
156.25
1195
156.25
1195
156.25
1195
LVDS
LVDS
52.992
LVDS
24.999
Disable 779913
1236
28-
V2G
LVCM
OS
LVCM
MAN-
SEC
2967.5
52
LVCM
OS-PN
156.25
1195
156.25
1195
156.25
1195
10
0x1B
0.192
0.192
OS
0.192
52.992
LVDS
52.992
LVDS
52.992
LVDS
X
LVDS
LVDS
LVDS
29-
V2G
LVCM
OS
MAN-
SEC
LVCM
OS-P
LVCM
OS-PN
10
10
10
10
0x1C
0x1D
0x1E
0x1F
25
50
50
50
25
50
25
25
Crystal
Crystal
Crystal
Crystal
25
25
25
25
3125
3125
3125
3125
156.25
156.25
156.25
156.25
LVDS
LVDS
LVDS
LVDS
156.25
156.25
156.25
156.25
LVDS
LVDS
LVDS
LVDS
156.25
156.25
156.25
156.25
CML
CML
CML
CML
X
Disable
Disable
CML
X
Disable
125
125
125
125
200
200
200
200
LVDS
LVDS
LVDS
LVDS
25
25
25
25
30-
V2G
LVCM
OS
MAN-
SEC
LVCM
OS-P
LVCM
OS-P
LVCM
OS-PN
X
50
31-
V2G
LVCM
OS
MAN-
SEC
LVCM
OS-P
LVCM
OS-PN
156.25
156.25
156.25
156.25
HCSL
HCSL
32-
V2G
LVCM
OS
MAN-
SEC
LVCM
OS-P
LVCM
OS-PN
CML
32
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
10.4.2 Loop Filter Recommendations for Pin Modes
The following two tables provide the internal charge pump and R3/C3 settings for pin modes. The designer can
either design their own optimized loop filter, or use the suggested loop filter in the Table 5.
Table 5. CDCM6208V2G Loop Filter Recommendation for Pin Mode
Internal LPF
Components
PRI_REF
SEC_REF
Recommended
External LPF
Components
C1 / R2 / C2
f(PFD)
(MHz)
ICP
(mA)
Use Case
Freq
Freq
R3
C3
Type
Type
(MHz)
(MHz)
(Ω)
(pF)
SPI
Default
MAN-
SEC
00
I/O
I/O
25
25
LVCMOS
LVCMOS
25
25
LVCMOS
LVCMOS
25
25
2.5
2.5
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
100
100
242.5
242.5
I2C
Default
MAN-
SEC
01
11
10
RESERVED
MAN-
SEC
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
1-V2G
2-V2G
25
25
25
25
25
25
25
25
25
25
25
X
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Disable
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Crystal
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
6.25
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
4m
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
200pF / 400Ω / 22nF
22pF / 860Ω / 22nF
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
MAN-
SEC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
MAN-
SEC
3-V2G
MAN-
SEC
4-V2G
MAN-
SEC
5-V2G
MAN-
SEC
6-V2G
MAN-
SEC
7-V2G
MAN-
SEC
8-V2G
MAN-
SEC
9-V2G
MAN-
SEC
10-V2G
11-V2G
12-V2G
13-V2G
14-V2G
15-V2G
16-V2G
17-V2G
18-V2G
19-V2G
20-V2G
21-V2G
22-V2G
23-V2G
24-V2G
MAN-
SEC
MAN-
SEC
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
X
Disable
Crystal
MAN-
SEC
25
LVCMOS
Crystal
Copyright © 2016, Texas Instruments Incorporated
33
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
Table 5. CDCM6208V2G Loop Filter Recommendation for Pin Mode (continued)
Internal LPF
Components
PRI_REF
SEC_REF
Recommended
External LPF
Components
C1 / R2 / C2
f(PFD)
(MHz)
ICP
(mA)
Use Case
Freq
Freq
R3
C3
Type
Type
(MHz)
(MHz)
(Ω)
(pF)
MAN-
SEC
10
10
10
10
10
10
10
10
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
25-V2G
26-V2G
27-V2G
28-V2G
29-V2G
30-V2G
31-V2G
32-V2G
125
35.328
35.328
0.192
25
CML
25
35.328
35.328
0.192
25
LVCMOS
Crystal
Crystal
LVCMOS
Crystal
Crystal
Crystal
Crystal
6.25
35.328
35.328
0.192
25
4m
22pF / 860Ω / 22nF
22pF / 400Ω / 22nF
22pF / 400Ω / 22nF
100pF / 2.67kΩ / 6.8nF
100pF / 470Ω / 22nF
100pF / 470Ω / 22nF
100pF / 470Ω / 22nF
100pF / 470Ω / 22nF
100
100
100
100
100
100
100
100
242.5
242.5
242.5
242.5
242.5
242.5
242.5
242.5
MAN-
SEC
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
2.5m
2.5m
3.5m
2.5m
2.5m
2.5m
2.5m
MAN-
SEC
MAN-
SEC
MAN-
SEC
MAN-
SEC
50
50
25
MAN-
SEC
50
50
25
MAN-
SEC
50
50
25
10.4.3 Status Pins Definition
The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by
reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization
of which vitals are mapped to these two pins. Table 6 lists the three events that can be mapped to each status
pin and which can also be read in the register space.
Table 6. CDCM6208V2G Status Pin Definition List
STATUS
SIGNAL NAME
REGISTER BIT
NO.
SIGNAL TYPE SIGNAL NAME
DESCRIPTION
SEL_REF
LVCMOS
STATUS0, 1
Reg 3.12
Reg 3.9
Indicates Reference Selected for PLL:
0 → Primary input selected to drive PLL
1 → Secondary input selected to drive PLL
LOS_REF
LVCMOS
STATUS0, 1
Reg 3.11
Reg 3.8
Loss of selected reference input observed at active input:
0 → Reference input present
1 → Loss of reference input
Important Note 1: For LOS_REF to operate properly, the secondary
input SEC_IN must be enabled. Set register Q4.5=1. If register
Q4.5 is set to zero, LOS_REF will output a static high signal
regardless of the actual input signal status on PRI_IN.
PLL_UNLOCK
LVCMOS
STATUS0, 1
Reg 3.10
Reg 3.7
Indicates unlock status for PLL (digital):
PLL locked → Q21.02 = 0 and VSTATUS0/1= VIH
(1)
PLL unlocked → Q21.2 = 1 and VSTATUS0/1= VILSee note
Note 2: I f the smartmux is enabled and both reference clocks stall,
the STATUSx output signal will 98% of the time indicate the LOS
condition with a static high signal. However, in 2% of the cases, the
LOS detection engine erroneously stalls at a state where the
STATUSx output PLL lock indicator will signalize high for 511 out of
every 512 PFD clock cycles.
(1) The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.
34
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
NOTE
It is recommended to assert only one out of the three register bits for each of the status
pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference
clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 =
1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to
set the according 3 register bits to zero (e.g. Q3[12:9] = 0 for STATUS0 = 0). If more than
one bit is enabled for each STATUS signal, the function becomes OR'ed. For example, if
Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if the device
goes out of lock or the selected reference clock signal is lost.
10.4.4 PLL Lock Detect
The PLL lock detection circuit is a digital detection circuit which detects any frequency error, even a single cycle
slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the
counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as
th
toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 of the PFD update frequency to the
device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000 PFD
update clock cycles. If the system plans using PLL lock to toggle a system reset, then consider adding an RC
filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system
reset.
10.4.5 Interface and Control
The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208V2G via the SPI or I2C port.
The host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block
is controlled and monitored via a specific grouping of bits located within the register file. The host controls and
monitors certain device-wide critical parameters directly, via control/status pins. In the absence of a host, the
CDCM6208V2G can be configured to operate in pin mode where the control pins [PIN0-PIN4] can be set
appropriately to generate the necessary clock outputs out of the device.
REGISTER SPACE
Reg31
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
STATUS0
STATUS1/PIN0
PDN
Reg30
15 14 13 12 11 10
Control/
Status
Pins
Reg 23
15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
RESETN/PWR
Reg 22
15 14 13 12 11 10
Device
Control
And
Device
Hardware
Reg 21
15 14 13 12 11 10
SCL/PIN4
SDI/SDA/PIN1
SDO/AD0/PIN2
SCS/AD1/PIN3
9
8
7
6
5
4
3
2
1
0
SPI/
I2C
Port
Reg 20
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Status
Reg3
15 14 13 12 11 10
9
9
9
9
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
Reg2
15 14 13 12 11 10
Reg1
15 14 13 12 11 10
SI_MODE0
SI_MODE1
Reg 0
15 14 13 12 11 10
Comm
Select
SPI: SI_MODE[1:0]=00; I2C: SI_MODE[1:0]=01; Pin Mode: SI_MODE[1:0]=10
Figure 27. CDCM6208V2G Interface and Control Block
Within this register space, there are certain bits that have read/write access. Other bits are read-only (an attempt
to write to a read only bit will not change the state of the bit).
Copyright © 2016, Texas Instruments Incorporated
35
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
10.4.5.1 Register File Reference Convention
Figure 28 shows the method this document employs to refer to an individual register bit or a grouping of register
bits. If a drawing or text references an individual bit, the format is to specify the register number first and the bit
number second. The CDCM6208V2G contains 21 registers that are 16 bits wide. The register addresses and the
bit positions both begin with the number zero (0). A period separates the register address and bit address. The
first bit in the register file is address 'R0.0' meaning that it is located in Register 0 and is bit position 0. The last
bit in the register file is address R31.15 referring to the 16thbit of register address 31 (the 32ndregister in the
device
Reg05
Bit Number(s)
(s)
Register Number
5
4
3
2
Figure 28. CDCM6208V2G Register Reference Format
36
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
10.4.5.2 SPI - Serial Peripheral Interface
To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave
protocol in which the host system is always the master; therefore, the host always initiates communication
to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000.
Table 7. Serial Port Signals in SPI Mode
PIN
I/O
DESCRIPTION
NAME
NUMBER
SDI/SDA/PIN1
SDO/AD0/PIN2
SCS/AD1/PIN3
SCL/PIN4
2
3
4
5
Input
Output
Input
SDI: SPI Serial Data Input
SDO: SPI Serial Data
SCS: SPI Latch Enable
SCL: SPI/I2C Clock
Input
The host must present data to the device MSB first. A message includes a transfer direction bit, an address field,
and a data field as depicted in Figure 29
LSB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
1
2
0
3
0
4
0
5
0
6
7
8
9
Order of Transmission
Bit Definition
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
First Out
15 14 13 12 11 10
Fixed (4 bits)
Examples: Read Register 4:
Register Address (11 bits)
Data Payload (16 bits)
Message Field Definition
1|000 0|000 0000 0100| xxxx xxxx xxxx xxxx
0|000 0|000 0000 0101| 1111 0000 1111 0001
Write 0xF0F1 to Register 5:
Figure 29. CDCM6208V2G SPI Message Format
10.4.5.2.1 Configuring the PLL
The CDCM6208V2G allows configuring the PLL to accommodate various input and output frequencies either
through an I2C or SPI programming interface or in the absence of programming, the PLL can be configured
through control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop
Filter, Feedback Divider, Prescaler Divider, and Output Dividers.
For the PLL to operate in closed loop mode, the following condition in Equation 2 has to be met when using
primary input for the reference clock, and the condition in Equation 3 has to be met when using secondary input
for the reference clock.
f
f
PRI_REF
(M × R)
VCO
(N × PS_A)
=
(2)
f
f
SEC_REF
M
VCO
(N × PS_A)
=
(3)
In Equation 2 and Equation 3, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the
reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the
feedback divider, and PS_A the prescaler divider A.
The output frequency, ƒOUT, is a function of ƒVCO, the prescaler A, and the output divider (O), and is given by
Equation 4. (Use PS_B in for outputs 2, 3, 6, and 7).
f
OSC
(O × PS_A)
f
=
OUT
(4)
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When the output frequency plan calls for the use of some output dividers as fractional values, the following steps
are needed to calculate the closest achievable frequencies for those using fractional output dividers and the
frequency errors (difference between the desired frequency and the closest achievable frequency).
•
•
•
Based on system needs, decide the frequencies that need to have best possible jitter performance.
Once decided, these frequencies need to be placed on integer output dividers.
Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the
common divisor algorithm.
•
•
•
Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider,
input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the
prescaler divider.
Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support
the output frequencies that are not part of the common frequency plan from the common divisor algorithm
already worked out.
For each fractional divider value, try to represent the fractional portion in a 20 bit binary scheme, where the
first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is
represented as 0.125 and so on. Continue this process until the entire 20 bit fractional binary word is
exhausted.
•
•
Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of
the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the
mathematical function of the frequency out of the prescaler divider divided by the achievable fractional
divider.
The frequency error can then be calculated as the difference between the desired frequency and the closest
achievable frequency.
10.5 Programming
10.5.1 Writing to the CDCM6208V2G
To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the
clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208V2G. This bit signals if a read
(first bit high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208V2G with each
rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the
target register in the register file. The 16 bits that follow are the data payload. If the host sends an incomplete
message, (i.e. the host de-asserts the SCS pin high prior to a complete message transmission), then the
CDCM6208V2G aborts the transfer, and device makes no changes to the register file or the hardware. Figure 31
shows the format of a write transaction on the CDCM6208V2G SPI port. The host signals the CDCM6208V2G of
the completed transfer and disables the SPI port by de-asserting the SCS pin high.
38
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Programming (continued)
10.5.2 Reading from the CDCM6208V2G
As with the write operation, the host first initiates a SPI transfer by asserting the SCS pin low. The host signals a
read operation by shifting a logical high in the first bit position, signaling the CDCM6208V2G that the host is
imitating a read data transfer from the device. During the portion of the message in which the host specifies the
CDCM6208V2G register address, the host presents this information on the SDI pin of the device (for the first 15
clock cycles after the W/R bit). During the 16 clock cycles that follow, the CDCM6208V2G presents the data from
the register specified in the first half of the message on the SDO pin. The SDO output is 3-stated anytime SCS is
high, so that multiple SPI slave devices can be connected to the same serial bus. The host signals the
CDCM6208V2G that the transfer is complete by de-asserting the SCS pin high.
SCS (#37)
&
0
0
0
SDO internal
enable signal
SDO
(#34)
Data out
LVCMOS
CDCM6208
Figure 30.
10.5.3 Block Write/Read Operation
The device supports a block write and block read operation. The host need only specify the lowest address of the
sequence of addresses that the host needs to access. The CDCM6208V2G will automatically increment the
internal register address pointer if the SCS pin remains low after the SPI port finishes the initial 32-bit
transmission sequence. Each transmission of 16 bits (a data payload width) results in the device automatically
incrementing the address pointer (provided the SCS pin remains active low for all sequences).
SCS
SCL
WRITE
A29 A28
A26 A25
A22 A21 A20 A19
A16 D15
D13
D10 D9 D8
D6 D5 D4
D2 D1 D0
A31 A30
A27
A24 A23
A18 A17
D14
D12 D11
D7
D3
SCI
A31 A30 A29 A28
A23
SCI
A27 A26 A25
A24
A21 A20 A19 A18 A17 A16
A22
DON‘T CARE
READ
D3
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4
D2 D1 D0
HI-Z
SCO
16-BIT COMMAND
16-BIT DATA
Figure 31. CDCM6208V2G SPI Port Message Sequencing
10.5.4 I2C Serial Interface
With SI_MODE1=0 and SI_MODE0=1 the CDCM6208V2G enters I 2C mode. The I2C port on the
CDCM6208V2G works as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode
operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input
receivers ignore pulses of less than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger
at the SDA and SCL inputs to provide receiver input hysteresis for increased noise robustness.
NOTE
Communication through I2C is not possible while RESETN is held low.
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Programming (continued)
In an I2C bus system, the CDCM6208V2G acts as a slave device and is connected to the serial bus (data bus
SDA and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices
to be connected to the same serial bus. The CDCM6208V2G allows up to four unique CDCM6208V2G slave
devices to occupy the I2C bus in addition to any other I2C slave device with a different I2C address. These slave
devices are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a
matching slave address responds to subsequent I2C commands. The device slave address is 10101xx (the two
LSBs are determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set
through pins on device powerup.
SDA
Data out
Data in
CDCM6208
Figure 32.
During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred.
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data
line can change only when the clock signal on the SCL line is low. The start data transfer condition is
characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is
characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are
always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed
by an acknowledge bit and bytes are sent MSB first.
The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A
= 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA
line high during the 9thclock pulse.
The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master. The CDCM6208V2G slave address bytes are given in
below table.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10 thclock pulse following the acknowledge bit for the last data byte from
the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during
the 9thclock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave
knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the
low period before the 10 thclock pulse, and high during the 10 thclock pulse to assert a stop condition.
40
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Programming (continued)
For "Register Write/Read" operations, the I2C master can individually access addressed registers, that are made
of two 8-bit data bytes.
Table 8. I2C Slave Address Byte
A6
1
A5
0
A4
1
A3
0
A2
1
AD1
AD0
R/W
1/0
1/0
1/0
1/0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
Table 9. Generic Programming Sequence
S
Start Condition
Repeated Condition
Sr
R/W 1 = Read (Rd) from slave; 0 = Write (Wr) to slave
A
P
Acknowledge (ACK = 0 and NACK = 1)
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 33. Register Write Programming Sequence
1
7
1
1
8
1
8
1
8
1
8
1
1
SLAVE
Address
Register
Address
Register
Address
Data
Byte
Data
Byte
S
Wr
A
A
A
A
A
P
Figure 34. Register Read Programming Sequence
1
7
1
1
8
1
8
1
1
1
1
1
8
1
8
1
1
SLAVE
Address
Register
Address
Register
Address
Slave
Address
Data
Byte
Data
Byte
S
Wr
A
A
A
S
Rd
A
A
A
P
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10.6 Register Maps
In SPI/I2C mode the device can be configured through twenty registers. Register 4 configures the input, Reg 0-3
the PLL and dividers, and Register 5 - 20 configures the 8 different outputs.
CDCM6208 Register programming
INT
REG 5
DIV
REG 6
REG 4
REG 4
PRI
R
PSB
M
Charge Pump
and
Loop Filter
PSA
VCO
f
REG 4
SEC
REG 1
REG 3
INT
DIV
REG 0
REG 7
N
REG 8
REG 2 / REG1
REG 9,10,11
FRAC
DIV
PRI
SEC
REG 9
REG 12,13,14
FRAC
DIV
twL
{9/
REG 12
FRAC
DIV
REG 15,16,17
FRAC
DIV
REG 18,19, 20
Figure 35. Device Register Map
42
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Register Maps (continued)
Table 10. Register 0
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
These bits must be set to 0
15:10
RESERVED
PLL Internal Loop Filter Capacitor (C3) Selection
000 → 35 pF
001→ 112.5 pF
010 → 177.5 pF
011 → 242.5 pF
100 → 310 pF
PLL Internal Loop Filter
(C3)
9:7
LF_C3[2:0]
101 → 377.5 pF
110 → 445 pF
111 → 562.5 pF
PLL Internal Loop Filter Resistor (R3) Selection
000 → 10 Ω
001 → 30 Ω
010 → 60 Ω
011 → 100 Ω
100 → 530 Ω
PLL Internal Loop Filter
(R3)
6:4
LF_R3[2:0]
101→ 1050 Ω
110 → 2080 Ω
111 → 4010 Ω
PLL Charge Pump Current Setting
000 → 500 µA
001 → 1.0 mA
010 → 1.5 mA
3:1
PLL_ICP[2:0]
RESERVED
PLL Charge Pump
011 → 2.0 mA
100 → 2.5 mA
101 → 3.0 mA
110 → 3.5 mA
111→ 4.0 mA
This bit is tied to zero statically, and it is recommended to set to 0
when writing to register.
0
Table 11. Register 1
BIT
15:2
1:0
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
PLL Reference 14-b Divider Selection
(Divider value is register value +1)
PLL_REFDIV[13:0]
PLL_FBDIV1[9:8]
PLL Reference Divider
PLL Feedback Divider 1 PLL Feedback 10-b Divider Selection, Bits 9:8
Table 12. Register 2
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
PLL Feedback 10-b Divider Selection, Bits 7:0
(Divider value is register value +1)
15:8
PLL_FBDIV1[7:0]
PLL Feedback Divider 1
PLL Feedback 8-b Divider Selection
(Divider value is register value +1)
7:0
PLL_FBDIV0[7:0]
PLL Feedback Divider 0
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Table 13. Register 3
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
These bits must be set to 0
15:13
RESERVED
Reference clock status enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 6 for full description)
12
11
10
9
ST1_SEL_REFCLK
ST1_LOR_EN
ST1_PLLLOCK_EN
ST0_SEL_REFCLK
ST0_LOR_EN
ST0_PLLLOCK_EN
RSTN
Loss-of-reference Enable on Status 1 pin:
0 → Disable"
1 → Enable (See Table 6 for full description)
PLL Lock Indication Enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 6 for full description)
Device Status
Reference clock status enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 6 for full description)
Loss-of-reference Enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 6 for full description)
8
PLL Lock Indication Enable on Status 0 pin:"
0 → Disable
1 → Enable (See Table 6 for full description)
7
Device Reset Selection:
0 → Device In Reset (retains register values)
1 → Normal Operation
6
Device Reset
Output Divider
PLL/VCO
Output Channel Dividers Synchronization Enable:
0 → Forces synchronization
1 → Exits synchronization
5
SYNCN
PLL/VCO Calibration Enable:
0 → Disable
4
ENCAL
1 → Enable
PLL Prescaler 1 Integer Divider Selection:
00 → Divide-by-4
01→ Divide-by-5
10 → Divide-by-6
11 → RESERVED
used for Y2, Y3, Y6, and Y7
3:2
1:0
PS_B[1:0]
PS_A[1:0]
PLL Prescaler Divider B
PLL Prescaler Divider A
PLL Prescaler 0 Integer Divider Selection:
00 → Divide-by-4
01 → Divide-by-5
10 → Divide-by-6
11 → RESERVED
used in PLL feedback, Y0, Y1, Y4, and Y5
44
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BIT
ZHCSF03 –MARCH 2016
Table 14. Register 4
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
Smart MUX Pulse Width Selection. This bit controls the Smart MUX
delay and waveform reshaping.
00 → PLL Smart MUX Clock Delay and Reshape Disabled (default
in all pin modes)
15:14
SMUX_PW[1:0]
01 → PLL Smart MUX Clock Delay Enable
10 → PLL Smart MUX Clock Reshape Enable
11 → PLL Smart MUX Clock Delay and Reshape Enable
Smart MUX Mode Selection:
0 → Auto select
1 → Manual select
Reference Input Smart
MUX
13
SMUX_MODE_SEL
Note: in Auto select mode, both input buffers must be enabled. Set
R4.5 = 1 and R4.2 = 1
Smart MUX Selection for PLL Reference:
0 → Primary
12
11:8
7:6
5
SMUX_REF_SEL
CLK_PRI_DIV[3:0]
SEC_SELBUF[1:0]
EN_SEC_CLK
1 → Secondary (only if REF_SEL pin is high)
This bit is ignored when smartmux is set to auto select (e.g. R4.13 =
0). See Table 6 for details.
Primary Input (R) Divider Selection:
0000 → Divide by 1
1111 → Divide by 16
Primary Input Divider
Secondary Input
Secondary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → Crystal
Secondary input enable:
0 → Disable
1 → Enable
Primary Input Buffer Type Selection:
00 → CML
4:3
PRI_SELBUF[1:0]
EN_PRI_CLK
01 → LVDS
10 → LVCMOS
11 → LVCMOS
Primary Input
Primary input enable:
0 → Disable
1 → Enable
2
1
0
Supply voltage for secondary input:
0 → 1.8 V
1 → 2.5/3.3 V
(1)
SEC_SUPPLY
Secondary Input
Primary Input
Supply voltage for primary input:
0 → 1.8 V
(2)
PRI_SUPPLY
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_SEC supply voltage used.
(2) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_PRI supply voltage used.
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Table 15. Register 5
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output Channel 1 Type Selection:
00, 01 → LVDS
10 → CML
8:7
6:5
4:3
SEL_DRVR_CH1[1:0]
11 → PECL
Output Channel 1
Output channel 1 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN _CH1[1:0]
Output Channel 0 Type Selection:
00, 01 → LVDS
10 → CML
SEL_DRVR_CH0[1:0]
EN_CH0[1:0]
11 → PECL
Output Channel 0
Output channel 0 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
2:1
0
Output Channels 0 and 1 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
Output Channels 0
and 1
(1)
SUPPLY_CH0_1
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 16. Register 6
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
8
Output Channels 0
and 1
Output channels 0 and 1 8-b output integer divider setting
(Divider value is register value +1)
7:0
OUTDIV0_1[7:0]
46
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Table 17. Register 7
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output Channel 3 Type Selection:
00, 01 → LVDS
10 → CML
8:7
6:5
4:3
SEL_DRVR_CH3[1:0]
11 → PECL
Output Channel 3
Output channel 3 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH3[1:0]
Output Channel 2 Type Selection:
00, 01 → LVDS
10 → CML"
SEL_DRVR_CH2[1:0]
EN_CH2[1:0]
11 → PECL
Output Channel 2
Output channel 2 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
2:1
0
Output Channels 2 and 3 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
Output Channels 2
and 3
(1)
SUPPLY_CH2_3
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 18. Register 8
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
8
Output Channels 2
and 3
Output channels 2 and 3 8-b output integer divider setting
(Divider value is register value +1)
7:0
OUTDIV2_3[7:0]
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Table 19. Register 9
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
15
RESERVED
Output MUX setting for output channel 4:
00 and 11 → PLL
01 → Primary input
14:13
12:10
OUTMUX_CH4[1:0]
PRE_DIV_CH4[2:0]
10 → Secondary input
Output channel 4 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q9.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
Output channel 4 fractional divider enable:
0 → Disable
1 → Enable
9
8
EN_FRACDIV_CH4
Output channel 4 LVCMOS output slew:
0 → Normal
1 → Slow
LVCMOS_SLEW_CH4
Output channel 4 negative-side LVCMOS enable:
0 → Disable
7
EN_LVCMOS_N_CH4
Output Channel 4
1 → Enable (Negative side can only be enabled if positive side is
enabled)
Output channel 4 positive-side LVCMOS enable:
6
5
EN_LVCMOS_P_CH4
RESERVED
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 4 type selection:
00 or 01 → LVDS
10 → LVCMOS
4:3
SEL_DRVR_CH4[2:0]
11 → HCSL
Output channel 4 enable:
00 → Disable
2:1
0
EN_CH4[1:0]
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output channel 4 Supply Voltage Selection:
0 → 1.8 V
(1)
SUPPLY_CH4
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 20. Register 10
BIT
15
14
13
12
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output channel 4 8-b integer divider setting
(Divider value is register value +1)
11:4
3:0
OUTDIV4[7:0]
Output Channel 4
FRACDIV4[19:16]
Output channel 4 20-b fractional divider setting, bits 19 - 16
Table 21. Register 11
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:0
FRACDIV4[15:0]
Output Channel 4
Output channel 4 20-b fractional divider setting, bits 15 - 0
48
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Table 22. Register 12
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
15
RESERVED
Output MUX setting for output channel 5:
00 and 11 → PLL
01 → Primary input
14:13
12:10
OUTMUX_CH5[1:0]
PRE_DIV_CH5[2:0]
10 → Secondary input
Output channel 5 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q12.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
Output channel 5 fractional divider enable:
0 → Disable
1 → Enable
9
8
EN_FRACDIV_CH5
Output channel 5 LVCMOS output slew:
0 → Normal
1 → Slow
LVCMOS_SLEW_CH5
Output channel 5 negative-side LVCMOS enable:
0 → Disable
7
EN_LVCMOS_N_CH5
Output Channel 5
1 → Enable (Negative side can only be enabled if positive side is
enabled)
Output channel 5 positive-side LVCMOS enable:
6
5
EN_LVCMOS_P_CH5
RESERVED
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 5 type selection:
00 or 01 → LVDS
10 → LVCMOS
4:3
SEL_DRVR_CH5[2:0]
11 → HCSL
Output channel 5 enable:
00 → Disable
2:1
0
EN_CH5[1:0]
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output channel 5Supply Voltage Selection:
0 → 1.8 V
(1)
SUPPLY_CH5
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 23. Register 13
BIT
15
14
13
12
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output channel 5 8-b integer divider setting
(Divider value is register value +1)
11:4
3:0
OUTDIV5[7:0]
Output Channel 5
FRACDIV5[19:16]
Output channel 5 20-b fractional divider setting, bits 19-16
Table 24. Register 14
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:0
FRACDIV5[15:0]
Output Channel 5
Output channel 5 20-b fractional divider setting, bits 15-0
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Table 25. Register 15
BIT
15
BIT NAME
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
14
This bit must be set to 0
This bit must be set to 0
13
Output channel 6 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q15.9 = 0)
000 → Divide by 2
12:10
PRE_DIV_CH6[2:0]
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
Output channel 6 fractional divider enable:
0 → Disable
1 → Enable
9
8
EN_FRACDIV_CH6
Output channel 6 LVCMOS output slew:
0 → Normal
1 → Slow
LVCMOS_SLEW_CH6
Output channel 6 negative-side LVCMOS enable:
0 → Disable
7
EN_LVCMOS_N_CH6
1 → Enable (Negative side can only be enabled if positive side is
enabled)
Output Channel 6
Output channel 6 positive-side LVCMOS enable:
6
5
EN_LVCMOS_P_CH6
RESERVED
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 6 type selection:
00 or 01 → LVDS
10 → LVCMOS
4:3
SEL_DRVR_CH6[1:0]
11 → HCSL
Output channel 6 enable:
00 → Disable
2:1
0
EN_CH6[1:0]
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output channel 6 Supply Voltage Selection:
0 → 1.8 V
(1)
SUPPLY_CH6
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 26. Register 16
BIT
15
14
13
12
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output channel 6 8-b integer divider setting
(Divider value is register value +1)
11:4
3:0
OUTDIV6[7:0]
Output Channel 6
FRACDIV6[19:16]
Output channel 6 20-b fractional divider setting, bits 19-16
Table 27. Register 17
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:0
FRACDIV6[15:0]
Output Channel 6
Output channel 6 20-b fractional divider setting, bits 15-0
50
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Table 28. Register 18
BIT
15
BIT NAME
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
14
This bit must be set to 0
This bit must be set to 0
13
Output channel 7 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q18.9 = 0)
000 → Divide by 2
12:10
PRE_DIV_CH7[2:0]
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
Output channel 7 fractional divider enable: 0 → Disable, 1 →
Enable
9
8
EN_FRACDIV_CH7
LVCMOS_SLEW_CH7
Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow
Output channel 7 negative-side LVCMOS enable: 0 → Disable, 1 →
Enable (Negative side can only be enabled if positive side is
enabled)
7
EN_LVCMOS_N_CH7
Output Channel 7
Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 →
Enable
6
5
EN_LVCMOS_P_CH7
RESERVED
This bit must be set to 0
Output channel 7 type selection:00 or 01 → LVDS, 10 → LVCMOS,
11 → HCSL
4:3
SEL_DRVR_CH7[2:0]
Output channel 7 enable: 00 → Disable, 01 → Enable, 10 → Drive
static low, 11 → Drive static high
2:1
0
EN_CH7[1:0]
Output channel 7 Supply Voltage Selection: 0 → 1.8 V, 1 → 2.5/3.3
V
(1)
SUPPLY_CH7
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 29. Register 19
BIT
15
14
13
12
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
This bit must be set to 0
Output channel 7 8-b integer divider setting
(Divider value is register value +1)
11:4
3:0
OUTDIV7[7:0]
Output Channel 7
FRACDIV7[19:16]
Output channel 7 20-b fractional divider setting, bits 19-16
Table 30. Register 20
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:0
FRACDIV7[15:0]
Output Channel 7
Output channel 7 20-b fractional divider setting, bits 15-0
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Table 31. Register 21 (Read Only)
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
This bit will read a 0
8
7
6
5
4
3
Indicates unlock status for PLL (digital):
0 → PLL locked
1 → PLL unlocked
2
PLL_UNLOCK
Note: the external output signal on Status 0 or Status 1 uses a
reversed logic, and indicates "lock" with a VOH signal and unlock
with a VOL signaling level.
Device Status
Monitoring
Loss of reference input observed at input Smart MUX output in
observation window for PLL:
1
0
LOS_REF
SEL_REF
0 → Reference input present
1 → Loss of reference input
Indicates Reference Selected for PLL:
0 → Primary
1 → Secondary
Table 32. Register 40 (Read Only)
BIT
15
14
13
12
11
10
9
BIT NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
8
7
6
Indicates the device version (Read only):
000 → CDCM6208V2G
5:3
VCO_VERSION
Device Information
Indicates the silicon die revision (Read only):
00X --> Engineering Prototypes
010 --> Production Material
2:0
DIE_REVISION
52
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Table 33. Default Register Setting For SPI/I2C Modes
Register
CDCM6208V2G
0x01B9
0x0000
0x0013
0x08F6
0x30B4
0x01BA
0x0004
0x01BA
0x0005
0x001A
0x0130
0x0000
0x001A
0x0030
0x0000
0x001A
0x0050
0x0000
0x0652
0x0008
0x0000
.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
.
.
.
.
.
40
0x00XX
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output
clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers.
11.2 Typical Applications
DR
Packet PCIe
Accel
CDCM6208
Synthesizer
Mode
TMS320TCI6616/18
DSP
AIF
ALT
SRIO
CORE
Base Band DSP
Clocking
Figure 36. Typical Application Circuit
Timing
FBADC
RXADC
TXDAC
Core
SyncE
Packet
network
1pps
1pps
GPS receiver
RF LO
CDCM6208
DPLL
APLL
IEEE1588
timing extract
RF LO
Ethernet
Pico Cell Clocking
Figure 37. Typical Application Circuit
11.2.1 Design Requirements
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, a 10 GigEthernet). Fully estimating the clock jitter
impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR
bandwidth.
54
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Typical Applications (continued)
11.2.1.1 Device Block-level Description
The CDCM6208V2G includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input
interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider.
Completing the CDCM6208V2G device are the combination of integer and fractional output dividers, and
universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the
regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs
than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the
external power supply rail with a PSNR of better than -50 dB at all frequencies. The regulator capacitor pin
REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (e.g. below 1 Ω ESR) to ensure
stability.
11.2.1.2 Device Configuration Control
Figure 39 illustrates the relationships between device states, the control pins, device initialization and
configuration, and device operational modes. In pin mode, the state of the control pins determines the
configuration of the device for all device states. In programming mode, the device registers are initialized to their
default state and the host can update the configuration by writing to the device registers. A system may transition
a device from pin mode to host connected mode by changing the state of the SI_MODE pins and then triggering
a device reset (either via the RESETN pin or via setting the RESETN bit in the device registers). In reset, the
device disables the outputs so that unwanted sporadic activity associated with device initialization does not
appear on the device outputs.
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Typical Applications (continued)
11.2.1.3 Configuring the RESETN Pin
Figure 38 shows two typical applications examples of the RESETN pin.
DVDD
DVDD
DVDD
50k
50k
50k
#44 (RESET)
#44 (RESET)
#44 (PWR)
GPO
5k
RPD
Host
Controller
CDCM6208
CDCM6208
CDCM6208
if I/O power = 1.8V: RPD=0-Ohm
if I/O power=3.3V: RPD=open
(a) (SPI/I2C Host mode)
(b) (SPI/I2C Host Mode)
(c) (PIN Mode)
Figure 38. RESETN/PWR Pin Configurations
Figure 38 (a) SPI / I2C mode only: shows the RESETN pin connected to a digital device that controls device
reset. The resistor and capacitor combination ensure reset is held low even if the CDCM6208V2G is powered up
before the host controller output signal is valid.
Figure 38 (b) SPI / I2C mode only:shows a configuration in which the user wishes to introduce a delay between
the time that the system applies power to the device and the device exiting reset. If the user does not use a
capacitor, then the device effectively ignores the state of the RESETN pin.
Figure 38 (c) Pin mode only: shows a configuration useful if the device is used in Pin Mode. Here device pin
number 44 becomes the PWR input. An external pull down resistor can be used to pull this pin down. If the
resistor is not installed, the pin is internally pulled high.
56
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Typical Applications (continued)
Figure 39 shows how the different possible device configurations and when the VCO becomes calibrated and the
outputs turn on and off.
Power on
Reset
no
PDN =1?
(all outputs are disabled)
SI_MODE1
SI_MODE0
01
I2C Mode
(activate I2C IF)
00
10
no
RESETN =1?
SPI Mode
(activate SPI IF)
Pin Mode
latch PIN0 to PIN4, and
PWR
Enter Pin Mode specified by
the PINx and PWR
load device registers with defaults; registers
are customer programmable through serial IF
wait for selected reference input
signal (PRI/SEC) to become valid
Configure all device settings
no
wait for selected reference
input signal (PRI/SEC) to
become valid
Disable
all
RESETN =1?
outputs
Calibrate VCO
no
Calibrate VCO
no
Disable
Disable
all
all
SYNCN =1?
SYNCN =1?
outputs
outputs
Synchronize outputs
Enable all outputs
Synchronize outputs
Enable outputs
Normal device operation in
PIN mode
Normal device operation in
HOST mode
no
no
no
SYNCN=1?
SYNCN=1?
yes
RESETN=1?
yes
PDN=1?
PDN=1?
Disable
all
outputs
Figure 39. Device Power up and Configuration
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Typical Applications (continued)
11.2.1.4 Preventing False Output Frequencies in SPI/I2C Mode at Startup:
Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency.
Holding RESET low at power-up until the device is fully configured keeps all outputs disabled. The device
calibrates automatically after RESET becomes released and starts out with the desired output frequency.
NOTE
The RESETN pin cannot be held low during I2C communication. Instead, use the SYNC
pin to disable the outputs during an I2C write operation, and toggle RESETN pin
afterwards. Alternatively, other options exist such as using the RESETN bit in the register
space to disable outputs until the write operation is complete.
Configure
Registers
Register
Space
Register
Space
0 to 21
SPI or I2C
Master
SPI or I2C
Master
DVDD
DVDD
Release
RESETGPO
50k
50k
GPO
RESET=low
CDCM6208
RESET=high
CDCM6208
Step 1
Step 2
Figure 40. Reset Pin Control During Register Loading
11.2.1.5 Power Down
When the PDN pin = 0, the device enters a complete power down mode with a current consumption of no more
than 1 mA from the entire device.
11.2.1.6 Device Power Up Timing:
Before the device outputs turn on after power up, the device goes through the following initialization routine:
Table 34. Initialization Routine
STEP
DURATION
COMMENTS
Depends on customer supply
ramp time
The POR monitor holds the device in power-down or reset until the
VDD supply voltage reaches 1.06 V (min) to 1.26 V (max)
Step 1: Power up ramp
Depends on XTAL. Could be
several ms;
For NX3225GA 25 MHz typical
XTAL startup time measures 200 circuit, and holds the device in reset until the XTAL stage has
µs. sufficient swing.
This step assumes RESETN = 1 and PDN = 1.The XTAL startup
time is the time it takes for the XTAL to oscillate with sufficient
amplitude. The CDCM6208V2G has a built-in amplitude detection
Step 2: XO startup (if crystal is
used)
58
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Typical Applications (continued)
Table 34. Initialization Routine (continued)
STEP
DURATION
COMMENTS
This counter of 64 k clock cycles needs to expire before any further
power-up step is done inside the device. This counter ensures that
the input to the PFD from PRI or SEC input has stabilized in
64k Reference clock cycles at
PFD input
Step 3: Ref Clock Counter
frequency. The duration of this step can range from 640 µs (fPFD
100 MHz) to 8 sec (8 kHz PFD).
=
64k FBCLK cycles with CW=32;
The duration is similar to Step 3, The Feedback counter delays the startup by another 64k PFD clock
or can be more accurately
estimated as:
Approximately 64k x PS_A x
N/2.48 GHz
cycles. This is so that all counters are well initialized and also ensure
additional timing margin for the reference clock to settle. This step
can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz).
Step 4: FBCLK counter
This step calibrates the VCO to the exact frequency range, and
Step 5: VCO calibration
Step 6: PLL lock time
128k PFD reference clock cycles takes exactly 128k PFD clock cycles. The duration can therefore
range from 1280 µs (fPFD= 100 MHz) to 16 sec (f PFD= 8 KHz).
The Outputs turn on immediately after calibration. A small frequency
error remains for the duration of approximately 3 x LBW (so in
approximately 3 x LBW
synthesizer mode typically 10 µs). The initial output frequency will be
lower than the target output frequency, as the loop filter starts out
initially discharged.
The PLL lock indicator if selected on output STATUS0 or STATUS1
will go high after approximately 2048 to 2560 PFD clock cycles to
indicate PLL is now locked.
approximately 2305 PFD clock
cycles
Step 7: PLL Lock indicator high
Y4n
Device outputs held static lo(wYxP=low, Yxn=high)
Outputs tristated
Y4(HCSL)
Y4p
Step5
VCO CAL
Step2
XO startup
Step3
Ref Clk Cntr
Step4
FBCLK Cntr
From here
on Device
is locked
Step6: PLL lock time
RESETN held low
1.8V
1.05V
Step1: Pwr up
Figure 41. Powerup Time
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Figure 42. XTAL Startup Using NX3225GA 25 MHz (Step 2)
60
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{tep 7
Çime from ꢀ[[ [ock
to [h/Y signal asserting ꢁigꢁ on {Ç!ÇÜ{0 = 78…s
4=3.5%
140ns
250ns
Figure 43. PLL Lock Behavior (Step 6)
11.2.1.7 Input Mux and Smart Input Mux
The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register).
The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes
are suppressed at the MUX output.
Table 35. Input Mux Selection
REGISTER 4 BIT
13SMUX_MODE_SE
L
SI_MODE1
PIN NO. 47
REGISTER 4 BIT 12
SMUX_REF_SEL
REF_SEL
PIN NO. 6
SELECTED INPUT
Auto Select Priority is given to Primary
Reference input.
0
1
X
X
1
0
1
Primary input
input select through
SPI/I2C
0 (SPI/I2C mode)
Secondary input
Primary input
0
1
0
1
input select through
external pin
1
Secondary input
Primary or Auto (see Table 4)
1 (pin mode)
not available
Secondary or Auto (see Table 4)
Example 1:An application desired to auto-select the clock reference in SPI/I2C mode. During production testing
however, the system needs to force the device to use the primary followed by the secondary input. The settings
would be as follows:
1. Tie REF_SEL pin always high
2. For primary clock input testing, use R4[13:12] = 10
3. For secondary clock input testing, set R4[13:12] = 11.
4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00
Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case,
program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.
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SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux
(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.
Switching behavior: The input clocks can have any phase. When switching happens between one input clock to
the other, the phase of the output clock slowly transitions to the phase of the newly selected input clock. There
will be no-phase jump at the output. The phase transition time to the new reference clock signal depends on the
PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF. The
timing diagram of an auto-switch at the input MUX is shown in Figure 44.
Figure 44. Smart Input MUX Auto-Switch Mode Timing Diagram
11.2.1.8 Universal INPUT Buffer (PRI_REF, SEC_REF)
The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require
external termination schemes. The secondary input buffer also supports crystal inputs and Table 28 provides the
characteristics of the crystal that can be used. Both inputs incorporate hysteresis.
11.2.1.9 VCO Calibration
The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of
the CDCM6208V2G must be calibrated to ensure that the clock outputs deliver optimal phase noise
performance. Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of
the VCO. While transparent to the user, the CDCM6208V2G and the host system perform the following steps
comprising a VCO calibration sequence:
1. Normal Operation- When the CDCM6208V2G is in normal (operational) mode, the state of both the power
down pin (PDN) and reset pin (RESETN) is high.
2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset via the PDN pin, via the RESETN pin, or by
removing and restoring device power. Pulling either of these pins low places the device in the reset state.
Holding either pin low holds the device in reset.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated via the host interface. Exiting the reset state occurs automatically after
power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.
Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device
register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device
retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration
for a frequency plan other than the default state (i.e. the device calibrates the VCO based on the settings
contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is
low. Writing this bit to a high state and then returning it to the low state invokes a device reset without
restoring device defaults.
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4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The CDCM6208V2G calibrates the VCO. During the calibration routine, the device holds
all outputs in reset so that the CDCM6208V2G generates no spurious clock signals.
11.2.1.10 Reference Divider (R)
The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the
Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets
the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed
as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.
11.2.1.11 Input Divider (M)
The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is
operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to
the PLL and should be in the range of 8 kHz to 100 MHz.
11.2.1.12 Feedback Divider (N)
The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider
(1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to
800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to
100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper
operation.
11.2.1.13 Prescaler Dividers (PS_A, PS_B)
The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to
the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes
the PLL as it also drives the input of the Feedback Divider (N).
11.2.1.14 Phase Frequency Detector (PFD)
The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output
that is dependent on the phase and frequency difference between the two inputs. The allowable range of
frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.
11.2.1.15 Charge Pump (CP)
The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or
discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then
converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range
of the charge pump current is from 500 µA to 4 mA.
11.2.1.16 Programmable Loop Filter
The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop
bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in
Figure 45 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.
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C2
R2
C1
ELF
R3
C3
Figure 45. CDCM6208V2G PLL Loop Filter Topology
11.2.1.16.1 Loop Filter Component Selection
The loop filter setting and external resistor selection is important to set the PLL to best possible bandwidth and to
minimize jitter. A high bandwidth (≥ 100 kHz) provides best input signal tracking and is therefore desired with a
clean input reference (synthesizer mode). A low bandwidth (≤ 1 kHz) is desired if the input signal quality is
unknown (jitter cleaner mode). TI provides a software tool that makes it easy to select the right loop filter
rd
components. C1, R2, and C2 are external loop filter components, connected to the ELF pin. The 3 pole of the
loop filter is device internal with R3 and C3 register selectable.
11.2.1.16.2 Device Output Signaling
LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and
drives a signal swing identical to LVDS (~350mV). The output slew rate is faster than standard LVDS for best
jitter performance. The LVDS-like outputs should be AC-coupled when interfacing to a LVDS receiver. See
reference schematic Figure 63 for an example. The supply voltage for outputs configured LVDS can be selected
freely between 1.8 V and 3.3 V.
LVPECL-like: Outputs Y[3:0] support LVPECL-like signaling. The actual output stage uses a CML structure but
drives the same signal amplitude and rise time as true emitter coupled logic output stages. The LVPECL-like
outputs should be AC-coupled, and contrary to standard PECL designs, no external termination resistor to VCC-
2V is used (fewer components for lowest BOM cost). See reference schematic Figure 63 for an example. The
supply voltage for outputs configured LVPECL-like is recommended to be 3.3 V, though even 1.8 V provides
nearly the same output swing and performance at much lower power consumption.
CML: Outputs Y[3:0] support standard CML signaling. The supply voltage for outputs configured CML can be
selected freely between 1.8 V and 3.3 V. A true CML receiver can be driven DC coupled. All other differential
receiver should connected using AC coupling. See reference schematic Figure 63 for a circuit example.
HCSL: Outputs Y[7:4] support HCSL signaling. The supply voltage for outputs configured HCSL can be selected
freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50 Ω termination to GND.
See reference schematic for an example.
CMOS: Outputs Y[7:4] support 1.8 V, 2.5 V, and 3.3 V CMOS signaling. A fast or reduced slew rate can be
selected through register programming. Each differential output port can drive one or two CMOS output signals.
Both signals are “in-phase”, meaning their phase offset is zero degrees, and not 180˚. The output swing is set by
providing the according supply voltage (for example, if VDD_Y4=2.5 V, the output swing on Y4 will be 2.5 V
CMOS). Outputs configured for CMOS should only be terminated with a series-resistor near the device output to
preserve the full signal swing. Terminating CMOS signals with a 50 Ω resistor to GND would reduce the output
signal swing significantly.
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11.2.1.16.3 Integer Output Divider (IO)
Each integer output divider is made up of a continuous 10-b counter. The output buffer itself contributes only little
to the total device output jitter due to a low output buffer phase noise floor. The typical output phase noise floor
at an output frequency of 122.88 MHz, 20 MHz offset from the carrier measures as follows: LVCMOS: -157.8
dBc/Hz, LVDS: -158 dBc/Hz, LVPECL: -158.25 dBc/Hz, HCSL: -160 dBc/Hz. Therefore, the overall contribution
of the output buffer to the total jitter is approximately 50 fs-rms (12 k - 20 MHz). An actual measurement of phase
noise floor with different output frequencies for one nominal until yielded the following:
Table 36. Integer Output Divider (IO)
fOUT
LVDS (Y0)
PECL (Y0)
CML (Y0)
HCSL (Y4)
CMOS 3p3V (Y7)
-150.9 dBc/Hz
-153.1 dBc/Hz
-156.2 dBc/Hz
-159.4 dBc/Hz
-162.8 dBc/Hz
737.28 MHz
368.64 MHz
184.32 MHz
92.16 MHz
46.08 MHz
-154.0 dBc/Hz
-157.0 dBc/Hz
-157.3 dBc/Hz
-161.2 dBc/Hz
-162.2 dBc/Hz
-154.8 dBc/Hz
-155.8 dBc/Hz
-158.6 dBc/Hz
-161.6 dBc/Hz
-165.0 dBc/Hz
-154.4 dBc/Hz
-156.4 dBc/Hz
158.1 dBc/Hz
-161.4 dBc/Hz
-163.0 dBc/Hz
-153.1 dBc/Hz
-153.9 dBc/Hz
-154.7 dBc/Hz
-155.2 dBc/Hz
-154.0 dBc/Hz
11.2.1.16.4 Fractional Output Divider (FOD)
The CDCM6208V2G incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-
integer output divide ratios of the PLL frequencies. This feature is useful when systems require different,
unrelated frequencies. The fractional output divider architecture is shown in Figure 46.
tre-{caler t{_! or t{_ꢂ
Cracꢃiv tre ꢃivider
Lnꢀeger ꢃivider
Cracꢀional division
ë/h
2.39-2.55DIz
2.94-3.13DIz
[imiꢀ: 200-400ꢁIz
tre-{caler
ouꢀpuꢀ clock
398-800ꢁIz
÷ 4, 5 or 6
÷ 1, 2 or 3
÷ 1 ꢀo 256
.xxx
weg 10.11:4
weg 13.11:4
weg 16.11:4
weg 19.11:4
weg 9.12:10
weg 12.12:10
weg 15.12:10
weg 18.12:10
weg 10.3:0 + weg 11
weg 13.3:0 + weg 14
weg 16.3:0 + weg 17
weg 19.3:0 + weg 20
weg 3.4:0
Cracꢀional ꢃivider (simplified)
Figure 46. Fractional Output Divider Principle Architecture
(Simplified Graphic, not Showing Output Divider Bypass Options)
The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any
frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider
block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep
enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency
in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The
fractional values available are all possible 20-b representations of fractions within the following range:
•
•
•
•
•
•
1.0 ≤ ƒracDIV ≤ 1.9375
2.0 ≤ ƒracDIV ≤ 3.875
4.0 ≤ ƒracDIV ≤ 5.875
x.0 ≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254
254.0 ≤ ƒracDIV ≤ 255.875
256.0 ≤ ƒracDIV ≤ 256.99999
The CDCM6208V2G user GUI comprehends the fractional divider limitations; therefore, using the GUI to
comprehend frequency planning is recommended.
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The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on
which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than
exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from
50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths
(approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (<
1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer
mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional
divider enable bit, which engages the higher performing integer divider.
11.2.1.16.5 Output Synchronization
Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208V2G, this signal
comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output
synchronization is to toggle the SYNCN pin. When SYNC is asserted (VSYNCN ≤ VIL), all outputs are disabled
(high-impedance) and the output dividers are reset. When SYNC is de-asserted (VSYNCN ≥ VIH), the device first
internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on
simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the
SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles.
For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.
The SYNC feature is particularly helpful in systems with multiple CDCM6208V2G. If SYNC is released
simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices
configured to identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew
uncertainty due to sync remains ±2 clock cycles.
Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with
the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values
(PS_A=PS_B).
PS_A
1
2
3
4
5
6
7
8
9
10
11
12
One pre-scaler clock cycle
uncertainty, of when the
output turns on for one
device in one particular
configuration
SYNCN
Outputs tristates
Y0
Possibility (A)
Outputs turned on
Y0
Possibility (B)
Figure 47. SYNCN to Output Delay Uncertainty
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11.2.1.16.6 Output MUX on Y4 and Y5
The CDCM6208V2G device outputs Y4 and Y5 can either be used as independent fractional outputs or allow
bypassing of the PLL in order to output the primary or secondary input signal directly.
11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP
DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term
reliability problems, it is recommended to avoid any clock signal to the DSP until the DSP power rail is also
powered up. This can be achieved in two ways using the CDCM6208V2G:
1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on
outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power
supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208V2G
output will remain disabled until the DSP rails ramps up as well. Figure 48 shows the turn-on behavior.
Figure 48. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers
Up While Output Y0 is Already Running.
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11.2.2 Detailed Design Procedure
11.2.2.1 Jitter Considerations in SERDES Systems
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, 10 GigEthernet). Fully estimating the clock jitter impact
on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR bandwidth. As
can be seen in Figure 49, the bandwidth of TX and RX is the frequency range in which clock jitter adds without
any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock
jitter with a 20 dB/dec or even steeper roll-off.
Serializer
De-Serializer
serial data with
embedded clock
TX PLL
RX PLL
CDR
TX REF
CLOCK
RX REF
CLOCK
fhigh=BWTX PLL
flow=BWRX PLL
HTransfer(f) = HTXPLL * ( 1 - HRXPLL
)
flow fhigh
f
=20MHz for 10GbE
flow=1.875MHz for 10GbE
high
Figure 49. Serial Link Jitter Budget Explanation
Example: SERDES link with KeyStone™ I DSP
The SERDES TX PLL of the TI KeyStone™ I DSP family (see SPRABI2) for the SRIO interface, has a 13 MHz
PLL bandwidth (Low Pass Characteristic, see Figure 49). The CDCM6208V2, pin-mode 27, was characterized in
this example over Process, Voltage and Temperature (PVT) with a low pass filter of 13 MHz to simulate the TX
PLL. The attenuation is higher or equal to 20 dB/dec; therefore, the characterization used 20 dB/dec as worst
case.
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Table 37 shows the maximum Total Jitter(1) over PVT with and without Low Pass Filter.
Table 37. Maximum Total Jitter Over PVT With and Without Low Pass Filter
MAX TJ [ps]
with 13 MHz LOW PASS
FILTER
FREQUENCY
[MHz]
MAX TJ [ps]
DSP SPEC
MAX TJ [ps]
without LOW PASS FILTER
OUTPUT
Y0
Y2
Y3
122.88
30.72
30.72
56
56
56
9.43
9.60
9.47
8.19
7.36
7.42
156.25
(6 bit fraction)
Y4
Y5
56
56
57.66
76.87
17.48
32.32
156.25
(20 bit fraction)
Y6
Y7
100.00
66.667
56
86.30
81.71
33.86
35.77
300
(1) Input signal: 250fs RMS (Integration Range 12kHz to 5MHz)
Figure 50 shows the maximum Total Jitter with, without Low Pass Filter characteristic and the maximum TI
KeyStone™ I specification.
Figure 50. Maximum Jitter Over PVT
NOTE
Due to the damping characteristic of the DSP SERDES PLLs, the actual TJ data can be
worse.
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11.2.2.2 Jitter Considerations in ADC and DAC Systems
A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular
frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity.
The following test results were achieved connecting the CDCM6208V2G to ADC and DACs:
Figure 51. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49
Figure 52. IF = 60 MHz Fclk = 122.88 MHz CDCM6208V2G driving ADC
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Observation: up to an IF = 100 MHz, The ADC performance when driven by the CDCM6208V2G (Figure 52) is
similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering
(Figure 51).
Conclusion Therefore, the CDCM6208V2G is usable for applications up to 100 MHz IF. For IF above 100 MHz,
the SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and
other outputs running at different integer frequencies.
Important note on crosstalk: it is highly recommended that both pre-dividers are configured identically, as
otherwise SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.
245.76MHz DAC
driven from —ideal source“
245.76MHz DAC
driven from CDCM6208
(Wenzel oscillator buffered by HP8133A)
(no performance degradation observed)
* RBW 30 kHz
* VBW 300 kHz
* RBW 30 kHz
* VBW 300 kHz
Ref -14.1 dBm
* Att 5 dB
* SWT 1 s
Ref -14.1 dBm
* Att 5 dB
* SWT 1 s
-20
-30
-40
-50
-60
-70
-20
-30
-40
-50
-60
-70
A
A
1 RM *
CLRWR
1 RM *
CLRWR
-80
-80
NOR
PRN
NOR
PRN
-90
-90
-100
-100
-110
-110
Center 245.76 MHz
2.55 MHz/
W-CDMA 3GPP FWD
Span 25.5 MHz
Center 245.76 MHz
2.55 MHz/
W-CDMA 3GPP FWD
Span 25.5 MHz
Tx Channel
Bandwidth 3.84 MHz
Tx Channel
Bandwidth 3.84 MHz
Power -9.40 dBm
Power -9.39 dBm
Adjacent Channel
Bandwidth 3.84 MHz
Spacing 5 MHz
Adjacent Channel
Bandwidth 3.84 MHz
Spacing 5 MHz
Lower -73.12 dB
Upper -73.06 dB
Lower -72.81 dB
Upper -72.40 dB
Alternate Channel
Bandwidth 3.84 MHz
Spacing 10 MHz
Alternate Channel
Bandwidth 3.84 MHz
Spacing 10 MHz
Lower -79.22 dB
Upper -79.19 dB
Lower -77.79 dB
Upper -78.31 dB
Figure 53. DAC Driven by Lab Source and CDCM6208V2G in Comparison (Performance Identical)
Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208V2G compared to
driving the DAC with a perfect lab source. Therefore, the CDCM6208V2G provides sufficient low noise to drive a
245.76 MHz DAC.
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11.2.3 Application Performance Plots
11.2.3.1 Typical Device Jitter
Figure 54. Typical Device Output Phase Noise and Jitter
for 25 MHz
Figure 55. Typical Device Output Phase Noise and Jitter
for 312.5 MHz
0
156.25MHz output using 60Hz Loop
Bandwidth; Clock source is ok to be noisy,
as CDCM6208 filters the jitter out of the
noisy source; RJ=1.2ps-rms (12k-20MHz)
-20
-40
-60
156.25 MHZ
with 60 Hz BW
-80
156.25 MHZ
closed loop
-100
-120
156.25MHz output using 300kHz
-140 bandwidth; Clock source needs to
be clean (e.g. XTAL source)
RJ=265fs-rms
-160
1
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
Figure 56. Phase Noise Plot for Jitter Cleaning Mode (blue) and Synthesizer Mode (green)
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12 Power Supply Recommendations
12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
Mixing Supplies: The CDCM6208V2G incorporates a very flexible power supply architecture. Each building
block has its own power supply domain, and can be driven independently with 1.8 V, 2.5 V, or 3.3 V . This is
especially of advantage to minimize total system cost by deploying multiple low-cost LDOs instead of one, more-
expensive LDO. This also allows mixed IO supply voltages (e.g. one CMOS output with 1.8 V, another with 3.3
V) or interfacing to a SPI/I2C controller with 3.3 V supply while other blocks are driven from a lower supply
voltage to minimize power consumption. The CDCM6208V2G current consumption is practically independent of
the supply voltage, and therefore a lower supply voltage consumes lower device power. Also note that outputs
Y3:0 if used for PECL swing will provide higher output swing if the according output domains are connected to
2.5 V or 3.3 V.
Power-on Reset: The CDCM6208V2G integrates a built-in POR circuit, that holds the device in powerdown until
all input, digital, and PLL supplies have reached at least 1.06 V (min) to 1.24 V (max). After this power-on
release, device internal counters start (see previous section on device power up timing) followed by device
calibration. While the device digital circuit resets properly at this supply voltage level, the device is not ready to
calibrate at such a low voltage. Therefore, for slow power up ramps, the counters expire before the supply
voltage reaches the minimum voltage of 1.71 V. Hence for slow power-supply ramp rates, it is necessary to delay
calibration further using the PDN input.
Slow power-up supply ramp: No particular power supply sequence is required for the CDCM6208V2G.
However, it is necessary to ensure that device calibration occurs AFTER the DVDD supply as well as the
VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC supply are all operational, and the voltage on each supply is
higher than 1.45. This is best realized by delaying the PDN low-to-high transition. The PDN input incorporates a
50 kΩ resistor to DVDD. Assuming the DVDD supply ramp has a fixed time relationship to the slowest of all PLL
and input power supplies, a capacitor from PDN to GND can delay the PDN input signal sufficiently to toggle
PDN low-to-high AFTER all other supplies are stable. However, if the DVDD supply ramps much sooner than the
PLL or input supplies, additional means are necessary to prevent PDN from toggling too early. A premature
toggling of PDN would possibly result in failed PLL calibration, which can only be corrected by re-calibrating the
PLL by either toggling PDN or RESET high-low-high.
1.8ë,
2.ꢀë, or
3.3ë
ë5ë55
1.3ë
ë55_t[[1, ë55_t[[2, ë55_twL,
ꢀ0k
ë5ë55
t5b
ë55_{9/ ꢂll musꢁ rise ꢃefore t5b ꢁoggles high
0ë
ꢁ?0
/
t5b
ë5ë55
/5/a6208
ëLI(min)
ët5b
0ë
Figure 57. PDN Delay When Using Slow Ramping Power Supplies (Supply Ramp > 50 ms)
12.1.1 Fast Power-up Supply Ramp
If the supply ramp time for DVDD, VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC are faster than 50 ms from
0 V to 1.8 V, no special provisions are necessary on PDN; the PDN pin can be left floating. Even an external
capacitor to GND can be omitted in this circumstance, as the device delays calibration sufficiently by internal
means.
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Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued)
12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs
DSPs and other highly integrated processors sometimes do not permit any clock signal to be present until the
DSP power supply for the corresponding IO is also present. The CDCM6208V2G allows to either sequence
output clock signals by writing to the corresponding output enable bit through SPI/I2C, or alternatively it is
possible to connect the DSP IO supply and the CDCM6208V2G output supply together, in which case the
CDCM6208V2G output will not turn on until the DSP supply is also valid. This second implementation avoids
SPI/I2C programming.
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13 Layout
13.1 Layout Guidelines
Employing the thermally enhanced printed circuit board layout shown in Figure 58 insures good thermal
performance of the solution. Observing good thermal layout practices enables the thermal pad on the backside of
the QFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
13.2 Layout Example
Figure 58 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via pattern facilitates both considerations.
Figure 58. Recommended PCB layout of CDCM6208
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Layout Example (continued)
Figure 59 shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If
the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the
Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to
facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the
device as short as possible. Ground the other side of the capacitor using a low impedance connection to the
ground plane.
Figure 59. PCB Conceptual Layouts
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13.2.1 Reference Schematic
5
4
3
2
1
STATUS1_PIN0
SDI_SDA_PIN1
SDO_AD0_PIN2
SCS_AD1_PIN3
SCL_PIN4
REG_CAP
C82
Place 10uF close to
device pin to minimize
series resistance
10uF/6.3V
General Power supply related note:
Place all 0.1uF bypass caps as close as possible to device pins.
BLM15HD102SN1D
L1
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
1
2
VDD_PLL
C298
C283
C280
C282
C281
D
C
B
A
D
C
B
A
VDD_PLL_A
DVDD
DVDD
DVDD
DVDD
DVDD
0.1uF
100pF
0.1uF
1uF
10uF
VDD_OUT01
VDD_OUT23
PWR_MONITOR
RESET_PWR
C288
0.1uF
C279
C275
C295
Device Reset can connect to
power monitor or left unconnected;
pin has internal 150k pullup
0.1uF
1uF
0.1uF
C289
0.1uF
C284
C276
0.1uF
1uF
VDD_OUT4
VDD_OUT5
VDD_OUT6
C290
0.1uF
C285
C277
0.1uF
1uF
1
2
36
35
34
33
32
31
30
29
28
27
26
25
0.1uF
0.1uF
SI_MODE0
Y7_N
Y7_P
SI_MODE0
SDI_SDA_PIN1
SDO_AD0_PIN2
SCS_AD1_PIN3
SCL_PIN4
DSP_CLK7N
C291
0.1uF
C287
C286
SDI/SDA/PIN1
SDO/AD0/PIN2
SCS/AD1/PIN3
SCL/PIN4
DSP_CLK7P
VDD_OUT7
3
0.1uF
1uF
VDD_Y7
Y6_N
4
0.1uF
0.1uF
DSP_CLK6N
5
C292
0.1uF
C299
C300
Y6_P
DSP_CLK6P
VDD_OUT6
6
0.1uF
1uF
REF_SEL
VDD_Y6
VDD_Y5
Y5_P
REF_SEL
CDCM6208
7
VDD_PRI_IN
VDD_OUT5
DSP_CLK5N
VDD_PRI_REF
PRI_REFP
8
0.1uF
0.1uF
U1
VDD_OUT7
PRI_REFP
C301
0.1uF
C303
C302
9
PRI_REFN
Y5_N
PRI_REFN
DSP_CLK5P
VDD_OUT4
0.1uF
1uF
10
11
12
VDD_SEC_IN
VDD_SEC_REF
SEC_REFP
SEC_REFN
VDD_Y4
Y4_P
0.1uF
0.1uF
SEC_REFP
SEC_REFN
DSP_CLK4N
DSP_CLK4P
VDD_PRI_IN
Y4_N
C304
0.1uF
C305
1uF
VDD_SEC_IN
DVDD
C307
0.1uF
C308
C274
0.1uF
C293
1uF
1uF
Title
Rev
01
CDCM6208 Reference Schematic
Date:
December, 2011
2
Sheet
1
of
3
5
4
3
1
Figure 60. Schematic Page 1
Copyright © 2016, Texas Instruments Incorporated
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5
4
3
2
1
PRIMARY REFERENCE INPUT
C_PRI_P
LOOP FILTER
CLKIN_PRIP
PRI_REFP
R_PRI_PUP
C2
C1
R2
1uF
49.9
ELF
D
C
B
A
D
C
B
A
VDD_PRI_IN
R83
C296
49.9
R_PRI_PDN
1uF
R84
C_PRI_N
CLKIN_PRIN
PRI_REFN
1uF
Synthesizer mode (high loop bandwidth)
CDCM6208V1:
With C1=100pF, R2=500Ö, C2=22nF and
Internal components R3=100Ö, C3=242.5pF,
fPFD=25MHz, and ICP=2.5mA:
Loop Filter
Examples:
The following input biasing is recommended:
Loop bandwidth ~ (300kHz)
AC coupled differential signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),
target VBIAS=1.2V, therefore
for VDD_PRI/SEC=1.8V:
target VBIAS=0.9V, therefore
CDCM6208V2:
With C1=470pF, R2=560Ö, C2=100nF and
Internal components R3=100Ö, C3=242.5pF,
fPFD=30.72MHz, and ICP=2.5mA:
Loop bandwidth ~ (300kHz)
set R_PRI_PUP=5.5k, RPRI_PDN=3.14k
set R_PRI_PUP=5.5k, RPRI_PDN=5.5k
DC coupled LVDS signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),
R_PRI_PUP=5.5k, RPRI_PDN=3.14k
for VDD_PRI/SEC=1.8V:
R_PRI_PUP=5.5k, RPRI_PDN=3.14k
Jitter cleaner mode (low loop bandwidth):
CDCM6208V1:
With C1=4.7éF, R2=145Ö, C2=47éF and
Internal components R3=4.01kÖ, C3=662.5pF,
fPFD=40kHz, and ICP=500éA:
replace C_PRI_P=C_PRI_N=0Ö
Y1
DC coupled 3.3V CMOS signals:
Connect VDD_SEC_IN=3.3V,
select Reg4[7:6]=10 and/or Reg4[4:3]=10 (CMOS),
R83,R84,R85, & R86=DNI, replace C_PRI_P=C_PRI_N=0Ö
for 1.8V CMOS signals:
25MHz
GND0
Connect VDD_SEC_IN=1.8V:
4
1
3
2
3
Loop bandwidth ~ (40Hz)
CDCM6208V2:
DC coupled CML only (VDD_PRI/SEC voltage is don¬t care):
1
GND1
With C1=5éF, R2=100Ö, C2=100éF and
Internal components R3=4.01kÖ, C3=662.5pF,
select Reg4[7:6]=00 and/or Reg4[4:3]=00 (CML),
set R_PRI_PUP=0Ö, RPRI_PDN=DNI,
Replace CPRI_P=0Ö, C_PRI_N=0Ö
f
PFD=80kHz, and ICP=500éA:
NX3225GA
Loop bandwidth ~ (100Hz)
Use of Crystal on secondary reference input (VDD_SEC_IN voltage is don¬t care):
select Reg4[7:6]=11 (XTAL),
set R87=DNI, R89=DNI, R72=0Ö, R73=0Ö
C27
4pF
C28
4pF
R73
DNI
R72
DNI
SECONDARY REFERENCE INPUT
C29
0.0
R87
CLKIN_SECP
SEC_REFP
1uF
49.9
R_SEC_PUP
R_SEC_PDN
VDD_SEC_IN
R85
C297
49.9
1uF
R86
C30
1uF
0.0
CLKIN_SECN
SEC_REFN
R89
Title
Rev
CDCM6208 Reference Schematic
01
Date:
December, 2011
2
of
3
Sheet
5
4
3
2
1
Figure 61. Schematic Page 2
78
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
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ZHCSF03 –MARCH 2016
5
4
3
2
1
3.3V Power Supply
3p3V
+5V
1
5
6
7
8
C37
510pF
R40
30.9k
C34
10uF/6.3V
OUT1
OUT2
FB
EN
NR
D
D
C
B
A
2
3
4
TPS7A8001
C38
0.01uF
IN2
IN1
R1p8
0
2
2
2
VDD_PLL
VDD_OUT01
VDD_OUT23
VDD_OUT4
VDD_OUT5
1p8V
2p5V
3p3V
VDD_OUT6
VDD_OUT7
VDD_PRI_IN
VDD_SEC_IN
DVDD
1p8V
2p5V
3p3V
0
R41
10k
GND
R2p5
DNI
DNI
DNI
U6
C39
10uF/6.3V
R3p3
DNI
MANY VIAS with Heat Sink
2
2
2
2
2
2
1p8V
2p5V
3p3V
1p8V
2p5V
3p3V
0
0
DNI
DNI
DNI
DNI
2.5V Power Supply
2p5V
2
2
2
2
2
2
C
B
A
1p8V
2p5V
3p3V
1p8V
2p5V
3p3V
0
0
+5V
1
5
6
7
8
C50
750pF
R55
21k
C35
OUT1
OUT2
FB
EN
NR
DNI
DNI
DNI
DNI
2
3
4
TPS7A8001
10uF/6.3V
C48
0.01uF
IN2
IN1
R54
10k
GND
2
2
2
2
2
2
1p8V
2p5V
3p3V
1p8V
2p5V
3p3V
0
0
U7
C49
10uF/6.3V
DNI
DNI
DNI
DNI
MANY VIAS with Heat Sink
2
2
2
2
2
2
1p8V
2p5V
3p3V
1p8V
2p5V
3p3V
0
0
DNI
DNI
1.8V Power Supply
DNI
DNI
1p8V
VDD_OUT4, 5, 6, and VDD_OUT7 supply setting
reflect the CMOS signal output swing
If SPI or I2C is used, set DVDD to the same
supply voltage (e.g. 1.8V, 2.5V, or 3.3V)
+5V
1
5
6
7
8
C53
1300pF
R58
12.5k
C36
OUT1
OUT2
FB
EN
NR
2
3
4
TPS7A8001
10uF/6.3V
C51
0.01uF
IN2
IN1
Every supply can individually be connected to either 1.8V, 2.5V, or 3.3V. It is also possible to
run all IO from one single supply at 1.8V, 2.5V, or 3.3V.
R56
10k
GND
U8
C52
10uF/6.3V
MANY VIAS with Heat Sink
Title
Rev
CDCM6208 Reference Schematic
01
Date:
December, 2011
Sheet
1
3
of
3
5
4
3
2
Figure 62. Schematic Page 3
Copyright © 2016, Texas Instruments Incorporated
79
CDCM6208V2G
ZHCSF03 –MARCH 2016
www.ti.com.cn
5
4
3
2
1
HCSL connection example (DC coupled)
LVDS or LVPECL connection example (AC coupled)
RS(P)
Y4-7_HCSL_P
Y4-7_HCSL_N
TX-line 50Ö
TX-line 50Ö
PCIe_PHY_P
PCIe_PHY_N
D
0
TX-line 50Ö
TX-line 50Ö
Diff_in_P
Y0-7 LVDS_P
Y0-7 LVDS_N
RS(N)
0
1uF
1uF
5{t wiꢀh receiver inpuꢀ
ꢀerminaꢀion and self-
biasing
D
Diff_in_N
49.9
49.9
tL/e phy
Outputs 4 to 7 have option for HCSL, LVCMOS, LPCML
For HCSL, install 50 ohm termination resistors and adjust
series resistor between 0 and 33 ohms to improve ringing.
C
LVDS or LVPECL connection example (AC coupled)
TX-line 50Ö
TX-line 50Ö
Diff_in_P
Y0-7 LVDS_P
Y0-7 LVDS_N
1uF
5{t wiꢀhouꢀ receiver
inpuꢀ ꢀerminaꢀion and
self-biasing
B
B
Diff_in_N
1uF
49.9
49.9
Vbias
100n
A
A
Title
Rev
CDCM6208 Reference Schematic (Extra: output termination)
01
extra
Date:
December, 2011
2
Sheet
of
5
4
3
1
Figure 63. Schematic Page 4
80
Copyright © 2016, Texas Instruments Incorporated
CDCM6208V2G
www.ti.com.cn
ZHCSF03 –MARCH 2016
14 器件和文档支持
14.1 文档支持
14.1.1 相关文档ꢀ
应用报告《IC 封装热指标》,SPRA953.
关于 SRIO 接口,请参见《KeyStone 器件的硬件设计指南》,SPRABI2。
14.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.3 商标
KeyStone, E2E are trademarks of Texas Instruments.
I2C is a trademark of NXP B.V. Corporation.
All other trademarks are the property of their respective owners.
14.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
14.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏
版权 © 2016, Texas Instruments Incorporated
81
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCM6208V2GRGZR
CDCM6208V2GRGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
CM6208V2G
CM6208V2G
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
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PACKAGE OUTLINE
RGZ0048B
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
7.15
6.85
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
4.1 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
13
24
44X 0.5
12
25
49
SYMM
2X
5.5
0.30
0.18
36
48X
1
0.1
0.05
C B A
48
37
SYMM
PIN 1 ID
(OPTIONAL)
0.5
0.3
48X
4218795/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.1)
(1.115) TYP
(0.685)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
(1.115)
TYP
44X (0.5)
(0.685)
TYP
SYMM
49
(
0.2) TYP
VIA
(6.8)
(R0.05)
TYP
12
25
13
24
SYMM
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218795/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.37)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
44X (0.5)
(1.37)
TYP
SYMM
49
(R0.05) TYP
(6.8)
9X
METAL
TYP
(
1.17)
12
25
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4218795/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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