CDCS504TPWRQ1 [TI]
时钟缓冲器/时钟倍频器 | PW | 8 | -40 to 105;
| 型号： | CDCS504TPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 时钟缓冲器/时钟倍频器 | PW | 8 | -40 to 105 时钟 DCS 倍频器 驱动 分布式控制系统 CD 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CDCS504-Q1
ZHCSG99 –APRIL 2017
CDCS504-Q1 时钟缓冲器和时钟乘法器
1 特性
3 说明
1
•
•
符合汽车应用 标准
具有下列结果的 AEC-Q100 测试指南：
CDCS504-Q1 器件是一款带有可选频率倍乘的
LVCMOS 输入时钟缓冲器。
–
–
–
器件温度 2 级：–40°C 至 105°C 的环境运行温
度范围
CDCS504-Q1 具有输出使能引脚。
此器件在输入上接受一个 3.3V LVCMOS 信号。
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
这个输入信号由一个锁相环路 (PLL) 处理，此环路的
输出频率或者与输入频率相等或者被乘以因子 4。
器件组件充电模式 (CDM) ESD 分类等级 C3B
•
•
•
属于易用型时钟发生器器件系列的一部分
具有可选输出频率的时钟乘法器
这样一来，该器件可生成介于 2MHz 和 108MHz 之间
的输出频率。
可使用一个外部控制引脚来选择 x1 或者 x4 的频率
倍乘
独立的控制引脚可用于启用或者禁用输出。CDCS504-
Q1 器件在 3.3V 环境下工作。
•
•
•
•
•
通过控制引脚进行输出禁用
单一 3.3V 器件电源
其特征在于运行温度范围介于 -40°C 至 105°C 之间，
并采用 8 引脚 TSSOP 封装。
宽温度范围：-40°C 至 105°C
节省空间的 8 引脚薄型小外形尺寸 (TSSOP) 封装
使用 CDCS504-Q1 并借助 WEBENCH® 电源设计
器创建定制设计方案
器件信息(1)
器件型号
封装
TSSOP (8)
封装尺寸（标称值）
CDCS504-Q1
3.00mm x 4.40mm
2 应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
汽车 应用 （需要时钟
倍乘）
框图
GND
VDD
LV
CMOS
LVCMOS
IN
x1 or x4
OUT
GND
GND
FS
Control
Logic
OE
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCAS951
CDCS504-Q1
ZHCSG99 –APRIL 2017
www.ti.com.cn
目录
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics – Device Characteristics... 4
6.6 Typical Characteristics.............................................. 5
Parameter Measurement Information .................. 6
7.1 Measurement Circuits ............................................... 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
9
10 Power Supply Recommendations ....................... 9
11 Layout..................................................................... 9
11.1 Layout Guidelines ................................................... 9
11.2 Layout Example ...................................................... 9
12 器件和文档支持 ..................................................... 10
12.1 器件支持................................................................ 10
12.2 接收文档更新通知 ................................................. 10
12.3 社区资源................................................................ 10
12.4 商标....................................................................... 10
12.5 静电放电警告......................................................... 10
12.6 Glossary................................................................ 10
13 机械、封装和可订购信息....................................... 10
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2017 年 4 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
CDCS504-Q1
www.ti.com.cn
ZHCSG99 –APRIL 2017
5 Pin Configuration and Functions
PW Package
8-Pin TSSOP
Top View
IN
GND
GND
GND
1
2
3
4
8
7
6
5
VDD
OE
OUT
FS
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
FS
NO.
5
I
Frequency multiplication selection, internal pullup
Ground
GND
IN
2, 3, 4
Ground
1
7
6
8
I
LVCMOS clock input
OE
I
Output enable, internal pullup
LVCMOS clock output
OUT
VDD
O
Power
3.3-V power supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
4.6
4.6
4.6
20
UNIT
V
VDD
VIN
Vout
IIN
Supply voltage
Input voltage
V
Output voltage
V
Input current (VI < 0, VI > VDD
)
mA
mA
°C
°C
Iout
TJ
Continuous output current
50
Maximum junction temperature
Storage temperature
125
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1500
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2017, Texas Instruments Incorporated
3
CDCS504-Q1
ZHCSG99 –APRIL 2017
www.ti.com.cn
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
VDD
fIN
Supply voltage
Input frequency
3.6
27
V
FS = 0
FS = 1
2
MHz
2
27
VIL
Low-level input voltage LVCMOS
High-level input voltage LVCMOS
Input voltage threshold LVCMOS
Output load test LVCMOS
Output current
0.3 × VDD
V
V
VIH
VI
0.7 × VDD
0.5 × VDD
V
CL
15
±12
105
pF
mA
°C
IOH/IOL
TA
Operating free-air temperature
–40
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)(1)
CDCS504-Q1
THERMAL METRIC(2)
PW (TSSOP)
8 PINS
179.9
149
UNIT
°C/W
°C/W
Thermal Airflow (CFM) 0
Thermal Airflow (CFM) 150
Thermal Airflow (CFM) 250
Thermal Airflow (CFM) 500
Thermal Airflow (CFM) 0
Thermal Airflow (CFM) 150
Thermal Airflow (CFM) 250
Thermal Airflow (CFM) 500
142
High K
138
Junction-to-ambient thermal
RθJA
132
resistance
230
185
Low K
170
150
64.9
65
Junction-to-case (top) thermal
RθJC(top)
High K
Low K
resistance
69
RθJB
ψJT
Junction-to-board thermal resistance
108.7
9
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
107
RθJC(bot)
n/a
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics – Device Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fin = 3.072 MHz; FS = 1
MIN
TYP
MAX
UNIT
IDD
Device supply current
24
mA
FS = 0
2
8
27
108
10
fOUT
Output frequency
MHz
FS = 1
IIH
IIL
LVCMOS input current
LVCMOS input current
VI = VDD; VDD = 3.6 V
VI = 0 V; VDD = 3.6 V
IOH = -–0.1 mA
IOH = -–8 mA
IOH = -–12 mA
μA
μA
–10
2.9
2.4
2.2
VOH
LVCMOS high-level output voltage
V
4
Copyright © 2017, Texas Instruments Incorporated
CDCS504-Q1
www.ti.com.cn
ZHCSG99 –APRIL 2017
Electrical Characteristics – Device Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 0.1 mA
MIN
TYP
MAX
0.1
0.5
0.8
2
UNIT
VOL
LVCMOS low-level output voltage
IOL = 8 mA
IOL = 12 mA
OE = Low
V
IOZ
High-impedance-state output current
–2
μA
fout = 11.264 MHz; FS = 1,
10000 Cycles
tJIT(C-C) Cycle to cycle jitter(1)
144
ps
tr
Rise time(1)
Fall time(1)
20%–80%
20%–80%
0.65
0.55
ns
ns
tf
Odc
Output duty cycle(2)
45%
55%
(1) Measured with Test Load, see Figure 4.
(2) Not production tested.
6.6 Typical Characteristics
775
900
850
800
750
700
650
600
550
500
-40°C, 3.0 V
-40°C, 3.3 V
-40°C, 3.6 V
25°C, 3.0 V
25°C, 3.3 V
25°C, 3.6 V
85°C, 3.0 V
85°C, 3.3 V
85°C, 3.6 V
-40°C, 3.0 V
-40°C, 3.3 V
-40°C, 3.6 V
25°C, 3.0 V
25°C, 3.3 V
25°C, 3.6 V
85°C, 3.0 V
85°C, 3.3 V
85°C, 3.6 V
750
725
700
675
650
625
600
575
550
525
500
475
450
0
10 20 30 40 50 60 70 80 90 100 110
Frequency (MHz)
0
10 20 30 40 50 60 70 80 90 100 110
Frequency (MHz)
tc_D
tc_D
Figure 1. Typical Tr vs Output Frequency, VDD,
Temperature in X4 Mode
Figure 2. Typical Tf vs Output Frequency, VDD, Temperature
in X4 Mode
34
32
30
28
26
24
22
20
18
16
14
12
10
x4 Mode
x1 Mode
0
3
6
9
12
15
18
21
24
27
30
33
Freq
[MHz]
D001
VCC = 3.3 V, output loaded with test load
Figure 3. IDD vs Input Frequency
Copyright © 2017, Texas Instruments Incorporated
5
CDCS504-Q1
ZHCSG99 –APRIL 2017
www.ti.com.cn
7 Parameter Measurement Information
7.1 Measurement Circuits
VDD
1 kW
CDCS504-Q1
LVCMOS
1 kW
10 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 4. Test Load
CDCS504-Q1
LVCMOS
LVCMOS
ZL = 50 W
Series Termination
~ 18 W
Typical Driver
Impedance
~ 32 W
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Load for 50-Ω Board Environment
6
Copyright © 2017, Texas Instruments Incorporated
CDCS504-Q1
www.ti.com.cn
ZHCSG99 –APRIL 2017
8 Detailed Description
8.1 Overview
The CDCS504-Q1 is a LVCMOS clock buffer (x1 mode) or quadrupler (x4 mode). It integrates an internal PLL
and generates a LVCMOS clock frequency range from 2 MHz to 108 MHz.
8.2 Functional Block Diagram
VDD
GND
8
4
LVCMOS
IN
1
LVCMOS
PLL
6 OUT
FS
5
Control Logic
2
3
7
GND
GND
OE
Copyright © 2017, Texas Instruments Incorporated
8.3 Feature Description
The CDCS504-Q1 is qualified for automotive applications with AEC-Q100 test, which could support wide
temperature range from –40°C to 105°C. The device is easy to use, only need single 3.3-V power supply. The
output enable or disable mode, along with frequency multiplication, could be controlled by external controls pins.
8.4 Device Functional Modes
When pin 7 OE is in low, the CDCS504-Q1 outputs 3-state. When pin 7 OE is set in high, the device would
output clocks, output frequency depends on pin 5 FS status. FS = high enables frequency ×4 mode. FS= low
makes output frequency equal to input frequency. If no input clock is provided, it is recommended to set OE=low
in order to avoid random clock pulses from the internal PLL at the outputs.
Table 1. Function Table
OE
0
FS
x
fOUT/fIN
fOUT at fin = 27 MHz
3-state
x
1
4
1
0
27 MHz
1
1
108 MHz
Copyright © 2017, Texas Instruments Incorporated
7
CDCS504-Q1
ZHCSG99 –APRIL 2017
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCS504-Q1 is a clock buffer or multiplier for automotive amplifiers and infotainment. It is fit for the
TAS6424-Q1, a four-channel, class-D, digital-input audio-amplifier, when the applications are without available
MCLK. See Figure 6 for more details.
9.2 Typical Application
SCLK
(2.816 MHz)
CDCS504-Q1
MCLK
(11.264 MHz)
SCLK
(2.816 MHz)
Audio DSP
TAS6424
Other Signals
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Clock for Automotive Amplifiers
9.2.1 Design Requirements
The CDCS504-Q1 is supplied with a single-power 3.3 V. The device supports minimum input frequency to 2
MHz. For maximum input frequency, it is 32 MHz in ×1 mode, and 27 MHz in ×4 mode. The input clock is
LVCMOS type and should satisfy requirements in the Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
In some applications, the clock input for CDCS504-Q1 is not always presented. In case there is an unexpected
clock output without clock input, TI recommends setting OE pin to low. When it gets clock input ready, set OE pin
to high to get expected clock output. If the other application presents continuous clock input for CDCS504-Q1,
the OE pin could be floated, internal pullup brings output enable, or an external pullup circuits could be used
fixedly.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the CDCS504-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
8
Copyright © 2017, Texas Instruments Incorporated
CDCS504-Q1
www.ti.com.cn
ZHCSG99 –APRIL 2017
Typical Application (continued)
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.3 Application Curves
125
100
75
50
25
0
80
60
40
20
0
66.3
100.5
98.5
61.9
92.7
59.2
91.1
56.4
-40
0
25
85
-40
0
25
85
ac_D
ac_D
Ta (°C)
Ta (°C)
X1 mode, 8-MHz input, 8-MHz output, VDD = 3.3 V
X4 mode, 27.5-MHz input, 110-MHz output, VDD = 3.3 V
Figure 7. Typical Cycle-to-Cycle Jitter vs Temperature
Figure 8. Typical Cycle-to-Cycle Jitter vs Temperature
10 Power Supply Recommendations
The CDCS504-Q1 requires a 3.3-V supply.
11 Layout
11.1 Layout Guidelines
The CDCS504-Q1 only has typical 20-mA supply current, so there is no thermal design challenge. A 0.01-µF
capacitor may be placed close to VDD pin as a bypass capacitor.
11.2 Layout Example
Figure 9. Layout Example
版权 © 2017, Texas Instruments Incorporated
9
CDCS504-Q1
ZHCSG99 –APRIL 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 使用 WEBENCH® 工具定制设计方案
请单击此处，借助 WEBENCH® 电源设计器并使用 CDCS504-Q1 器件创建定制设计方案。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每周定
期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
10
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCS504TPWRQ1
ACTIVE
TSSOP
PW
8
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
CS504Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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