CDCV304-EP_18 [TI]
200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT;
| 型号： | CDCV304-EP_18 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT PC |
| 文件： | 总13页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCV304-EP
www.ti.com
SCAS927A –MARCH 2012
200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT
Check for Samples: CDCV304-EP
1
FEATURES
•
General-Purpose and PCI-X 1:4 Clock Buffer
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
Operating Frequency
•
•
•
•
•
•
•
Controlled Baseline
–
0 MHz to 200 MHz General-Purpose
One Assembly/Test Site
•
•
Low Output Skew: <100 ps
One Fabrication Site
Distributes One Clock Input to One Bank of
Four Outputs
Available in –40°C/105°C Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
Output Enable Control that Drives Outputs
Low when OE is Low
Operates from Single 3.3-V Supply or 2.5-V
Supply
TSSOP
PW PACKAGE
(TOP VIEW)
•
•
PCI-X Compliant
8-Pin TSSOP Package
1
2
3
4
8
7
6
5
CLKIN
OE
1Y0
GND
1Y3
1Y2
VDD
1Y1
(1) Custom temperature ranges available
DESCRIPTION
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one
input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X
applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X
specifications.
The CDCV304 is characterized for operation from –40°C to 105°C.
Table 1. FUNCTION TABLE
FUNCTIONAL BLOCK DIAGRAM
INPUTS
OUTPUTS
Logic
Control
2
OE
CLKIN
OE
L
1Y[0:3]
L
H
L
L
L
3
5
1
L
1Y0
1Y1
CLKIN
H
L
H
H
H
7
8
1Y2
1Y3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
CDCV304-EP
SCAS927A –MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 2. ORDERING INFORMATION(1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
–40°C to 105°C
TSSOP - PW
CDCV304TPWREP
C304T
V62/12618-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
1Y[0:3]
CLKIN
GND
OE
NO.
3, 5, 7, 8
O
Buffered output clocks
Input reference frequency
Ground
1
4
2
6
I
Power
I
Output enable control
Supply
VDD
Power
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
–0.5 V to 4.3 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
Supply voltage range, VDD
(2) (3)
Input voltage range, VI
(2) (3)
Output voltage range, VO
Input clamp current, IIK (VI < 0 or VI> VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
)
±50 mA
Continuous total output current, IO (VO = 0 to VDD
)
±50 mA
Storage temperature range Tstg
–65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
2
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): CDCV304-EP
CDCV304-EP
www.ti.com
SCAS927A –MARCH 2012
THERMAL INFORMATION
CDCV304
THERMAL METRIC(1)
PW
8 PINS
175.8
61.8
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
θJCtop
θJB
104.3
7.7
°C/W
ψJT
ψJB
102.6
xxx
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
Supply voltage, VDD
2.3
3.6
V
V
V
V
Low-level input voltage, VIL
High-level input voltage, VIH
Input voltage, VI
0.3 x VDD
0.7 x VDD
0
VDD
–12
–24
12
VDD = 2.5 V
VDD = 3.3 V
VDD = 2.5 V
VDD = 3.3 V
High-level output current, IOH
mA
Low-level output current, IOL
mA
°C
24
Operating free-air temperature, TA
–40
105
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
Clock frequency
0
200
MHz
Copyright © 2012, Texas Instruments Incorporated
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SCAS927A –MARCH 2012
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
VDD = 3 V,
II = –18 mA
IOH = –1 mA
IOH = –8 mA
IOH = –24 mA
IOH = –12 mA
IOL = 8 mA
IOL = 1 mA
IOL = 24 mA
IOL = 12 mA
VO = 1 V
–1.2
V
VDD = min to max,
VDD = 2.3 V,
VDD = 3 V,
VDD – 0.3
1.78
1.90
2.30
VOH
High-level output voltage
V
VDD = 3 V,
VDD = 2.3 V,
VDD = min to max,
VDD = 3 V,
0.51
0.20
0.84
0.60
VOL
Low-level output voltage
High-level output current
V
VDD = 3 V,
VDD = 3 V,
–45
54
IOH
mA
VDD = 3.3 V,
VDD = 3 V,
VO = 1.65 V
VO = 2 V
–55
70
IOL
II
Low-level output current
Input current
mA
μA
VDD = 3.3 V,
VI = VO or VDD
f = 67 MHz,
f = 67 MHz,
VDD = 3.3 V,
VDD = 3.3 V,
VO = 1.65 V
±5
28
37
VDD = 2.7 V
IDD
Dynamic current, see
mA
VDD = 3.6 V
CI
Input capacitance
Output capacitance
VI = 0 V or VDD
VI = 0 V or VDD
3
pF
pF
CO
3.2
(1) All typical values are with respect to nominal VDD and TA = 25°C.
4
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CDCV304-EP
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SCAS927A –MARCH 2012
SWITCHING CHARACTERISTICS
VDD = 2.5 V ± 10%, CL= 10 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1 and Figure 2
See Figure 3
MIN
2
TYP(1)
MAX UNIT
tPLH
tPHL
tsk(o)
tr
Low-to-high propagation delay
High-to-low propagation delay
Output skew(2)
Output rise slew rate(3)
Output fall slew rate(3)
2.9
3
4.5
ns
2
4.5
50
2.2
2.2
150
4
ps
1
1
V/ns
V/ns
tf
4
(1) All typical values are with respect to nominal VDD
.
(2) The tsk(o) specification is only valid for equal loading of all outputs and TA = -40°C to 85°C.
(3) This symbol is according to PCI-X terminology.
SWITCHING CHARACTERISTICS
VDD = 3.3 V ± 10%, CL= 10 pF (unless otherwise noted)
PARAMETER
Low-to-high propagation delay
High-to-low propagation delay
Output skew(2)
TEST CONDITIONS
MIN
1.8
TYP(1)
2.4
MAX UNIT
tPLH
tPHL
tsk(o)
3.8
ns
See Figure 1 and Figure 2
1.8
2.5
3.8
50
100
ps
12 kHz to 5 MHz, fout = 30.72 MHz
12 kHz to 20 MHz, fout = 125 MHz
VIH = VDD, VIL = 0 V
63
tjitter
Additive phase jitter from input to output 1Y0
fs rms
56
tsk(p)
Pulse skew
180
0.2
ps
ns
ns
tsk(pr)
tsk(pp)
Process skew
Part-to-part skew
0.25
66 MHz
140 MHz
66 MHz
140 MHz
6
2.2
6
thigh
Clock high time, see Figure 4
ns
ns
tlow
Clock low time, see Figure 4
3
tr
tf
Output rise slew rate(3)
Output fall slew rate(3)
1
2.7
2.7
4
4
V/ns
V/ns
1
(1) All typical values are with respect to nominal VDD
.
(2) The tsk(o) specification is only valid for equal loading of all outputs and and TA = -40°C to 85°C.
(3) This symbol is according to PCI-X terminology.
Copyright © 2012, Texas Instruments Incorporated
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CDCV304-EP
SCAS927A –MARCH 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
DD
140 Ω
Y
n
10 pF
140 Ω
Figure 1. Test Load Circuit
V
DD
50% V
DD
CLKIN
0 V
t
t
PLH
PHL
V
OH
0.6 V
0.6 V
DD
DD
50% V
50% V
DD
DD
0.2 V
0.2 V
DD
DD
1Y0 − 1Y3
V
OL
t
r
t
f
Figure 2. Voltage Waveforms Propagation Delay (tpd) Measurements
50% V
DD
Any Y
Any Y
50% V
DD
t
sk(0)
Figure 3. Output Skew
t
cyc
t
PARAMETER
VALUE
UNIT
V
high
V
0.5 V
IH(Min)
DD
DD
DD
0.6 V
DD
V
IH(Min)
V
0.35 V
V
V
IL(Max)
t
low
V
test
V
test
0.4 V
V
IL(Max)
0.2 V
DD
0.4 V
DD
Peak to Peak (Minimum)
A. All parameters in Figure 4 are according to PCI-X 1.0 specifications.
Figure 4. Clock Waveform
6
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Product Folder Link(s): CDCV304-EP
CDCV304-EP
www.ti.com
SCAS927A –MARCH 2012
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
T
A
= 3.3 V
= 25°C
DD
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
I
− High-Level Output Current − mA
OH
Figure 5.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
T
A
= 3.3 V
= 25°C
DD
−20
0
20
40
60
80
100
120
I
− Low-Level Output Current − mA
OL
Figure 6.
Copyright © 2012, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCV304TPWREP
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCV304-EP :
Catalog: CDCV304
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCV304TPWREP
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
CDCV304TPWREP
8
2000
Pack Materials-Page 2
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