CDCVF111FN [TI]
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER; 1 ： 9差分LVPECL时钟驱动器
| 型号： | CDCVF111FN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
FN PACKAGE
(TOP VIEW)
D
D
D
D
Low-Output Skew for Clock-Distribution
Applications
Differential Low-Voltage Pseudo-ECL
(LVPECL) Compatible Inputs and Outputs
Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
4
3
2 1 28 27 26
5
25
24
23
22
21
20
19
Y8
Y8
Y7
Y0
Y0
Y1
Output Reference Voltage (V
) Allows
6
REF
Distribution From a Single-Ended Clock
Input
7
8
V
V
CC
Y7
Y6
Y6
CC
9
D
Packaged In a 28-Pin Plastic Chip Carrier
Y1
Y2
Y2
10
11
description
1213 14 15 16 17 18
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-Ω transmission lines.
NC – No internal connection
The V
output can be strapped to the CLKIN input for a single-ended CLKIN input.
REF
The CDCVF111 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLKIN CLKIN
Yn
L
Yn
H
H
L
X
L
X
H
L
L
H
L
H
L
V
V
H
L
REF
H
H
H
L
REF
L
V
V
L
REF
H
H
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
logic diagram (positive logic)
25
24
Y0
Y0
23
21
Y1
Y1
20
19
Y2
Y2
18
17
Y3
Y3
28
CLKIN
2
16
14
Y4
Y4
CLKIN
13
12
Y5
Y5
11
10
Y6
Y6
9
7
Y7
Y7
6
5
Y8
Y8
3
V
REF
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 mW
Storage temperature range, T
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 mA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
recommended operating conditions
MIN
MAX
UNIT
V
V
V
Supply voltage
3
3.6
CC
V
CC
V
CC
V
CC
V
CC
= 3 V to 3.6 V
= 3.3 V
V
–1.165
V
–0.88
V
CC
2.135
–1.81
CC
2.42
–1.475
High-level input voltage
IH
V
= 3 V to 3.6 V
= 3.3 V
V
V
V
CC
1.49
–40
CC
1.825
V
IL
Low-level input voltage
V
T
A
Operating free-air temperature
Input frequency
85
650
°C
MHz
f
clock
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
= 3 V to 3.6 V
MIN
–1.38
MAX
–1.26
UNIT
V
CC
V
CC
V
CC
V
V
CC
1.92
CC
2.04
V
REF
I
= 100 µA
V
REF
= 3.3 V
= 3 V to 3.6 V,
T
= 0°C to 85°C,
V
–1.12
V
V
–0.83
A
CC
CC
CC
f
= 650 MHz
(max)
V
= 3 V to 3.6 V,
V
OH
CC
T
= –40°C to 85°C,
V
–1.15
–0.83
A
(max)
CC
f
= 650 MHz
V
V
= 3.3 V
2.275
2.42
CC
V
= 3 V to 3.6 V
CC
T
= 0°C to 85°C,
V
V
–1.86
V
V
–1.49
–1.52
A
CC
CC
f
= 650 MHz
(max)
V
= 3 V to 3.6 V,
V
OL
CC
T
= –40°C to 85°C,
–1.86
A
(max)
CC
CC
f
= 650 MHz
V
CC
= 3.3 V
1.49
1.68
I
I
V = 2.4 V,
V
V
= 3 .6 V
= 3 .6 V
150
100
µA
I
I
CC
(Internal)
I
O
= 0,
mA
CC
CC
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (see Figure 1 and Figure 2)
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
PLH
PHL
sk(o)
CLKIN, CLKIN
450
600
ps
Y, Y
Y, Y
Y, Y
50
ps
ps
t
150
sk(pr)
t
r
f
Y, Y
200
600
ps
t
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
ESD information
ESD MODELS
Human Body Model (HBM)
LIMIT
2.0 kV
200 V
2.0 kV
Machine Model (MM)
Charge Device Model (CDM)
thermal information
THERMAL AIR FLOW (CFM)
CDCVF111 28-PIN PLCC
UNIT
0
150
44
250
42
500
39
R
R
R
R
High K
Low K
High K
Low K
48
70
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
θJC
58
52
46
22
28
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2 V
Oscilloscope
LVPECL
Driver
Z
Z
= 50 Ω
= 50 Ω
O
Yn
Yn
50 Ω
O
50 Ω
V
EE
= –1.3 V
LOAD CIRCUIT (See Note B)
80% 80%
V
OH
Y, Y
Outputs
20%
20%
V
OL
t
t
f
r
VOLTAGE WAVEFORMS
RISE AND FALL TIMES
CLKIN
V
V
– 0.9 V
CC
– 1.7 V
CLKIN
t
CC
t
PLH
PHL
V
V
OH
Y
Outputs
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 45 MHz, Z = 50 Ω, t ≤ 1 ns, t ≤ 1 ns.
O
r
f
B. For additonal signal interface, see the Interfacing Between LVPECL, LVDS, and CML application note, Literature Number
SCAA056.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
CLKIN
CLKIN
Y0
Y0
Y1
Y1
Y2
Y2
t
t
t
t
PLH1
PLH2
PHL1
PHL2
t
t
t
t
t
PLH3
PLH4
PLH5
PHL3
PHL4
Y3
Y3
Y4
Y4
Y5
t
t
t
PHL5
PHL6
PHL7
Y5
Y6
t
t
PLH6
PLH7
Y6
Y7
Y7
Y8
t
t
t
t
PLH8
PLH9
PHL8
Y8
PHL9
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest t
– The difference between the fastest and slowest t
(n = 1, 2, . . . 9)
(n = 1, 2, . . . 9)
PLHn
PHLn
B. Process skew, t
, is calculated as the greater of:
sk(pr)
– The difference between the fastest and slowest t
– The difference between the fastest and slowest t
(n = 1, 2, . . . 9)
(n = 1, 2, . . . 9) across multiple devices
PLHn
PHLn
C. For additional information on skew and propagation delay parameters, see the Defining Skew, Propagation Delay, Phase-Offset
(Phase Error) application note, literature number SCAA055.
Figure 2. Waveforms for Calculation of t
, t
sk(o) sk(pr)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF111
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PLCC
Drawing
CDCVF111FN
ACTIVE
ACTIVE
FN
28
28
37
TBD
TBD
CU
CU
Level-1-220C-UNLIM
Level-1-220C-UNLIM
CDCVF111FNR
FN
750
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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