CDCVF857 [TI]
2.5-V PHASE-LOCK LOOP CLOCK DRIVER; 2.5 -V锁相环时钟驱动器
| 型号： | CDCVF857 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| 文件： | 总19页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇ ꢈꢅ ꢉꢂ ꢊꢋꢌ ꢍꢎꢉꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢊ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢂ ꢎꢒ
SCAS047D − MARCH 2003 − REVISED JUNE 2005
D
Recommended Applications:
− DDR Memory Modules
(DDR400/333/266/200)
D
Operates From Dual 2.6-V or 2.5-V Supplies
D
Available in a 40-Pin MLF Package, 48-Pin
TSSOP Package, 56-Ball MicroStar Junior
BGA Package
− Zero Delay Fan-Out Buffer
D
D
D
D
D
D
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): 35 ps
Low Static Phase Offset: 50 ps
Low Jitter (Period): 30 ps
D
D
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
D
Meets/Exceeds JEDEC Standard
(JESD82−1) For DDRI-200/266/333
Specification
1-To-10 Differential Clock Distribution
(SSTL2)
D
D
Meets/Exceeds Proposed DDRI-400
Specification (JESD82−1A)
D
Best in Class for V
= V /2 0.1 V
OX DD
Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
description
The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, the outputs switch in phase
DD
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able
DD
to track spread spectrum clocking for reduced EMI.
Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial
and industrial temperature ranges.
AVAILABLE OPTIONS
†
T
A
TSSOP (DGG)
40-Pin MLF
56-Ball BGA
CDCVF857DGG
(Pb-Free)
−40°C to 85°C
−40°C to 85°C
CDCVF857RTB
CDCVF857GQL
CDCVF857RHA
(Pb-Free, Green)
†
Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum T allowed is 70°C.
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
Y[0:9] FBOUT
PLL
AV
DD
PWRDWN
CLK
L
CLK
Y[0:9]
FBOUT
GND
GND
H
H
L
H
L
L
H
Z
Z
L
H
L
L
H
Z
Z
L
H
L
Bypassed/Off
H
Bypassed/Off
X
L
H
L
Z
Z
H
L
Z
Z
H
L
Off
Off
On
On
Off
X
L
H
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
H
H
X
L
H
L
H
H
Z
H
Z
<20 MHz <20 MHz
Z
Z
DGG PACKAGE (TSSOP)
(TOP VIEW)
GND
Y0
GND
1
48
47
46
45
44
43
Y5
Y5
V
2
RHA/RTB PACKAGE (MLF)
(TOP VIEW)
Y0
3
V
4
DDQ
Y1
DDQ
Y6
Y6
5
Y1
GND
GND
Y2
6
7
42 GND
41 GND
40 Y7
40 39 38 37 36 35 34 33 32 31
8
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
GND
Y7
Y7
V
9
Y2
Y2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y2
Y7
V
V
DDQ
DDQ
DDQ
V
V
PWRDWN
FBIN
V
PWRDWN
FBIN
DDQ
CLK
DDQ
CLK
GND
CLK
FBIN
CLK
FBIN
V
V
V
DDQ
DDQ
DDQ
DDQ
AV
V
AV
FBOUT
FBOUT
GND
Y8
DD
DDQ
DD
AGND
GND
FBOUT
FBOUT
AGND
GND
Y3
11 12 13 14 15 16 17 18 19 20
Y3
Y8
V
V
DDQ
Y4
DDQ
Y9
Y4
Y9
40-pin HP-VFQFP-N (6,0 x 6,0-mm Body Size,
0,5-mm Pitch, M0#220, Variation VJJD-2,
E2 = D2 = 2,9 mm 0,15 mm) Package Pinouts
GND
GND
48-pin TSSOP (MO-153-ED)
2
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
MicroStar Junior BGA (GQL) Package
(TOP VIEW)
1
2
3
4
5
6
A
B
C
Y6
Y6
Y1
Y1
NC
NC
NC
GND
GND
GND
GND
D
E
F
NC
NB
NB
Y7
Y7
Y2
Y2
PWRDN
V
V
DDQ
DDQ
V
DDQ
NB
NC
NC
FBIN
FBIN
CLK
CLK
G
H
J
NC
NC
V
DDQ
V
DDQ
AV
DD
FBOUT
FBOUT
GND
AGND
GND
Y8
Y8
Y3
Y3
K
NB = No ball
NC = No connection
3
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
functional block diagram
3
2
Y0
Y0
5
6
Y1
Y1
37
PWRDWN
Power Down
and Test
Logic
16
AV
DD
10
9
Y2
Y2
20
19
Y3
Y3
22
23
Y4
Y4
46
47
Y5
Y5
13
14
CLK
CLK
44
43
Y6
Y6
PLL
FBIN 36
39
40
Y7
Y7
35
FBIN
29
30
Y8
Y8
27
26
Y9
Y9
32
33
FBOUT
FBOUT
4
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
Terminal Functions
TERMINAL
RHA/RTB
I/O
DESCRIPTION
NAME
AGND
AV
DGG
17
GQL
H1
9
Ground for 2.5-V analog supply
2.5-V analog supply
16
8
G2
DD
CLK, CLK
13, 14
35, 36
32, 33
5, 6
F1, F2
F5, F6
H6, G5
I
I
Differential clock input
FBIN, FBIN
FBOUT, FBOUT
25, 26
21, 22
Feedback differential clock input
Feedback differential clock output
O
1, 7, 8, 18, 24,
25, 31, 41, 42, 48
A3, A4, C1, C2, C5,
C6, H2, H5, K3, K4
GND
1, 10
27
Ground
PWRDWN
37
E6
I
Output enable for Y and Y
2.5-V supply
4, 11, 12, 15, 21,
28, 34, 38, 45
4, 7, 13, 18, 23,
24, 28, 33, 38
B3, B4, E1, E2, E5,
G1, G6, J3, J4
V
DDQ
Y0, Y0
Y1, Y1
Y2, Y2
Y3, Y3
Y4, Y4
Y5, Y5
Y6, Y6
Y7, Y7
Y8, Y8
Y9, Y9
3, 2
37, 36
39, 40
3, 2
A1, A2
B2, B1
D1, D2
J2, J1
O
O
O
O
O
O
O
O
O
O
5, 6
10, 9
20, 19
22, 23
46, 47
44, 43
39, 40
29, 30
27, 26
12,11
14, 15
34, 35
32, 31
29, 30
19, 20
17, 16
K1, K2
A6, A5
B5, B6
D6, D5
J5, J6
Buffered output copies of input clock, CLK, CLK
K6, K5
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
,
DDQ
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
DDQ
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
I
DDQ
O
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O
DDQ
Continuous output current, I (V = 0 to V
Continuous current to GND or V
Storage temperature range T
O
O
DDQ
DDQ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
q
For TSSOP (DGG) Package (see Note 3)
q
For MLF (RHA/RTB) Package
q
JA
For BGA(GQL) Package (see Note 4)
JA
Airflow
JA
Low K
High K
70°C/W
Airflow
0 ft/min
With 4 Thermal Vias
Airflow
High K
0 ft/min
89.1°C/W
78.5°C/W
44.7°C/W
0 ft/min
132.2°C/W
126.4°C/W
150 ft/min
65.3°C/W
150 ft/min
150 ft/min
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4. Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the θ to 114.8°C/W (0 airflow).
JA
5
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
recommended operating conditions (see Note 5)
MIN
2.3
TYP
MAX UNIT
V
PC1600 − PC3200
2.7
DDQ
AV
Supply voltage
V
V
DDQ
− 0.12
2.7
DD
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 – 0.18
Low-level input voltage, V
V
IL
−0.3
0.7
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 + 0.18
1.7
High-level input voltage, V
IH
V
V
V
DDQ
V
DDQ
V
DDQ
V
DDQ
+ 0.3
+ 0.3
+ 0.6
+ 0.6
DC input signal voltage (see Note 5)
–0.3
0.36
0.7
dc
ac
CLK, FBIN
CLK, FBIN
Differential input signal voltage, V (see Note 6)
ID
V
Input differential pair cross voltage, V (see Notes 7 and 8)
IX
V
DDQ
/2 – 0.2
V
DDQ
/2 + 0.2
−12
12
V
High-level output current, I
mA
mA
V/ns
°C
OH
Low-level output current, I
Input slew rate, SR
OL
1
4
Operating free-air temperature, T
−40
85
A
NOTES: 5. The unused inputs must be held high or low to prevent them from floating.
6. The dc input signal voltage specifies the allowable dc execution of the differential input.
7. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
8. The differential cross-point voltage is expected to track variations of V
be crossing.
and is the voltage at which the differential signals must
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 2.3 V, I = –18 mA
MIN
TYP
MAX UNIT
V
V
All inputs
V
V
V
V
V
–1.2
V
IK
DDQ
DDQ
DDQ
DDQ
DDQ
I
= min to max, I
= –1 mA
= –12 mA
V
– 0.1
1.7
OH
DDQ
High-level output voltage
Low-level output voltage
V
OH
= 2.3 V, I
OH
= min to max, I
= 1 mA
= 12 mA
0.1
0.6
OL
V
OL
V
V
= 2.3 V, I
OL
}
V
V
Output voltage swing
1.1
V
– 0.4
OD
Differential outputs are terminated with
DDQ
w
120 Ω /C = 14 pF (See Figure 3)
Output differential cross-voltage
Input current
V
/2 – 0.1
V
/2
V
/2 + 0.1
10
L
OX
DDQ
DDQ
DDQ
I
I
V
V
= 2.7 V, V = 0 V to 2.7 V
µA
µA
I
DDQ
I
High-impedance state output current
Power-down current on
= 2.7 V, V = V
DDQ
or GND
10
OZ
DDQ
O
CLK and CLK = 0 MHz;
I
20
100
µA
DDPD
V
DDQ
+ AV
DD
PWRDWN = Low; Σ of I
and AI
DD
DD
f
= 170 MHz
= 200 MHz
6
8
8
10
O
O
AI
DD
Supply current on AV
Input capacitance
mA
pF
DD
f
C
V
= 2.5 V, V = V
or GND
2
2.5
3.5
I
DDQ
I
DDQ
†
‡
All typical values are at a respective nominal V
The differential output signal voltage specifies the differential voltage VTR − VCP, where VTR is the true output level and VCP is the
.
DDQ
complementary output level.
The differential cross-point voltage is expected to track variations of V
DDQ
§
and is the voltage at which the differential signals must be crossing.
6
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
140
150
270
280
330
350
1
UNIT
f
O
f
O
f
O
f
O
f
O
f
O
= 170 MHz
= 200 MHz
= 170 MHz
= 200 MHz
= 170 MHz
= 200 MHz
120
125
220
230
280
300
Without load
Differential outputs terminated with
I
Dynamic current on V
mA
DD
DDQ
120 Ω/C = 0 pF
L
Differential outputs terminated with
120 Ω/C = 14 pF
L
∆C
Part-to-part input capacitance variation
V
DDQ
= 2.5 V, V = V
I
or GND
or GND
pF
pF
DDQ
Input capacitance difference between
CLK and CKB, FBIN, and FBINB
C
V
= 2.5 V, V = V
I
0.25
I(∆)
DDQ
.
DDQ
†
All typical values are at a respective nominal V
DDQ
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
60
MAX
220
220
60%
10
UNIT
Operating clock frequency
Application clock frequency
Input clock duty cycle
f
MHz
CLK
90
40%
{
Stabilization time (PLL mode)
µs
}
Stabilization time (bypass mode)
30
ns
†
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and V must be applied. Until phase lock is obtained, the specifications
DD
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
‡
switching characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
3.5
MAX
UNIT
ns
w
t
t
Low-to-high level propagation delay time Test mode/CLK to any output
High-to-low level propagation delay time Test mode/CLK to any output
PLH
PHL
w
3.5
ns
100 MHz (PC1600)
−65
−30
−50
−35
−100
−75
1
65
30
50
35
100
75
2
t
t
t
Jitter (period), See Figure 7
ps
ps
ps
jit(per)
jit(cc)
133/167/200 MHz (PC2100/2700/3200)
100 MHz (PC1600)
Jitter (cycle-to-cycle), See Figure 4
Half-period jitter, See Figure 8
133/167/200 MHz (PC2100/2700/3200)
100 MHz (PC1600)
jit(hper)
133/167/200 MHz (PC2100/2700/3200)
Load: 120 Ω/14 pF
t
t
Output clock slew rate, See Figure 9
Static phase offset, See Figure 5
Output skew, See Figure 6
V/ns
ps
slr(o)
100/133/167/200 MHz
–50
50
40
(Ø)
tsk
Load: 120 Ω/14 pF 100/133/167/200 MHz
ps
(o)
§
¶
Refers to the transition of the noninverting output.
This parameter is assured by design but can not be 100% production tested.
7
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
V
DD
V
Yx
R = 60 Ω
R = 60 Ω
V
DD
/2
V
Yx
CDCVF857
GND
Figure 1. IBIS Model Output Load
V
DD
/2
SCOPE
−V /2
DD
CDCVF857
C = 14 pF
Z = 50 Ω
R = 10 Ω
Z = 60 Ω
R = 50 Ω
(TT)
V
Z = 50 Ω
Z = 60 Ω
R = 10 Ω
R = 50 Ω
C = 14 pF
V
(TT)
−V /2
DD
V
(TT)
= GND
−V /2
DD
Figure 2. Output Load Test Circuit
8
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ꢇ
SCAS047D − MARCH 2003 − REVISED JUNE 2005
V
DD
PROBE
CDCVF857
C = 14 pF
GND
Z = 60 Ω
Z = 60 Ω
C = 1 pF
R = 1 MΩ
R = 120 Ω
V
(TT)
C = 1 pF
C = 14 pF
R = 1 MΩ
V
(TT)
GND
V
(TT)
= GND
GND
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
t
t
c(n+1)
c(n)
t
= t
− t
jit(cc) c(n) c(n+1)
Figure 4. Cycle-to-Cycle Jitter
9
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t
t
(
) n
(
) n+1
n = N
1
∑
t
(
) n
t
=
)
(
N
(N > 1000 Samples)
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t
sk(o)
Figure 6. Output Skew
10
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
t
c(n)
Yx, FBOUT
Yx, FBOUT
1
f
o
1
t
= t −
jit(per) cn
f
= Average input frequency measured at CLK/CLK
O
f
o
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t
t
(hper_n+1)
(hper_n)
1
f
o
n = any half cycle
1
t
= t
jit(hper) (hper_n) −
f
= Average input frequency measured at CLK/CLK
O
2xf
o
Figure 8. Half-Period Jitter
V , V
OH IH
80%
80%
20%
20%
20%
Clock Inputs
and Outputs
V , V
OL IL
t
t
f
r
V
* V
V
* V
80%
t
20%
80%
+
t
+
t
slr(IńO)
slf(IńO)
t
r(IńO)
f(IńO)
Figure 9. Input and Output Slew Rates
11
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
Bead
CARD
0603
VIA
AV DD
V
DDQ
0.1 uF
0603
4.7 uF
1206
2200 pF
0603
PLL
GND
AGND
CARD
VIA
See Notes 9, 10, and 11
Figure 10. Recommended AV
Filtering
DD
NOTES: 9. Place the 2200-pF capacitor close to the PLL.
10. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND
via (farthest from the PLL).
11. Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
12
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
THERMAL INFORMATION
This package incorporates an exposed thermal pad that is designed to be attached directly to an external
heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB), the PCB can be used
as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground
plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report,
Quad Flatpack No-Lead Packages, Texas Instruments Literature No. SCBA017. This document is available at
www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
13
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
CDCVF857DGG
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CDCVF857DGGG4
CDCVF857DGGR
CDCVF857DGGRG4
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CDCVF857GQLR
CDCVF857RHAR
ACTIVE
ACTIVE
VFBGA
QFN
GQL
RHA
56
40
1000
TBD
Call TI
Level-2A-220C-4 WKS
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
CDCVF857RHARG4
CDCVF857RHAT
ACTIVE
ACTIVE
ACTIVE
QFN
QFN
QFN
RHA
RHA
RHA
40
40
40
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
CDCVF857RHATG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
CDCVF857RTBR
CDCVF857RTBT
ACTIVE
ACTIVE
QFN
QFN
RTB
RTB
40
40
2500
250
TBD
TBD
CU SNPB
CU SNPB
Level-3-235C-168 HR
Level-3-235C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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Copyright 2005, Texas Instruments Incorporated
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