CLC114AE-QML [TI]
IC QUAD BUFFER AMPLIFIER, CQCC20, LCC-20, Buffer Amplifier;
| 型号： | CLC114AE-QML |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC QUAD BUFFER AMPLIFIER, CQCC20, LCC-20, Buffer Amplifier 放大器 |
| 文件： | 总10页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2001
CLC114
Quad, Low Power Video Buffer
n 450V/us slew rate
n Low power, 30mW per channel ( 5V sup.)
n 62dB channel isolation (10MHz)
n Specified for crosspoint switch loads
General Description
±
The CLC114 is a high performance, close loop quad buffer
intended for power sensitive applications. Requiring only
30mW of quiescent power dissipation per channel ( 5V
±
supplies), the CLC114 offers a small signal bandwidth of
200MHz (0.5Vpp) and a slew rate of 450V/µs.
Applications
n Video crosspoint switch driver
n Video distribution buffer
n Video switching buffer
n Video signaling multiplexing
n Instrumentation amps
n Active filters
Designed specifically for high density crosspoint switch and
analog multiplexer applications, the CLC114 offers excellent
@
linearity and wide channel isolation (62dB 10MHz). Driving
a typical crosspoint switch load, the CLC114 offers differen-
tial gain and phase performance of 0.08% and 0.1% gain
flatness through 30MHz is typically 0.1dB.
With its patented closed loop topology , the CLC114 has
significant performance advantages over conventional open
loop designs. Applications requiring low output impedance
and true unity gain stability through very high frequencies
(active filters, dynamic load buffering, etc.) Will benefit from
the CLC114’s superior performance.
Small Signal Pulse Response
Constructed using an advanced, complementary bipolar pro-
cess and National’s proven high speed architectures, the
CLC114 is available in several versions to meet a variety of
requirements.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-92339
*
*
Space level versions also available.
For more information, visit http://www.national/com/mil
Features
n Closed loop, quad buffer
n 200MHz small signal bandwidth
DS012738-10
Typical Application
DS012738-21
© 2001 National Semiconductor Corporation
DS012738
www.national.com
Connection Diagram
DS012738-3
Pinout
Ordering Information
Package
Temperature Range
Part Number
Package
Marking
NSC
Drawing
N14A
Industrial
14-Pin Plastic DIP
14-Pin Plastic SOIC
−40˚C to +85˚C
−40˚C to +85˚C
CLC114AJP
CLC114AJE
CLC114AJP
CLC114AJE
M14A,B
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
ESD Rating
−40˚C to +85˚C
−65˚C to +150˚C
+300˚C
500V
±
7V
Supply Voltage (VCC
IOUT
Output is short circuit protected to
ground, but maximum reliability will
be maintained if IOUT does not
exceed...
)
Operating Ratings
Thermal Resistance
Package
MDIP
(θJC
)
(θJA)
30mA
65˚C/W
55˚C/W
115˚C/W
125˚C/W
±
Input Voltage
VCC
SOIC
Maximum Junction Temperature
+150˚C
Electrical Characteristics
±
(VCC
=
5 V, RL = 100Ω; Unless Specified)
Symbol
Parameter
Conditions
Max/Min Ratings
Typ
Units
(Note 2)
Ambient Temperature
CLC114AI
+25˚C
−40˚C
+25˚C
+85˚
Frequency Domain Response
<
>
>
>
>
>
>
70
SSBW
LSBW
-3dB Bandwidth
VOUT 0.5VPP
200
95
135
135
120
MHz
MHz
<
VOUT 2VPP
70
70
<
Gain Flatness
Peaking
VOUT 0.5VPP
<
<
<
<
<
<
<
<
<
GFPL
GFPH
GFR
XT
DC to 30MHz
0.0
0.0
0.1
62
0.3
1.3
0.8
0.2
0.7
0.8
0.3
0.7
1.0
dB
dB
dB
dB
Peaking
30MHz to 200MHz
DC to 60MHz
10MHz
Rolloff
>
>
>
60
Crosstalk (All Hostile)
58
58
Time Domain Response
<
<
<
<
<
<
TRS1
TRS2
TS1
Rise and Fall Time
0.5V Step
2V Step
2V Step
2V Step
0.5V Step
1.8
5
2.8
2.8
3.0
ns
ns
7
7
8
<
<
<
<
<
<
<
<
<
Settling Time to 0.1%
to 0.01%
10
20
3
15
30
15
180
15
30
10
200
20
40
15
180
ns
TS01
OS
ns
Overshoot
%
>
>
>
SR
Slew Rate
450
V/µs
Distortion And Noise Response
<
<
<
<
<
<
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Input Noise
Noise Floor
2VPP,20MHz
2VPP,20MHz
−50
−58
−34
−50
−38
−50
−38
−45
dBc
dBc
>
<
<
<
−153 dBm1Hz
SNF
1MHz
−155
−153
−153
Static, DC Performance
>
<
<
<
<
>
<
>
<
<
±
30
<
±
<
>
46
<
16.0
GA
Small Signal Gain
100Ω Load
0.97
0.4
0.95
0.96
0.96
V/V
%
<
<
<
±
ILIN
VIO
Integral Endpoint Linearity
1V, Full Scale
1.0
0.6
0.5
±
±
±
±
±
±
±
8.0
Output Offset Voltage(Note 3)
Average Temperature Coefficient
Input Bias Current (Note 3)
0.5
9.0
1.0
6.0
8.2
5.0
mV
±
DVIO
IBN
40
10
62
–
±
–
µV/˚C
µA
<
±
±
5
4
±
DIBN
PSRR
ICC
Average Temperature Coefficient
Power Supply Rejection Ratio
Supply Current, Total (Note 3)
25
nA/˚C
dB
>
<
>
<
56
48
48
No Load, Quiescent
12.0
17.0
16.5
mA
Miscellaneous Performance
>
<
<
>
<
<
>
<
<
>
±
RIN
CIN
RO
VO
IO
Input Resistance
Input Capacitance
Output Impedance
Output Voltage Range
Output Current
1.5
1.8
2.5
0.3
3.5
5.0
1.0
3.0
3.5
2.0
3.5
3.5
MΩ
pF
Ω
DC
>
>
±
±
±
No Load
4.0
3.6
12
3.8
20
3.8
25
V
>
>
>
25
mA
3
www.national.com
Electrical Characteristics (Continued)
±
(VCC
=
5 V, RL = 100Ω; Unless Specified)
Symbol
Parameter
Conditions
Max/Min Ratings
Typ
Units
(Note 2)
Performance Driving a Crosspoint Switch
<
±
Gain Flatness VOUT 2VPP
DC to 5MHz
0.02
dB
dB
<
±
Gain Flatness VOUT 2VPP
DC to 30MHZ
3.58 & 4.43MHz
3.58 & 4.43MHz
0.1
0.08
0.1
Differential Gain
%
Differential Phase
2nd Harmonic Distortion
deg
dBc
dBc
dBc
dBc
dB
5MHz,2V
−60
−43
−58
−43
58
PP
30MHz,2VPP
5MHz,2VPP
3rd Harmonic Distortion
Crosstalk (All Hostile)
30MHz,2V
PP
5MHz
10MHz
30MHz
54
dB
42
dB
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
Test Load
DS012738-22
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4
Typical Performance Characteristics
Gain and Phase vs. Load
Output Impedance
DS012738-4
DS012738-5
Input Impedance
PSRR
DS012738-6
DS012738-7
Recommended RS vs. Load Capacitance
| S21| vs. CL with Recommended RS
DS012738-9
DS012738-8
5
www.national.com
Typical Performance Characteristics (Continued)
Small Signal Pulse Response
Large Signal Pulse Response
DS012738-10
DS012738-11
Short-Term Settling Time
Integral Linearity Error
DS012738-12
DS012738-13
Output Current vs. Temperature
Typical D.C. Errors vs. Temperature
DS012738-14
DS012738-15
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6
Typical Performance Characteristics (Continued)
Equivalent Input Noise
2nd and 3rd Harmonic Distortion
DS012738-16
DS012738-17
2-Tone, 3rd Order Intermodulation Intercept
DS012738-18
Application Division
Operation
to interface capacitance. For this reason it is recommended
that unused package pins (2, 4, 6, 11) be connected to the
ground plane for better channel isolation at the device pins.
Similarly, crosstalk can be improved by using a grounded
guard trace between signal traces. This will reduce the dis-
tributed capacitance between signal lines.
The CLC114 is a quad, low power, high speed, unity gain
buffer. The closed loop topology provides accuracy not found
in open loop designs. The input stage incorporates a slew
enhancement circuit which allows low quiescent power with-
out sacrificing AC performance.
Following are two graphs depicting the effects of crosstalk.
All-hostile crosstalk is measured by driving three of the four
buffers simultaneously while observing the fourth, undriven,
channel. Figure 2, “All-hostile Crosstalk Isolation”, shows
this effect as a function of input signal frequency. RL is the
resistive load for each driven channel. Figure 3, “Most Sus-
ceptible Channel-to-Channel Pulse Coupling”, describes one
effect of crosstalk when one channel is driven with a 2VPP
step (tr = 5ns) while the output of the undriven channel is
measured. FromFigure 2 it can be observed that crosstalk
decreases as the signal frequency is reduced. Similarly, the
pulse coupling crosstalk will decrease as the rise time in-
creases.
PC Board Layout and Crosstalk
High frequency devices demand a good printed circuit board
layout for optimum performance. The CLC114, with power
gain to 200 MHz, is no exception. A ground plane and power
supply bypassing with good high frequency ceramic capaci-
tors in close proximity to the supply pins is essential. Second
harmonic distortion can be improved by ensuring equal cur-
rent return paths for both the positive and negative supplies.
This can be accomplished by grounding the bypass capaci-
tors at the same point in the ground plane while keeping the
power supply side of the bypass capacitors within 0.1” of the
CLC114 supply pins.
Crosstalk (undesired signal coupling between buffer chan-
nels) is strongly dependent on board layout. Closely spaced
signal traces on the circuit board will degrade crosstalk due
Evaluation Board
An evaluation board for the CLC114 is available. This board
maybe ordered as part CLC730023.
7
www.national.com
Differential Gain and Phase
Application Division (Continued)
The CLC114 was designed to minimize deferential gain and
phase errors when driving the distributed capacitance of a
video cross point switch. Refer to the section “Performance
Driving a Crosspoint Switch” for typical values.
Unused Buffer
It is recommended that the inputs of any unused buffers be
tied to ground through 50Ω resistors.
DS012738-19
FIGURE 1. Recommended Circuit
DS012738-21
FIGURE 2. All- Hostile Crosstalk Isolation
DS012738-23
FIGURE 3. Most susceptible Channel-to-Channel Pulse Coupling
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
14-Pin SOIC
NS Package Number M14B
9
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Pin MDIP
NS Package Number N14A
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