COP87L20CJM-1B_技术文档

PRELIMINARY

July 1999

COP87LxxCJ/RJ Family

8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory

and Comparator

=

tions (-1 crystal; -2 external; -3 internal RC), one multi-

General Description

™

function 16-bit timer/counter, MICROWIRE/PLUS serial

The COP87LxxCJ/RJ Family OTP (One Time Program-

I/O, one analog comparator, power saving HALT mode with

multi-sourced wakeup/interrupt capability, on-chip R/C oscil-

lator capacitor, high current outputs, software selectable I/O

options, WATCHDOG timer, modulator/timer, Power on

Reset, program code security, 2.7V to 5.5V operation and

20/28 pin packages.

™

mable) microcontrollers are integrated COP8 Base core

devices with 4k or 32k memory, and an Analog comparator

(no brownout). These multi-chip CMOS devices are suited

for lower-functionality applications, and as pre-production

devices for a ROM design. Low cost, pin and software com-

patible (plus Brownout) 1k or 2k ROM versions are available

(COP820CJ/840CJ Family). Versions are available for use

with a range of COP8 software and hardware development

tools.

™

In this datasheet, the term COP87L20CJ refers to the

COP87L20CJ, and COP87L22CJ. COP840CJ refers to the

COP87L40CJ,

COP87L42RJ.

COP87L42CJ,

COP87L40RJ,

and

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI with 1µs instruction cycle, three clock op-

Devices included in this datasheet are:

Device

Memory (bytes)

4k OTP EPROM

32k OTP EPROM

RAM (bytes)

I/O Pins

24

Packages

Temperature

COP87L20CJ

COP87L22CJ

COP87L40CJ

COP87L42CJ

COP87L40RJ

COP87L42RJ

64

28 DIP/SOIC

20 DIP/SOIC

28 DIP/SOIC

20 DIP/SOIC

28 DIP/SOIC

20 DIP/SOIC

-40 to +85˚C

64

16

128

24

16

24

16

Key Features

CPU/Instruction Set Features

n Multi-Input Wakeup (on the 8-bit Port L)

n Analog comparator

n 1 µs instruction cycle time

n Three multi-source interrupts servicing

— External interrupt with selectable edge

— Timer interrupt

n Modulator/Timer (high speed PWM timer for IR

transmission)

— Software interrupt

n 16-bit multi-function timer supporting

— PWM mode

— External event counter mode

— Input capture mode

n Versatile and easy to use instruction set

n 8-bit stack pointer (SP) — stack in RAM

n Two 8-bit Register Indirect Data Memory Pointers (B and

X)

n Integrated capacitor for the R/C oscillator

n 4 or 32 kbyte on-board OTP EPROM with security

feature

n 64 or 128 bytes on-chip RAM

Fully Static CMOS

<

n Low current drain (typically 1 µA)

n Single supply operation: 2.7V to 5.5V

n Temperature range: −40˚C to +85˚C

I/O Features

n Software selectable I/O options (TRI-STATE^®, Push-Pull,

Weak Pull-Up Input, High Impedance Input)

n High current outputs (8 pins)

n Schmitt trigger inputs on Port G

n MICROWIRE/PLUS serial I/O

n Packages:

Development Support

n Emulation device for the COP820CJ/COP840CJ

n Real time emulation and full program debug offered by

MetaLink Development Systems

— 20 DIP/SO with 16 I/O pins

— 28 DIP/SO with 24 I/O pins

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

COP8 , MICROWIRE , MICROWIRE/PLUS and WATCHDOG are trademarks of National Semiconductor Corporation.

iceMASTER^®is a registered trademark of MetaLink Corporation.

DS012529

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Block Diagram

DS012529-1

FIGURE 1. Block Diagram

Connection Diagrams

DS012529-3

Top View

Order Number

COP87L22CJN (-1N, -2N, -3N), or

COP87L22CJM(-1N, -2N, -3N), or

COP87L42CJN (-1N, -2N, -3N), or

COP87L42CJM (-1N, -2N, -3N), or

COP87L42RJN (-1N, -2N, -3N), or

COP87L42RJM (-1N, -2N, -3N)

DS012529-2

Top View

Order Number

COP87L20CJN (-1N, -2N, -3N), or

COP87L20CJM(-1N, -2N, -3N), or

COP87L40CJN (-1N, -2N, -3N), or

COP87L40CJM (-1N, -2N, -3N), or

COP87L40RJN (-1N, -2N, -3N), or

COP87L40RJM (-1N, -2N, -3N)

See NS Package Number N20A or M20B

See NS Package Number N28B or M28B

FIGURE 2. Connection Diagrams

Note: -1 Crystal Oscillator

-2 External Oscillator

-3 R/C Oscillator

N - Brown out disabled

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2

Pin Assignment

Port

L0

ALT

Funct.

20

7

28

11

12

13

14

15

16

17

18

25

26

27

28

1

Typ

I/O

I

MIWU/CMPOUT

MIWU/CMPIN−

MIWU/CMPIN+

MIWU

L1

8

L2

9

L3

10

11

12

13

14

17

18

19

20

1

L4

MIWU

L5

MIWU

L6

MIWU

L7

MIWU/MODOUT

INTR

G0

G1

G2

G3

G4

G5

G6

G7

I0

TIO

SO

SK

2

SI

3

I

CKO

4

I

7

I1

I

8

I2

I

9

I3

I

10

19

20

21

22

6

D0

D1

D2

D3

V_CC

GND

CKI

RESET

O

6

15

5

23

5

16

24

3

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Total Current into V_CCpin (Source)

Total Current out of GND pin (sink)

Storage Temperature Range

Note 1: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

80 mA

−65˚C to +150˚C

Supply Voltage (V_CC

)

7.0V

Voltage at any Pin

−0.3V to V_CC+ 0.3V

DC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

5.5

Units

Operating Voltage

2.7

V

Power Supply Ripple 1 (Note 2)

Supply Current (Note 3)

Peak to Peak

0.1 V_CC

=

CKI 10 MHz

V_CC5.5V, tc 1 µs

12

mA

=

CKI 4 MHz

V_CC4.5V, tc 2.5 µs

6.5

=

CKI 4 MHz (COP87L20CJ)

V_CC4.0V, tc 2.5 µs

10

12

mA

µA

= =

V_CC5.5V, CKI 0 MHz

HALT Current (Note 4)

INPUT LEVELS (V_IH, V_IL

)

Reset, CKI:

Logic High

0.8 V_CC

0.7 V_CC

V

Logic Low

0.2 V_CC

All Other Inputs

Logic High

V

Logic Low

0.2 V_CC

+2

=

Hi-Z Input Leakage

Input Pullup Current

V_CC5.5V

−2

µA

V

=

V_CC5.5V

−40

−250

L- and G-Port Hysteresis (Note 7)

Output Current Levels

D Outputs:

0.35 V_CC

=

Source

V_CC4.5V, V_OH3.8V

−0.4

10

mA

= =

V_CC4.5V, V_OL1.0V

Sink (Note 5)

=

L4–L7 Output Sink

All Others

V_CC4.5V, V_OL2.5V

15

=

Source (Weak Pull-up Mode)

Source (Push-pull Mode)

Sink (Push-pull Mode)

(COP887L20CJ)

V_CC4.5V, V_OH3.2V

−10

−0.4

1.6

−110

+2.0

µA

mA

=

V_CC4.5V, V_OH3.8V

=

V_CC4.5V, V_OL0.4V

=

V_CC5.5V, V_OL0.4V

TRI-STATE Leakage

Allowable Sink/Source

Current Per Pin

−2.0

µA

D Outputs

15

20

3

mA

L4–L7 (Sink)

All Others

±

Maximum Input Current

without Latchup (Note 6)

RAM Retention Voltage, V_r

Room Temperature

100

500 ns Rise and

Fall Time (Min)

2.0

V

Input Capacitance

7

pF

Load Capacitance on D2

1000

Note 2: Rate of voltage change must be less than 10 V/mS.

Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

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4

DC Electrical Characteristics (Continued)

Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations by bringing CKI high. HALT test conditions: L, and G0..G5 ports configured

as outputs and set high. The D port set to zero. All inputs tied to V . The comparator is disabled.

CC

Note 5: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into

programming mode.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V and the pins will have sink current

CC

to V when biased at voltages greater than V (the pins do not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω

CC

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

AC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Instruction Cycle Time (tc)

Crystal/Resonator

R/C Oscillator

Conditions

Min

Typ

Max

Units

4.5V ≤ V_CC≤ 5.5V

1

2

DC

60

12

8

µs

%

=

CKI Clock Duty Cycle (Note 7)

Rise Time (Note 7)

Fall Time (Note 7)

Inputs

fr Max

40

=

fr 10 MHz ext. Clock

ns

=

fr 10 MHz ext. Clock

t_Setup

4.5V ≤ V_CC≤ 5.5V

200

60

ns

t_Hold

=

Output Propagation Delay

R_L2.2k, CL 100 pF

t

_PD1, t_PD0

SO, SK

4.5V ≤ V_CC≤ 5.5V

0.7

1

µs

All Others

Input Pulse Width

Interrupt Input High Time

Interrupt Input Low Time

Timer Input High Time

Timer Input Low Time

1

tc

1

tc

1

tc

™

MICROWIRE Setup Time (t_µWS

)

20

56

ns

MICROWIRE Hold Time (t_µWH

)

MICROWIRE Output

220

Propagation Delay (t_µPD

)

Reset Pulse Width

1

µs

Note 7: Parameter characterized but not production tested.

DS012529-4

FIGURE 3. MICROWIRE/PLUS Timing

5

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G7 CKO crystal oscillator output (selected by mask option)

or HALT restart input/general purpose input (if clock

option is R/C or external clock)

Pin Description

V_CCand GND are the power supply pins.

CKI is the clock input. This can come from an external

source, a R/C generated oscillator or a crystal (in conjunc-

tion with CKO). See Oscillator description.

G6 SI (MICROWIRE serial data input)

G5 SK (MICROWIRE clock I/O)

G4 SO (MICROWIRE serial data output)

G3 TIO (timer/counter input/output)

G0 INTR (an external interrupt)

RESET is the master reset input. See Reset description.

PORT I is a 4-bit Hi-Z input port.

PORT L is an 8-bit I/O port.

Pins G2 and G1 currently do not have any alternate func-

tions.

There are two registers associated with the L port: a data

register and a configuration register. Therefore, each L I/O

bit can be individually configured under software control as

shown below:

The selection of alternate Port G functions are done through

registers PSW [00EF] to enable external interrupt and CN-

TRL1 [00EE] to select TIO and MICROWIRE operations.

Port L

Setup

PORT D is a four bit output port that is preset when RESET

goes low. One data memory address location is allocated for

the data register [00DC]. The user can tie two or more D port

outputs (except D2 pin) together in order to get a higher

drive.

Config.

Data

0

1

0

1

0

1

Hi-Z Input (TRI-STATE)

Input with Weak Pull-up

Push-pull Zero Output

Push-pull One Output

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

above 0.8 V

CC

to prevent the chip from entering special modes. Also

Three data memory address locations are allocated for this

port, one each for data register [00D0], configuration register

[00D1] and the input pins [00D2].

keep the external loading on D2 to less than 1000 pF.

Functional Description

Port L has the following alternate features:

L7 MIWU or MODOUT (high sink current capability)

L6 MIWU (high sink current capability)

L5 MIWU (high sink current capability)

L4 MIWU (high sink current capability)

L3 MIWU

The internal architecture is shown in the block diagram. Data

paths are illustrated in simplified form to depict how the vari-

ous logic elements communicate with each other in imple-

menting the instruction set of the device.

ALU and CPU Registers

The ALU can do an 8-bit addition, subtraction, logical or shift

operations in one cycle time. There are five CPU registers:

L2 MIWU or CMPIN+

L1 MIWU or CMPIN−

A

is the 8-bit Accumulator register

L0 MIWU or CMPOUT

PC is the 15-bit Program Counter register

The selection of alternate Port L functions is done through

registers WKEN [00C9] to enable MIWU and CNTRL2

[00CC] to enable comparator and modulator.

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B

X

is the 8-bit address register and can be auto incre-

mented or decremented.

All eight L-pins have Schmitt Triggers on their inputs.

PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input

pins (G6, G7).

is the 8-bit alternate address register and can be auto

incremented or decremented.

All eight G-pins have Schmitt Triggers on the inputs.

SP is the 8-bit stack pointer which points to the subroutine

stack (in RAM).

There are two registers associated with the G port: a data

register and a configuration register. Therefore each G port

bit can be individually configured under software control as

shown below:

B, X and SP registers are mapped into the on chip RAM. The

B and X registers are used to address the on chip RAM. The

SP register is used to address the stack in RAM during sub-

routine calls and returns. The SP must be initialized by soft-

ware before any subroutine call or interrupts occurs.

Port G

Setup

Config.

Data

0

1

0

1

0

1

Hi-Z Input (TRI-STATE)

Input with Weak Pull-up

Push-pull Zero Output

Push-pull One Output

Memory

The memory is separated into two memory spaces: program

and data.

PROGRAM MEMORY

Three data memory address locations are allocated for this

port, one for data register [00D4], one for configuration reg-

ister [00D5] and one for the input pins [00D6]. Since G6 and

G7 are Hi-Z input only pins, any attempt by the user to con-

figure them as outputs by writing a one to the configuration

register will be disregarded. Reading the G6 and G7 configu-

ration bits will return zeros. Note that the device will be

placed in the Halt mode by writing a “1” to the G7 data bit.

Program memory consists of 4 kbytes of OTP EPROM.

These bytes of ROM may be instructions or constant data.

The memory is addressed by the 15-bit program counter

(PC). ROM can be indirectly read by the LAID instruction for

table lookup.

The device can be configured to inhibit external reads of the

program memory. This is done by programming the Security

Byte.

Six pins of Port G have alternate features:

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6

Memory (Continued)

Data and Configuration

Registers for L & G

WATCHDOG Timer

CLEARED

SECURITY FEATURE

Prescaler/Counter each

loaded with FF

The memory array has an associate Security Byte that is lo-

cated outside of the program address range. This byte can

be addressed only from programming mode by a program-

mer tool.

The device comes out of the HALT mode when the RESET

pin is pulled low. In this case, the user has to ensure that the

RESET signal is low long enough to allow the oscillator to re-

start. An internal 256 t_cdelay is normally used in conjunction

with the two pin crystal oscillator. When the device comes

out of the HALT mode through Multi-Input Wakeup, this de-

lay allows the oscillator to stabilize.

Security is an optional feature and can only be asserted after

the memory arrary has been programmed and verified. A se-

cured part will read all 00(hex) by a programmer. The part

will fail Blank Check and will fail Verify operations. A Read

operation will fill the programmer’s memory with 00(hex).

The Security Byte itself is always readable with value of

00(hex) if unsecure and FF(hex) if secure.

The following additional actions occur after the device

comes out of the HALT mode through the RESET pin.

If a two pin crystal/resonator oscillator is being used:

DATA MEMORY

The data memory address space includes on chip RAM, I/O

and registers. Data memory is addressed directly by the in-

struction or indirectly through B, X and SP registers. The de-

vice has 128 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers”, these can be loaded immediately,

decremented and tested. Three specific registers: X, B, and

SP are mapped into this space, the other registers are avail-

able for general usage.

RAM Contents

UNCHANGED

UNKNOWN

ALTERED

Timer T1 and A Contents

WATCHDOG Timer Prescaler/Counter

If the external or RC Clock option is being used:

RAM Contents

UNCHANGED

Timer T1 and A Contents

WATCHDOG Timer Prescaler/Counter

UNCHANGED

ALTERED

Any bit of data memory can be directly set, reset or tested.

All I/O and registers (except A and PC) are memory mapped;

therefore, I/O bits and register bits can be directly and indi-

vidually set, reset and tested, except the write once only bit

(WDREN, WATCHDOG Reset Enable), and the unused and

read only bits in CNTRL2 and WDREG registers.

Note: RAM contents are undefined upon power-up.

Reset

DS012529-5

EXTERNAL RESET

>

RC 5 x Power Supply Rise Time

The RESET input pin when pulled low initializes the

micro-controller. The user must insure that the RESET pin is

held low until V_CCis within the specified voltage range and

the clock is stabilized. An R/C circuit with a delay 5x greater

than the power supply rise time is recommended (Figure 4).

The device immediately goes into reset state when the RE-

SET input goes low. When the RESET pin goes high the de-

vice comes out of reset state synchronously. The device will

be running within two instruction cycles of the RESET pin go-

ing high. The following actions occur upon reset:

FIGURE 4. Recommended Reset Circuit

WATCHDOG RESET

With WATCHDOG enabled, the WATCHDOG logic resets

the device if the user program does not service the WATCH-

DOG timer within the selected service window. The WATCH-

DOG reset does not disable the WATCHDOG. Upon

WATCHDOG reset, the WATCHDOG Prescaler/Counter are

each initialized with FF Hex.

The following actions occur upon WATCHDOG reset that are

different from external reset.

Port L

TRI-STATE

Port G

TRI-STATE

WDREN WATCHDOG Reset Enable bit

WDUDF WATCHDOG Underflow bit

UNCHANGED

Port D

HIGH

PC

CLEARED

Additional initialization actions that occur as a result of

WATCHDOG reset are as follows:

RAM Contents

RANDOM with Power-On-

Reset

Port L

TRI-STATE

HIGH

UNAFFECTED with external

Port G

Reset (power already

applied)

Port D

PC

CLEARED

UNCHANGED

B, X, SP

Same as RAM

Ram Contents

B, X, SP

PSW, CNTRL1, CNTRL2

and WDREG Reg.

Multi-Input Wakeup Reg.

WKEDG, WKEN

WKPND

CLEARED

PSW, CNTRL1 and CNTRL2

(except

CLEARED

WDUDF Bit) Registers

CLEARED

UNKNOWN

7

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CRYSTAL OSCILLATOR

Reset (Continued)

By selecting the crystal oscillator option, the G7/CKO pin is

connected as a clock output, CKI and G7/CKO can be con-

nected to make a crystal controlled oscillator. Table 1 shows

the clock frequency for different component values. See Fig-

ure 5 for the connections.

Multi-Input Wakeup Registers

WKEDG, WKEN

CLEARED

WKPND

UNKNOWN

Data and Configuration

Registers for L & G

WATCHDOG Timer

R/C OSCILLATOR

CLEARED

By selecting R/C oscillator option, connecting a resistor from

the CKI pin to V_CCmakes a R/C oscillator. The capacitor is

on-chip. The G7/CKO pin is available as a general purpose

input G7 and/or HALT control. Adding an external capacitor

will jeopardize the clock frequency tolerance and increase

EMI emissions.

Prescalar/Counter

each loaded with FF

Oscillator Circuits

EXTERNAL OSCILLATOR

Table 2 shows the clock frequency for the different resistor

By selecting the external oscillator option, the CKI pin can be

driven by an external clock signal provided it meets the

specified duty cycle, rise and fall times, and input levels. The

G7/CKO is available as a general purpose input G7 and/or

HALT control.

values. The capacitor is on-chip. See Figure

connections.

5 for the

DS012529-6

FIGURE 5. Clock Oscillator Configurations

TABLE 1. Crystal Oscillator Configuration

R1

(kΩ)

0

R2

(MΩ)

1

C1

(pF)

30

C2

(pF)

CKI Freq.

(MHz)

10

Conditions

=

V_CC5V

30–36

100–156

=

V_CC5V

0

1

30

4

=

V_CC5V

5.6

1

100

0.455

=

TABLE 2. RC Oscillator Configuration (Part-To-Part Variation) T_A25˚C

R

CK1 Freq.

(MHz)

Instr. Cycle

(µs)

Conditions

(kΩ)

8.2

2.2

3.9

=

±

3.3 10%

3.0 10%

V_CC5V

=

±

1.3 10%

7.7 10%

V_CC5V

=

±

0.75 10%

13.3 10%

V_CC5V

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8

Halt Mode

MICROWIRE/PLUS

The device is a fully static device. The device enters the

HALT mode by writing a one to the G7 bit of the G data reg-

ister. Once in the HALT mode, the internal circuitry does not

receive any clock signal and is therefore frozen in the exact

state it was in when halted. In this mode the chip will only

draw leakage current.

MICROWIRE/PLUS is a serial synchronous bidirectional

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with any of National Semi-

conductor’s MICROWIRE peripherals (i.e. A/D converters,

display drivers, EEPROMS, etc.) and with other microcon-

trollers which support the MICROWIRE/PLUS interface. It

consists of an 8-bit serial shift register (SIO) with serial data

input (SI), serial data output (SO) and serial shift clock (SK).

Figure 6 shows the block diagram of the MICROWIRE/PLUS

interface.

The device supports three different methods of exiting the

HALT mode. The first method is with a low to high transition

on the CKO (G7) pin. This method precludes the use of the

crystal clock configuration (since CKO is a dedicated out-

put). It may be used either with an RC clock configuration or

an external clock configuration. The second method of exit-

ing the HALT mode is with the multi-Input Wakeup feature on

the L port. The third method of exiting the HALT mode is by

pulling the RESET input low.

If the two pin crystal/resonator oscillator is being used and

Multi-Input Wakeup causes the device to exit the HALT

mode, the WAKEUP signal does not allow the chip to start

running immediately since crystal oscillators have a delayed

start up time to reach full amplitude and freuqency stability.

The WATCHDOG timer (consisting of an 8-bit prescaler fol-

lowed by an 8-bit counter) is used to generate a fixed delay

of 256tc to ensure that the oscillator has indeed stabilized

before allowing instruction execution. In this case, upon de-

tecting a valid WAKEUP signal only the oscillator circuitry is

enabled. The WATCHDOG Counter and Prescaler are each

loaded with a value of FF Hex. The WATCHDOG prescaler is

clocked with the tc instruction cycle. (The tc clock is derived

by dividing the oscillator clock down by a factor of 10).

DS012529-7

FIGURE 6. MICROWIRE/PLUS Block Diagram

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS in-

terface with the internal clock source is called the Master

mode of operation. Operating the MICROWIRE/PLUS inter-

face with an external shift clock is called the Slave mode of

operation.

The Schmitt trigger following the CKI inverter on the chip en-

sures that the WATCHDOG timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specs. This Schmitt trigger is not part of the

oscillator closed loop. The start-up timeout from the WATCH-

DOG timer enables the clock signals to be routed to the rest

of the chip. The delay is not activated when the device

comes out of HALT mode through RESET pin. Also, if the

clock option is either RC or External clock, the delay is not

used, but the WATCHDOG Prescaler/-Counter contents are

changed. The Development System will not emulate the

256tc delay.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,

the MSEL bit in the CNTRL register is set to one. The SK

clock rate is selected by the two bits, SL0 and SL1, in the

CNTRL register. Table 3 details the different clock rates that

may be selected.

TABLE 3.

The RESET pin will cause the device to reset and start ex-

ecuting from address X’0000. A low to high transition on the

G7 pin (if single pin oscillator is used) or Multi-Input Wakeup

will cause the device to start executing from the address fol-

lowing the HALT instruction.

SL1

0

SL0

SK Cycle Time

0

1

x

2t_c

4t_c

8t_c

0

1

When RESET pin is used to exit the device from the HALT

mode and the two pin crystal/resonator (CKI/CKO) clock op-

tion is selected, the contents of the Accumulator and the

Timer T1 are undetermined following the reset. All other in-

formation except the WATCHDOG Prescaler/Counter con-

tents is retained until continuing. All information except the

WATCHDOG Prescaler/Counter contents is retained if the

device exits the HALT mode through G7 pin or Multi-Input

Wakeup.

where,

t_cis the instruction cycle time.

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS arrangement to start shifting the data. It

gets reset when eight data bits have been shifted. The user

may reset the BUSY bit by software to allow less than 8 bits

to shift. The device may enter the MICROWIRE/PLUS mode

either as a Master or as a Slave. Figure 7 shows how two de-

vice microcontrollers and several peripherals may be inter-

connected using the MICROWIRE/PLUS arrangement.

G7 is the HALT-restart pin, but it can still be used as an input.

If the device is not halted, G7 can be used as a general pur-

pose input.

Note: To allow clock resynchronization, it is necessary to program two NOP’s

immediately after the device comes out of the HALT mode. The user

must program two NOP’s following the “enter HALT mode” (set G7

data bit) instruction.

Master MICROWIRE/PLUS Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally by the device. The

MICROWIRE/PLUS Master always initiates all data ex-

9

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TABLE 4.

MICROWIRE/PLUS (Continued)

G4

G5

G4

G5 G6

Fun. Fun.

changes (Figure 7). The MSEL bit in the CNTRL register

must be set to enable the SO and SK functions on the G

Port. The SO and SK pins must also be selected as outputs

by setting appropriate bits in the Port G configuration regis-

ter. Table 4 summarizes the bit settings required for Master

mode of operation.

Config. Config.

Fun.

Operation

Bit

1

SO

Int.

SK

SI

MICROWIRE

Master

0

1

0

1

0

TRI-STATE Int.

SK

MICROWIRE

Master

Slave MICROWIRE/PLUS Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

on the G Port. The SK pin must be selected as an input and

the SO pin selected as an output pin by appropriately setting

up the Port G configuration register. Table 4 summarizes the

settings required to enter the Slave mode of operation.

SO

Ext.

SK

MICROWIRE

Slave

TRI-STATE Ext.

SK

MICROWIRE

Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated (see Figure 7).

DS012529-8

FIGURE 7. MICROWIRE/PLUS Application

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10

CNTRL allow the timer to be started and stopped under soft-

ware control. The timer-register pair can be operated in one

of three possible modes. Table 5 details various timer oper-

ating modes and their requisite control settings.

Timer/Counter

The device has a powerful 16-bit timer with an associated

16-bit register enabling it to perform extensive timer func-

tions. The timer T1 and its register R1 are each organized as

two 8-bit read/write registers. Control bits in the register

TABLE 5. Timer Operating Modes

CNTRL

Timer

Bits

7 6 5

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Operation Mode

T Interrupt

Counter

On

External Counter w/Auto-Load Reg.

Not Allowed

Timer Underflow

Not Allowed

TIO Pos. Edge

TIO Neg. Edge

Not Allowed

Timer w/Auto-Load Reg.

Timer w/Auto-Load Reg./Toggle TIO Out

Timer w/Capture Register

Timer Underflow

TIO Pos. Edge

TIO Neg. Edge

t_c

MODE 1. TIMER WITH AUTO-LOAD REGISTER

as a positive edge or as a negative edge. In this mode the

user can elect to be interrupted on the specified trigger edge

(Figure 9).

In this mode of operation, the timer T1 counts down at the in-

struction cycle rate. Upon underflow the value in the register

R1 gets automatically reloaded into the timer which contin-

ues to count down. The timer underflow can be programmed

to interrupt the microcontroller. A bit in the control register

CNTRL enables the TIO (G3) pin to toggle upon timer under-

flows. This allows the generation of square-wave outputs or

pulse width modulated outputs under software control (Fig-

ure 8).

MODE 2. EXTERNAL COUNTER

In this mode, the timer T1 becomes a 16-bit external event

counter. The counter counts down upon an edge on the TIO

pin. Control bits in the register CNTRL program the counter

to decrement either on a positive edge or on a negative

edge. Upon underflow the contents of the register R1 are au-

tomatically copied into the counter. The underflow can also

be programmed to generate an interrupt (Figure 8).

DS012529-11

FIGURE 9. Timer Capture Mode Block Diagram

TIMER PWM APPLICATION

Figure 10 shows how a minimal component D/A converter

can be built out of the Timer-Register pair in the Auto-Reload

mode. The timer is placed in the “Timer with auto reload”

mode and the TIO pin is selected as the timer output. At the

outset the TIO pin is set high, the timer T1 holds the on time

and the register R1 holds the signal off time. Setting TRUN

bit starts the timer which counts down at the instruction cycle

rate. The underflow toggles the TIO output and copies the off

time into the timer, which continues to run. By alternately

loading in the on time and the off time at each successive in-

terrupt a PWM frequency can be easily generated.

DS012529-9

FIGURE 8. Timer/Counter Auto

Reload Mode Block Diagram

MODE 3. TIMER WITH CAPTURE REGISTER

Timer T1 can be used to precisely measure external fre-

quencies or events in this mode of operation. The timer T1

counts down at the instruction cycle rate. Upon the occur-

rence of a specified edge on the TIO pin the contents of the

timer T1 are copied into the register R1. Bits in the control

register CNTRL allow the trigger edge to be specified either

DS012529-12

FIGURE 10. Timer Application

11

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be dedicated for the WATCHDOG or used as a general pur-

pose counter. Figure 11 shows the WATCHDOG timer block

diagram.

WATCHDOG

The device has an on-board 8-bit WATCHDOG timer. The

timer contains an 8-bit READ/WRITE down counter clocked

by an 8-bit prescaler. Under software control the timer can

DS012529-13

FIGURE 11. WATCHDOG Timer Block Diagram

MODE 1: WATCHDOG TIMER

MODE 2: TIMER

The WATCHDOG is designed to detect user programs get-

ting stuck in infinite loops resulting in loss of program control

or “runaway” programs. The WATCHDOG can be enabled or

disabled (only once) after the device is reset as a result of

external reset. On power-up the WATCHDOG is disabled.

The WATCHDOG is enabled by writing a “1” to WDREN bit

(resides in WDREG register). Once enabled, the user pro-

gram should write periodically into the 8-bit counter before

the counter underflows. The 8-bit counter (WDCNT) is

memory mapped at address 0CE Hex. The counter is loaded

with n-1 to get n counts. The counter underflow resets the

device, but does not disable the WATCHDOG. Loading the

8-bit counter initializes the prescaler with FF Hex and starts

the prescaler/counter. Prescaler and counter are stopped

upon counter underflow. Prescaler and counter are each

loaded with FF Hex when the device goes into the HALT

mode. The prescaler is used for crystal/resonator start-up

when the device exits the HALT mode through Multi-Input

Wakeup. In this case, the prescaler/counter contents are

changed.

In this mode, the prescaler/counter is used as a timer by

keeping the WDREN (WATCHDOG reset enable) bit at 0.

The counter underflow sets the WDUDF (underflow) bit and

the underflow does not reset the device. Loading the 8-bit

counter (load n-1 for n counts) sets the WDTEN bit (WATCH-

DOG Timer Enable) to “1”, loads the prescaler with FF, and

starts the timer. The counter underflow stops the timer. The

WDTEN bit serves as a start bit for the WATCHDOG timer.

This bit is set when the 8-bit counter is loaded by the user

program. The load could be as a result of WATCHDOG ser-

vice (WATCHDOG timer dedicated for WATCHDOG func-

tion) or write to the counter (WATCHDOG timer used as a

general purpose counter). The bit is cleared upon Brown Out

reset, WATCHDOG reset or external reset. The bit is not

memory mapped and is transparent to the user program.

CONTROL/STATUS BITS

WDUDF: WATCHDOG Timer Underflow Bit

This bit resides in the CNTRL2 Register. The bit is set when

the WATCHDOG timer underflows. The underflow resets the

=

device if the WATCHDOG reset enable bit is set (WDREN

1). Otherwise, WDUDF can be used as the timer underflow

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12

control can be written to only once (once written to, the hard-

ware does not allow the bit to be changed during program

execution).

WATCHDOG (Continued)

flag. The bit is cleared upon external reset, load to the 8-bit

counter, or going into the HALT mode. It is a read only bit.

=

WDREN 1 WATCHDOG reset is enabled.

WDREN: WD Reset Enable

=

WDREN 0 WATCHDOG reset is disabled.

WDREN bit resides in a separate register (bit 0 of WDREG).

This bit enables the WATCHDOG timer to generate a reset.

The bit is cleared upon external reset. The bit under software

Table 6 shows the impact of WATCHDOG Reset and Exter-

nal Reset on the Control/Status bits.

TABLE 6. WATCHDOG Control/Status

Parameter

HALT WD

EXT

Reset

FF

0

Counter

Mode

Reset

Load

8-Bit Prescaler

FF

8-Bit WD Counter

WDREN Bit

User Value

Unchanged

0

Unchanged

0

No Effect

WDUDF Bit

0

1

WDTEN Signal

Unchanged

0

Modulator/Timer

The Modulator/Timer contains an 8-bit counter and an 8-bit

autoreload register (MODRL address 0CF Hex). The

Modulator/Timer has two modes of operation, selected by

the control bit MC3. The Modulator/Timer Control bits MC1,

MC2 and MC3 reside in CNTRL2 Register.

by software loads the counter with the value of the autore-

load register and starts the counter. The counter underflow

toggles the (L7) output pin. The 50

% duty cycle signal will be

continuously generated until MC1 is reset by the user pro-

gram.

MODE 1: MODULATOR

b. Variable Duty Cycle:

=

The Modulator is used to generate high frequency pulses on

the modulator output pin (L7). The L7 pin should be config-

ured as an output. The number of pulses is determined by

the 8-bit down counter. Under software control the modulator

input clock can be either CKI or tC. The tC clock is derived by

dividing down the oscillator clock by a factor of 10. Three

control bits (MC1, MC2, and MC3) are used for the

When MC3 0 and MC2 1, a variable duty cycle PWM sig-

nal is generated on the L7 output pin. The counter is clocked

by tC. In this mode the 16-bit timer T1 along with the 8-bit

down counter are used to generate a variable duty cycle

PWM signal. The timer T1 underflow sets MC1 which starts

the down counter and it also sets L7 high (L7 should be con-

figured as an output).When the counter underflows the MC1

control bit is reset and the L7 output will go low until the next

timer T1 underflow. Therefore, the width of the output pulse

is controlled by the 8-bit counter and the pulse duration is

controlled by the 16-bit timer T1 (Figure 14). Timer T1 must

be configured in “PWM Mode/Toggle TIO Out” (CNTRL1 Bits

=

Modulator/Timer output control. When MC2 1 and MC3

=

1, CKI is used as the modulator input clock. When MC2 0,

=

and MC3 1, tC is used as the modulator input clock. The

user loads the counter with the desired number of counts

(256 max) and sets MC1 to start the counter. The modulator

autoreload register is loaded with n-1 to get n pulses. CKI or

tc pulses are routed to the modulator output (L7) until the

counter underflows (Figure 12). Upon underflow the hard-

ware resets MC1 and stops the counter. The L7 pin goes low

and stays low until the counter is restarted by the user pro-

gram. The user program has the responsibility to timeout the

low time. Unless the number of counts is changed, the user

program does not have to load the counter each time the

counter is started. The counter can simply be started by set-

ting the MC1 bit. Setting MC1 by software will load the

counter with the value of the autoreload register. The soft-

ware can reset MC1 to stop the counter.

=

7,6,5 101).

Table shows the different operation modes for the

Modulator/Timer.

7

TABLE 7. Modulator/Timer Modes

Control Bits in

CNTRL2(00CC)

Operation Mode

L7 Function

MC3 MC2 MC1

0

1

Normal I/O

50% Duty Cycle Mode (Clocked

by tc)

MODE 2: PWM TIMER

0

1

X

Variable Duty Cycle Mode

(Clocked by tc) Using Timer 1

Underflow

The counter can also be used as a PWM Timer. In this mode,

an 8-bit register is used to serve as an autoreload register

(MODRL).

1

0

1

X

Modulator Mode (Clocked by tc)

a. 50% Duty Cycle:

Modulator Mode (Clocked by

CKI)

When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle free

running signal is generated on the L7 output pin (Figure 13).

The L7 pin must be configured as an output pin. In this mode

the 8-bit counter is clocked by tC. Setting the MC1 control bit

Note: MC1, MC2 and MC3 control bits are cleared upon reset.

13

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Modulator/Timer (Continued)

Internal Data Bus

DS012529-14

FIGURE 12. Mode 1: Modulator Block Diagram/Output Waveform

DS012529-15

DS012529-16

FIGURE 13. Mode 2a: 50% Duty Cycle Output

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14

Modulator/Timer (Continued)

DS012529-17

DS012529-18

FIGURE 14. Mode 2b: Variable Duty Cycle Output

=

(CMPEN 1, CMPOE X)

Comparator

The device has one differential comparator. Ports L0–L2 are

used for the comparator. The output of the comparator is

brought out to a pin. Port L has the following assignments:

CMPOE Enables comparator output to pin L0

=

(“1” enable), CMPEN bit must be set to enable

this function. If CMPEN 0, L0 will be 0.

=

The Comparator Select/Control bits are cleared on RESET

(the comparator is disabled). To save power the program

should also disable the comparator before the device enters

the HALT mode.

L0 Comparator output

L1 Comparator negative input

L2 Comparator positive input

The user program must set up L0, L1 and L2 ports correctly

for comparator Inputs/Output: L1 and L2 need to be config-

ured as inputs and L0 as output. Table 8 shows the DC and

AC characteristics for the comparator.

THE COMPARATOR STATUS/CONTROL BITS

These bits reside in the CNTRL2 Register (Address 0CC)

=

CMPEN Enables comparator (“1” enable)

CMPRD Reads comparator output internally

TABLE 8. DC and AC Characteristics (Note 8) 4.5V ≤ V_CC≤ 5.5V, −40˚C ≤ T_A≤ +85˚C

Parameters

Input Offset Voltage

Conditions

Min

Typ

Max

Units

mV

V

<

±

25

0.4V V_INV_CC−1.5V

10

Input Common Mode Voltage Range

Voltage Gain

0.4

V_CC−1.5

300k

V/V

µA

=

DC Supply Current (when enabled)

Response Time

V_CC5.5V

250

1

TBD mV Step,

µs

TBD mV Overdrive, 100 pF Load

Note 8: For comparator output current characteristics see L-Port specs.

registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPND are

Multi-Input Wake Up

The Multi-Input Wakeup feature is used to return (wakeup)

the device from the HALT mode. Figure 15 shows the

Multi-Input Wakeup logic.

used in conjunction with the

Multi-Input Wakeup feature.

L port to implement the

All three registers Reg:WKEN, Reg:WKPND, and Reg-

:WKEDG are read/write registers, and are cleared at reset,

except WKPND. WKPND is unknown on reset.

This feature utilizes the L Port. The user selects which par-

ticular L port bit or combination of L Port bits will cause the

device to exit the HALT mode. Three 8-bit memory mapped

The user can select whether the trigger condition on the se-

lected L Port pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

15

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Multi-Input Wake Up (Continued)

This selection is made via the Reg:WKEDG, which is an 8-bit

control register with a bit assigned to each L Port pin. Setting

the control bit will select the trigger condition to be a negative

edge on that particular L Port pin. Resetting the bit selects

the trigger condition to be a positive edge. Changing an edge

select entails several steps in order to avoid a pseudo

Wakeup condition as a result of the edge change. First, the

associated WKEN bit should be reset, followed by the edge

select change in WKEDG. Next, the associated WKPND bit

should be cleared, followed by the associated WKEN bit be-

ing re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L port bit 5, where bit 5 has

previously been enabled for an input. The program would be

as follows:

RBIT 5, WKEN

; Disable MIWU

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

DS012529-19

FIGURE 15. Multi-Input Wakeup Logic

SBIT 5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup, a safety proce-

dure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected L port bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the associated WKPND bits being cleared. This

same procedure should be used following RESET, since the

L port inputs are left floating as a result of RESET.

INTERRUPTS

The device has a sophisticated interrupt structure to allow

easy interface to the real world. There are three possible in-

terrupt sources, as shown below.

A maskable interrupt on external G0 input (positive or nega-

tive edge sensitive under software control)

A maskable interrupt on timer carry or timer capture

A non-maskable software/error interrupt on opcode zero

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

Reg:WKPND. The respective bits of the WKPND register will

be set on the occurrence of the selected trigger edge on the

corresponding Port L pin. The user has the responsibility of

clearing these pending flags. Since the Reg:WKPND is a

pending register for the occurrence of selected wakeup con-

ditions, the device will not enter the HALT mode if any

Wakeup bit is both enabled and pending. Setting the G7 data

bit under this condition will not allow the device to enter the

HALT mode. Consequently, the user has the responsibility of

clearing the pending flags before attempting to enter the

HALT mode.

INTERRUPT CONTROL

The GIE (global interrupt enable) bit enables the interrupt

function. This is used in conjunction with ENI and ENTI to se-

lect one or both of the interrupt sources. This bit is reset

when interrupt is acknowledged.

ENI and ENTI bits select external and timer interrupts re-

spectively. Thus the user can select either or both sources to

interrupt the microcontroller when GIE is enabled.

=

IEDG selects the external interrupt edge (0 rising edge, 1

=

falling edge). The user can get an interrupt on both rising

and falling edges by toggling the state of IEDG bit after each

interrupt.

If a crystal oscillator is being used, the Wakeup signal will not

start the chip running immediately since crystal oscillators

have a finite start up time. The WATCHDOG timer prescaler

generates a fixed delay to ensure that the oscillator has in-

deed stabilized before allowing the device to execute in-

structions. In this case, upon detecting a valid Wakeup signal

only the oscillator circuitry and the WATCHDOG timer are

enabled. The WATCHDOG timer prescaler is loaded with a

value of FF Hex (256 counts) and is clocked from the tc in-

struction cycle clock. The tc clock is derived by dividing down

the oscillator clock by a factor of 10. A Schmitt trigger follow-

ing the CKI on chip inverter ensures that the WATCHDOG

timer is clocked only when the oscillator has a sufficiently

large amplitude to meet the Schmitt trigger specs. This

Schmitt trigger is not part of the oscillator closed loop. The

startup timeout from the WATCHDOG timer enables the

clock signals to be routed to the rest of the chip.

IPND and TPND bits signal which interrupt is pending. After

an interrupt is acknowledged, the user can check these two

bits to determine which interrupt is pending. This permits the

interrupts to be prioritized under software. The pending flags

have to be cleared by the user. Setting the GIE bit high in-

side the interrupt subroutine allows nested interrupts.

The software interrupt does not reset the GIE bit. This

means that the controller can be interrupted by other inter-

rupt sources while servicing the software interrupt.

INTERRUPT PROCESSING

The interrupt, once acknowledged, pushes the program

counter (PC) onto the stack and the stack pointer (SP) is

decremented twice. The Global Interrupt Enable (GIE) bit is

reset to disable further interrupts. The microcontroller then

vectors to the address 00FFH and resumes execution from

that address. This process takes 7 cycles to complete. At the

end of the interrupt subroutine, any of the following three in-

structions return the processor back to the main program:

RET, RETSK or RETI. Either one of the three instructions will

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16

DETECTION OF ILLEGAL CONDITIONS

Multi-Input Wake Up (Continued)

The device incorporates a hardware mechanism that allows

it to detect illegal conditions which may occur from coding er-

rors, noise, and “brown out” voltage drop situations. Specifi-

cally, it detects cases of executing out of undefined ROM

area and unbalanced tack situations.

pop the stack into the program counter (PC). The stack

pointer is then incremented twice. The RETI instruction addi-

tionally sets the GIE bit to re-enable further interrupts.

Any of the three instructions can be used to return from a

hardware interrupt subroutine. The RETSK instruction

should be used when returning from a software interrupt

subroutine to avoid entering an infinite loop.

Note: There is always the possibility of an interrupt occurring during an in-

struction which is attempting to reset the GIE bit or any other interrupt

enable bit. If this occurs when a single cycle instruction is being used

to reset the interrupt enable bit, the interrupt enable bit will be reset but

an interrupt may still occur. This is because interrupt processing is

started at the same time as the interrupt bit is being reset. To avoid this

scenario, the user should always use a two, three, or four cycle instruc-

tion to reset interrupt enable bits.

Reading an undefined ROM location returns 00 (hexadeci-

mal) as its contents. The opcode for a software interrupt is

also “00”. Thus a program accessing undefined ROM will

cause a software interrupt.

Reading an undefined RAM location returns an FF (hexa-

decimal). The subroutine stack on the device grows down for

each subroutine call. By initializing the stack pointer to the

top of RAM, the first unbalanced return instruction will cause

the stack pointer to address undefined RAM. As a result the

program will attempt to execute from FFFF (hexadecimal),

which is an undefined ROM location and will trigger a soft-

ware interrupt.

DS012529-20

FIGURE 16. Interrupt Block Diagram

Control Registers

CNTRL1 REGISTER (ADDRESS 00EE)

IPND External interrupt pending

BUSY MICROWIRE busy shifting flag

TC3 TC2 TC1 TRUN MSEL IEDG SL1

Bit 7

SL0

ENI

GIE

External interrupt enable

Bit 0

Global interrupt enable (enables interrupts)

The Timer and MICROWIRE control register contains the fol-

lowing bits:

The Half-Carry bit is also effected by all the instructions that

effect the Carry flag. The flag values depend upon the in-

struction. For example, after executing the ADC instruction

the values of the Carry and the Half-Carry flag depend upon

the operands involved. However, instructions like SET C and

RESET C will set and clear both the carry flags. Table *NO

TARGET FOR table NS2079* lists the instructions that effect

the HC and the C flags.

TC3

Timer T1 Mode Control Bit

TC2

Timer T1 Mode Control Bit

TC1

Timer T1 Mode Control Bit

TRUN

Used to start and stop the timer/counter

=

(1 run, 0 stop)

MSEL

IEDG

Selects G5 and G4 as MICROWIRE signals

SK and SO respectively

TABLE 9. Instructions Effecting HC and C Flags

External interrupt edge polarity select

Instr.

ADC

HC Flag

C Flag

SL1 and SL0 Select the MICROWIRE clock divide-by

=

Depends on

Operands

Depends on

Operands

(00 2, 01 4, 1x 8)

PSW REGISTER (ADDRESS 00EF)

SUBC

Depends on

Operands

Depends on

Operands

HC

C

TPND ENTI IPND BUSY ENI

GIE

SET C

RESET C

RRC

Set

Bit 7

Bit 0

The PSW register contains the following select bits:

Depends on

Operands

Depends on

Operands

HC

C

Half-Carry Flip/Flop

Carry Flip/Flop

TPND Timer T1 interrupt pending

(timer Underflow or capture edge)

ENTI Timer T1 interrupt enable

17

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Control Registers (Continued)

Address

E0 to EF

E0 to E7

E8

Contents

On-Chip Functions and Registers

Reserved for Future Parts

Reserved

CNTRL2 REGISTER (ADDRESS 00CC)

MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF Resvd

R/W R/W R/W

Bit 7

R/W

R/O

R/W

R/O

E9

MICROWIRE Shift Register

Timer Lower Byte

Bit 0

EA

MC3

MC2

MC1

Modulator/Timer Control Bit

EB

Timer Upper Byte

EC

Timer1 Autoreload Register Lower Byte

Timer1 Autoreload Register Upper Byte

CNTRL1 Control Register

PSW Register

ED

CMPEN Comparator Enable Bit

CMPRD Comparator Read Bit

EE

CMPOE Comparator Output Enable Bit

EF

WDUDF WATCHDOG Timer Underflow Bit (Read Only)

Resvd This bit is reserved and must be zero

F0 to FF

FC

On-Chip RAM Mapped as Registers

X Register

FD

SP Register

WDREG REGISTER (ADDRESS 00CD)

FE

B Register

UNUSED

Bit 7

WDREN

Reading other unused memory locations will return unde-

fined data.

Bit 0

WDREN WATCHDOG Reset Enable Bit (Write Once Only)

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

OPERAND ADDRESSING MODES

Address

Contents

REGISTER INDIRECT

00 to 2F

(820CJ)

On-chip RAM bytes (48 bytes)

This is the “normal” addressing mode for the chip. The oper-

and is the data memory addressed by the B or X pointer.

00 to 6F

(840CJ)

On-chip RAM bytes (112 bytes)

REGISTER INDIRECT WITH AUTO POST INCREMENT

OR DECREMENT

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

or X pointer. This is a register indirect mode that automati-

cally post increments or post decrements the B or X pointer

after executing the instruction.

30 to 7F

(820CJ)

Unused RAM Address Space (Reads as All

Ones)

70 to 7F

(840CJ)

Unused RAM Address Space (Reads as All

Ones)

80 to BF

Expansion Space for On-Chip EERAM

(Reads Undefined Data)

DIRECT

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

C0 to C7

C8

Reserved

MIWU Edge Select Register (Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

Reserved

IMMEDIATE

C9

The instruction contains an 8-bit immediate field as the oper-

and.

CA

SHORT IMMEDIATE

CB

This addressing mode issued with the LD B,# instruction,

where the immediate # is less than 16. The instruction con-

tains a 4-bit immediate field as the operand.

CC

Control2 Register (CNTRL2)

WATCHDOG Register (WDREG)

WATCHDOG Counter (WDCNT)

Modulator Reload (MODRL)

Port L Data Register

CD

CE

INDIRECT

CF

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

D0

D1

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

D2

D3

TRANSFER OF CONTROL ADDRESSING MODES

D4

Port G Data Register

RELATIVE

This mode is used for the JP instruction with the instruction

field being added to the program counter to produce the next

instruction address. JP has a range from −31 to +32 to allow

a one byte relative jump (JP + 1 is implemented by a NOP in-

struction). There are no “blocks” or “pages” when using JP

since all 15 bits of the PC are used.

D5

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Reserved for Port C

D6

D7

D8 to DB

DC

Port D Data Register

ABSOLUTE

DD to DF

Reserved for Port D

www.national.com

18

Addressing Modes (Continued)

This mode is used with the JMP and JSR instructions with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

ABSOLUTE LONG

This mode is used with the JMPL and JSRL instructions with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion up to 32k in the program memory space.

INDIRECT

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serves as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

Instruction Set

REGISTER AND SYMBOL DEFINITIONS

Registers

A

B

X

8-bit Accumulator register

8-bit Address register

SP 8-bit Stack pointer register

PC 15-bit Program counter register

PU upper 7 bits of PC

PL lower 8 bits of PC

C

1-bit of PSW register for carry

HC Half Carry

GIE 1-bit of PSW register for global interrupt enable

Symbols

[B]

Memory indirectly addressed by B register

Memory indirectly addressed by X register

Direct address memory or [B]

[X]

Mem

MemI

Imm

Reg

Direct address memory or [B] or Immediate data

8-bit Immediate data

Register memory: addresses F0 to FF (Includes B,

X and SP)

Bit

←

↔

Bit number (0 to 7)

Loaded with

Exchanged with

19

www.national.com

Instruction Set (Continued)

INSTRUCTION SET

←

ADD

ADC

add

A

A + MemI

←

add with carry

A + MemI + C, C

Carry

←

HC

Half Carry

←

SUBC

subtract with carry

A

A + MemI +C, C

←

HC

Half Carry

A and MemI

A or MemI

A xor MemI

←

AND

OR

Logical AND

A

←

Logical OR

XOR

IFEQ

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

X

Logical Exclusive-OR

IF equal

=

Compare A and MemI, Do next if A MemI

>

Compare A and MemI, Do next if A MemI

≠

Do next if lower 4 bits of B Imm

IF greater than

IF B not equal

←

Reg − 1, skip if Reg goes to 0

Decrement Reg. ,skip if zero

Set bit

Reg

=

1 to bit, Mem (bit 0 to 7 immediate)

0 to bit, Mem

Reset bit

If bit

If bit, Mem is true, do next instr.

↔

←

Exchange A with memory

Load A with memory

Load Direct memory Immed.

Load Register memory Immed.

Exchange A with memory [B]

Exchange A with memory [X]

Load A with memory [B]

Load A with memory [X]

Load Memory Immediate

Clear A

A

Mem

LD A

LD mem

LD Reg

X

MemI

←

Mem

Reg

Imm

←

Imm

↔

←

±

A

[B]

[X]

[B]

[X]

(B

(X

(B

(X

B

X

1)

↔

X

A

←

±

LD A

LD M

CLRA

INCA

DECA

LAID

DCORA

RRCA

SWAPA

SC

A

B

X

←

A

←

B

±

1)

[B]

Imm (B

←

A

C

0

←

→

Increment A

A + 1

A − 1

Decrement A

Load A indirect from ROM

DECIMAL CORRECT A

ROTATE A RIGHT THRU C

Swap nibbles of A

Set C

ROM(PU,A)

BCD correction (follows ADC, SUBC)

→

C

A7

…

A0

↔

A7 … A4

A3 … A0

←

C

1, HC

1

0

←

0, HC

RC

Reset C

IFC

If C

If C is true, do next instruction

IFNC

JMPL

JMP

If not C

If C is not true, do next instruction

←

=

ii (ii 15 bits, 0 to 32k)

Jump absolute long

Jump absolute

PC

PC11..0

←

=

i (i 12 bits)

←

PC

JP

Jump relative short

Jump subroutine long

Jump subroutine

Jump indirect

PC + r (r is −31 to +32, not 1)

←

ii

JSRL

JSR

[SP]

PL,[SP-1]

PU,SP-2,PC

←

PU,SP-2,PC11.. 0

i

←

ROM(PU,A)

JID

PL

←

RET

Return from subroutine

Return and Skip

Return from Interrupt

Generate an interrupt

No operation

SP+2,PL

[SP],PU

[SP-1]

[SP-1],Skip next instruction

RETSK

RETI

INTR

NOP

←

[SP-1],GIE

1

←

PU,SP-2,PC 0FF

[SP]

PL,[SP−1]

←

PC

PC + 1

www.national.com

20

0 – 3

B i t s

21

www.national.com

See the BYTES and CYCLES per INSTRUCTION table for

details.

Instruction Execution Time

Most instructions are single byte (with immediate addressing

mode instruction taking two bytes).

BYTES and CYCLES per

INSTRUCTION

Most single instructions take one cycle time to execute.

Skipped instructions require

x number of cycles to be

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

skipped, where x equals the number of bytes in the skipped

instruction opcode.

Arithmetic Instructions (Bytes/Cycles)

[B]

Direct

3/4

Immed.

2/2

ADD

ADC

SUBC

AND

OR

1/1

3/4

2/2

3/4

2/2

3/4

2/2

3/4

2/2

XOR

IFEQ

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

3/4

2/2

3/4

2/2

1/3

3/4

1/1

Memory Transfer Instructions (Bytes/Cycles)

Register

Register Indirect

Auto Incr & Decr

Indirect

[B] [X]

1/1 1/3

Direct

Immed.

[B+, B−]

[X+, X−]

1/3

*

X A,

2/3

1/2

*

LD A,

2/2

1/1

2/3

1/3

<

(If B 16)

LD B,Imm

>

(If B 15)

LD B,Imm

LD Mem,Imm

LD Reg,Imm

3/3

2/2

2/3

=

>

*

Memory location addressed by B or X or directly.

Instructions Using A & C

Transfer of Control Instructions

Instructions

Bytes/Cycles

Instructions

Bytes/Cycles

CLRA

1/1

1/3

1/1

JMPL

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

INCA

DECA

LAID

DCORA

RRCA

SWAPA

SC

JMP

JP

JSRL

JSR

JID

RET

RETSK

RETI

INTR

NOP

RC

IFC

IFNC

www.national.com

22

•

COP8C: Moderately priced C Cross-Compiler and Code

Development System from Byte Craft (no code limit). In-

cludes BCLIDE (Byte Craft Limited Integrated Develop-

ment Environment) for Win32, editor, optimizing C Cross-

Compiler, macro cross assembler, BC-Linker, and

MetaLink tools support. (DOS/SUN versions available;

Compiler is installable under WCOP8 IDE; Compatible

with DriveWay COP8).

Development Tools Support

OVERVIEW

National is engaged with an international community of inde-

pendent 3rd party vendors who provide hardware and soft-

ware development tool support. Through National’s interac-

tion and guidance, these tools cooperate to form a choice of

solutions that fits each developer’s needs.

•

EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-

bedded Workbench from IAR (Kickstart version:

COP8Sx/Fx only with 2k code limit; No FP). A fully inte-

grated Win32 IDE, ANSI C-Compiler, macro assembler,

editor, linker, Liberian, C-Spy simulator/debugger, PLUS

MetaLink EPU/DM emulator support.

This section provides a summary of the tool and develop-

ment kits currently available. Up-to-date information, selec-

tion guides, free tools, demos, updates, and purchase infor-

mation can be obtained at our web site at:

www.national.com/cop8.

EWCOP8-AS: Moderately priced COP8 Assembler and

Embedded Workbench from IAR (no code limit). A fully in-

tegrated Win32 IDE, macro assembler, editor, linker, li-

brarian, and C-Spy high-level simulator/debugger with

I/O and interrupts support. (Upgradeable with optional

C-Compiler and/or MetaLink Debugger/Emulator sup-

port).

SUMMARY OF TOOLS

COP8 Evaluation Tools

•

COP8–NSEVAL: Free Software Evaluation package for

Windows. A fully integrated evaluation environment for

COP8, including versions of WCOP8 IDE (Integrated De-

velopment Environment), COP8-NSASM, COP8-MLSIM,

™

COP8C, DriveWay COP8, Manuals, and other COP8

•

EWCOP8-BL: Moderately priced ANSI C-Compiler and

Embedded Workbench from IAR (Baseline version: All

COP8 devices; 4k code limit; no FP). A fully integrated

Win32 IDE, ANSI C-Compiler, macro assembler, editor,

linker, librarian, and C-Spy high-level simulator/debugger.

(Upgradeable; CWCOP8-M MetaLink tools interface sup-

port optional).

information.

•

COP8–MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

COP8–EPU: Very Low cost COP8 Evaluation & Pro-

gramming Unit. Windows based evaluation and

hardware-simulation tool, with COP8 device programmer

and erasable samples. Includes COP8-NSDEV, Drive-

way COP8 Demo, MetaLink Debugger, I/O cables and

power supply.

•

EWCOP8: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, and C-Spy high-level

simulator/debugger. (CWCOP8-M MetaLink tools inter-

face support optional).

•

COP8–EVAL-ICUxx: Very Low cost evaluation and de-

sign test board for COP8ACC and COP8SGx Families,

from ICU. Real-time environment with add-on A/D, D/A,

and EEPROM. Includes software routines and reference

designs.

EWCOP8-M: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, C-Spy high-level

simulator/debugger, PLUS MetaLink debugger/hardware

interface (CWCOP8-M).

Manuals, Applications Notes, Literature: Available free

from our web site at: www.national.com/cop8.

COP8 Integrated Software/Hardware Design Develop-

ment Kits

COP8 Productivity Enhancement Tools

•

WCOP8 IDE: Very Low cost IDE (Integrated Develop-

ment Environment) from KKD. Supports COP8C, COP8-

NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink

debugger under a common Windows Project Manage-

ment environment. Code development, debug, and emu-

lation tools can be launched from the project window

framework.

•

COP8-EPU: Very Low cost Evaluation & Programming

Unit. Windows based development and hardware-

simulation tool for COPSx/xG families, with COP8 device

programmer and samples. Includes COP8-NSDEV,

Driveway COP8 Demo, MetaLink Debugger, cables and

power supply.

•

COP8-DM: Moderate cost Debug Module from MetaLink.

A Windows based, real-time in-circuit emulation tool with

COP8 device programmer. Includes COP8-NSDEV,

DriveWay COP8 Demo, MetaLink Debugger, power sup-

ply, emulation cables and adapters.

•

DriveWay-COP8: Low cost COP8 Peripherals Code

Generation tool from Aisys Corporation. Automatically

generates tested and documented C or Assembly source

code modules containing I/O drivers and interrupt han-

dlers for each on-chip peripheral. Application specific

code can be inserted for customization using the inte-

grated editor. (Compatible with COP8-NSASM, COP8C,

and WCOP8 IDE.)

COP8 Development Languages and Environments

•

COP8-NSASM: Free COP8 Assembler v5 for Win32.

Macro assembler, linker, and librarian for COP8 software

development. Supports all COP8 devices. (DOS/Win16

v4.10.2 available with limited support). (Compatible with

WCOP8 IDE, COP8C, and DriveWay COP8).

•

COP8-UTILS: Free set of COP8 assembly code ex-

amples, device drivers, and utilities to speed up code de-

velopment.

•

COP8-NSDEV: Very low cost Software Development

Package for Windows. An integrated development envi-

ronment for COP8, including WCOP8 IDE, COP8-

NSASM, COP8-MLSIM.

COP8-MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

23

www.national.com

COP8 Device Programmer Support

Development Tools Support

•

MetaLink’s EPU and Debug Module include development

device programming capability for COP8 devices.

(Continued)

COP8 Real-Time Emulation Tools

•

Third-party programmers and automatic handling equip-

ment cover needs from engineering prototype and pilot

production, to full production environments.

•

COP8-DM: MetaLink Debug Module. A moderately

priced real-time in-circuit emulation tool, with COP8 de-

vice programmer. Includes COP8-NSDEV, DriveWay

COP8 Demo, MetaLink Debugger, power supply, emula-

tion cables and adapters.

•

Factory programming available for high-volume require-

ments.

•

IM-COP8: MetaLink iceMASTER^®. A full featured, real-

time in-circuit emulator for COP8 devices. Includes Met-

aLink Windows Debugger, and power supply. Package-

specific probes and surface mount adaptors are ordered

separately.

TOOLS ORDERING NUMBERS FOR THE COP87L20CJ/COP87L40CJ FAMILY DEVICES

Vendor

Tools

Order Number

COP8-NSEVAL

Cost

Notes

National COP8-NSEVAL

COP8-NSASM

COP8-MLSIM

COP8-NSDEV

COP8-EPU

Free Web site download

COP8-NSASM

Free Included in EPU and DM. Web site download

COP8-MLSIM

COP8-NSDEV

VL

Included in EPU and DM. Order CD from website

Not available for this device

Contact MetaLink

COP8-DM

Development

Devices

COP87L20/40CJxx

COP87L22/42CJxx

VL

L

4k or 32k OTP devices. No windowed devices

OTP

Programming

Adapters

COP8SA-PGMA

For programming 16/20/28 SOIC and 44 PLCC on the

EPU

COP8-PGMA-44QFP

COP8-PGMA-28CSP

COP8-PGMA-28SO

Contact MetaLink

L

For programming 44QFP on any programmer

For programming 28CSP on any programmer

For programming 16/20/28 SOIC on any programmer

L

VL

IM-COP8

MetaLink COP8-EPU

COP8-DM

Not available for this device

DM4-COP8-840CJ (10

MHz), plus PS-10, plus

DM-COP8/xxx (ie. 28D)

M

Included p/s (PS-10), target cable of choice (DIP or

PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and

44 PLCC programming sockets. Add OTP adapter (if

needed) and target adapter (if needed)

DM Target

Adapters

MHW-CONVxx (xx = 33,

34 etc.)

L

DM target converters for

16DIP/20/SO/28SO/44QFP/28CSP; (MHW-CNV38 for

20 pin DIP to SO package converter)

OTP

Programming

Adapters

MHW-COP8-PGMA-DS

For programming 16/20/28 SOIC and 44 PLCC on the

EPU

IM-COP8

IM-COP8-AD-464 (-220)

(10 MHz maximum)

H

Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

PC-840CJxxDW-AD-10

(xx = 20 or 28)

M

L

10 MHz 20 or 28 DIP probe card; 2.5V to 6.0V

IM Probe Target

Adapter

MHW-SOICxx (xx = 16,

20, 28)

16 or 20 or 28 pin SOIC adapter for probe card

ICU or

COP8-EVAL-ICUxx Not available for this device

National

KKD

IAR

WCOP8-IDE

EWCOP8-xx

COP8C

WCOP8-IDE

See summary above

COP8C

VL

Included in EPU and DM

L - H Included all software and manuals

Byte

Craft

M

Included all software and manuals

Aisys

DriveWay COP8

L

Included all software and manuals

www.national.com

24

Development Tools Support (Continued)

OTP Programmers

Contact vendor

L - H For approved programmer listings and vendor

information, go to our OTP support page at:

www.national.com/cop8

<

Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor

Home Office

U.S.A.: Santa Clara, CA

1-408-327-8820

Electronic Sites

Other Main Offices

Distributors

Aisys

www.aisysinc.com

@

info aisysinc.com

fax: 1-408-327-8830

U.S.A.

Byte Craft

IAR

www.bytecraft.com

Distributors

@

1-519-888-6911

info bytecraft.com

fax: 1-519-746-6751

Sweden: Uppsala

+46 18 16 78 00

fax: +46 18 16 78 38

www.iar.se

U.S.A.: San Francisco

1-415-765-5500

@

info iar.se

@

info iar.com

fax: 1-415-765-5503

U.K.: London

@

info iarsys.co.uk

@

info iar.de

+44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

Switzeland: Hoehe

+41 34 497 28 20

fax: +41 34 497 28 21

ICU

Sweden: Polygonvaegen

+46 8 630 11 20

www.icu.se

@

support icu.se

@

fax: +46 8 630 11 70

Denmark:

support icu.ch

KKD

www.kkd.dk

MetaLink

U.S.A.: Chandler, AZ

1-800-638-2423

www.metaice.com

Germany: Kirchseeon

80-91-5696-0

@

sales metaice.com

@

fax: 1-602-926-1198

support metaice.com

fax: 80-91-2386

@

bbs: 1-602-962-0013

www.metalink.de

islanger metalink.de

Distributors Worldwide

National

U.S.A.: Santa Clara, CA

1-800-272-9959

www.national.com/cop8

Europe: +49 (0) 180 530 8585

fax: +49 (0) 180 530 8586

Distributors Worldwide

@

support nsc.com

@

fax: 1-800-737-7018

europe.support nsc.com

The following companies have approved COP8 program-

mers in a variety of configurations. Contact your local office

or distributor. You can link to their web sites and get the lat-

est listing of approved programmers from National’s COP8

OTP Support page at: www.national.com/cop8.

Customer Support

Complete product information and technical support is avail-

able from National’s customer response centers, and from

our on-line COP8 customer support sites.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-

tems; ICE Technology; Lloyd Research; Logical Devices;

MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-

tem General; Tribal Microsystems; Xeltek.

25

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Surface Mount Package (M)

Order Number COP87L22CJM (-1B, -1N, -2B, -2N, -3B, -3N), or

Order Number COP87L42CJM (-1B, -1N, -2B, -2N, -3B, -3N), or

Order Number COP87L42RJM (-1B, -1N, -2B, -2N, -3B, -3N)

NS Package Number M20B

www.national.com

26

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Molded Dual-In-Line Package (N)

Order Number COP87L22CJN (-1N, -2N, -3N), or

Order Number COP87L42CJN (-1N, -2N, -3N), or

Order Number COP87L42RJN (-1N, -2N, -3N)

NS Package Number N20A

28-Lead Molded Dual-In-Line Package (M)

Order Number COP87L20CJM (-1N, -2N, -3N), or

Order Number COP87L40CJM (-1N, -2N, -3N), or

Order Number COP87L40RJM (-1N, -2N, -3N)

NS Package Number M28B

27

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Molded Dual-In-Line Package (N)

Order Number COP87L20CJN (-1N, -2N, -3N), or

Order Number COP87L40CJN (-1N, -2N, -3N), or

Order Number COP87L40RJN (-1N, -2N, -3N)

NS Package Number N28B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	COP87L20CJM-1B
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT, OTPROM, MICROCONTROLLER, PDSO28, PLASTIC, SOIC-28 可编程只读存储器时钟光电二极管外围集成电路
文件：	总28页 (文件大小：347K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

COP87L20CJM-1B [TI]

相关型号：

COP87L20CJM-1N

COP87L20CJM-2N

COP87L20CJM-3N

COP87L20CJN-1B

COP87L20CJN-1N

COP87L20CJN-2N

COP87L20CJN-3N

COP87L22CJ

COP87L22CJM-1B

COP87L22CJM-1N

COP87L22CJM-2N

COP87L22CJM-3B