COPC642-XXX/N [TI]
COPC642-XXX/N;
| 型号： | COPC642-XXX/N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | COPC642-XXX/N PC 微控制器 光电二极管 |
| 文件： | 总26页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2000
COP820C/840C Family
8-Bit CMOS ROM Based Microcontrollers with 1k or 2k
Memory
sions are available (COP87LxxCJ/RJ Family). Erasable win-
dowed versions are available for use with a range of COP8
software and hardware development tools.
General Description
Note: COP8SA devices are instruction set and pinout com-
patible supersets of the COP800C Family devices, and are
Family features include an 8-bit memory mapped architec-
replacements for these in new designs when possible.
ture, 10 Hz CKI with 1µs instruction cycle, one multi-function
The COP820C/840C Family ROM based microcontrollers
™
16-bit timer/counter with PWM, MICROWIRE/PLUS serial
™
are integrated COP8
Base core devices with smaller
I/O, power saving HALT mode, three clock modes, high cur-
rent outputs, software selectable I/O options, 2.3v-6.0v op-
eration and 20/28 pin packages.
memory (1k/2k), and fewer on-board features. These single-
chip CMOS devices are suited for lower-functionality appli-
cations where system cost is of prime consideration. Pin and
software compatible (different VCC range) 4k/32k OTP ver-
Devices included in this datasheet are:
Device
Memory (bytes)
RAM
(bytes)
64
I/O Pins
Packages
Temperature
Comments
COP620C
COP820C
COP920C
1k ROM
1k ROM
1k ROM
24
24
24
28 DIP/SOIC
28 DIP/SOIC
28 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
64
64
2.3v-4.0v,
CH=4.0v-6.0v
COP622C
COP822C
COP922C
1k ROM
1k ROM
1k ROM
64
64
64
16
16
16
20 DIP/SOIC
20 DIP/SOIC
20 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
COP640C
COP840C
COP940C
2k ROM
2k ROM
2k ROM
128
128
128
24
24
24
28 DIP/SOIC
28 DIP/SOIC
28 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
COP642C
COP842C
COP942C
2k ROM
2k ROM
2k ROM
128
128
128
16
16
16
20 DIP/SOIC
20 DIP/SOIC
20 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
— 20 DIP/SO with 16 I/O pins
— 28 DIP/SO with 24 I/O pins
Key Features
n 16-bit multi-function timer supporting
— PWM mode
CPU/Instruction Set Feature
n 1 µs instruction cycle time
— External event counter mode
— Input capture mode
n Three multi-source interrupts servicing
— External interrupt with selectable edge
— Timer interrupt
n 1024 bytes ROM/64 bytes RAM-COP820C
n 2048 bytes ROM/128 bytes RAM-COP840C
— Software interrupt
I/O Features
n Versatile and easy to use instruction set
n 8-bit Stack point (SP)—stack in RAM
n Two 8-bit Register Indirect Memory Pointers (B, X)
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Fully Static CMOS
n Low current drain (typically 1 µA)
n Single supply operation: 2.5V to 6.0V
n High current outputs
<
n Schmitt trigger inputs on Port G
n MICROWIRE/PLUS serial I/O
n Packages:
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
COP8 , MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS009103
www.national.com
n Real time emulation and full program debug offered by
MetaLink’s Development System
Fully Static CMOS (Continued)
n Temperature range: 0˚C to +70˚C, −40˚C to +85˚C,
−55˚C to +125˚C
Development Support
n Emulation and OTP devices
Block Diagram
DS009103-1
FIGURE 1.
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2
COP920C/COP922C/COP940C/COP942C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
50 mA
60 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at any Pin
)
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP92XC, COP94XC; 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
Units
COP9XXC
2.3
4.0
4.0
6.0
V
V
V
COP9XXCH
Power Supply Ripple (Note 2)
Supply Current (Note 3)
CKI = 10 MHz
CKI = 4 MHz
Peak to Peak
0.1 VCC
VCC = 6V, tc = 1 µs
6.0
4.0
2.0
1.2
8.0
5.0
mA
mA
mA
mA
µA
VCC = 6V, tc = 2.5 µs
VCC = 4V, tc = 2.5 µs
VCC = 4V, tc = 10 µs
VCC = 6V, CKI = 0 MHz
VCC = 4V, CKI = 0 MHz
CKI = 4 MHz
CKI = 1 MHz
<
<
HALT Current
(Note 4)
0.7
0.4
µA
Input Levels
RESET , CKI
Logic High
0.9 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
+1
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 6.0V
−1
µA
µA
V
VCC = 6.0V, VIN = 0V
−40
−250
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOL = 1.0V
VCC = 2.3V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
All Others
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 3.2V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOH = 3.8V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOL = 0.4V
VCC = 2.3V, VOL = 0.4V
VCC = 6.0V
−10
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
µA
0.7
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
−1.0
+1.0
D Outputs (Sink)
All Others
15
3
mA
mA
Maximum Input Current (Note 5)
Without Latchup (Room Temp)
±
Room Temp
100
mA
3
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DC Electrical Characteristics (Continued)
COP92XC, COP94XC; 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
RAM Retention Voltage, Vr
Input Capacitance
Condition
Min
Typ
Max
Units
V
500 ns Rise and Fall Time (Min)
2.0
7
pF
Load Capacitance on D2
1000
pF
Note 2: Rate of voltage change must be less than 0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G0 — G5 configured as
CC
outputs and set high. The D port set to zero.
Note 5: Except pin G7: +100 mA, −25 mA (COP920C only). Sampled and not 100% tested. Pins G6 and RESET are designed with a high voltage input network for
factory testing. These pins allow input voltages greater than V
and the pins will have sink current to V
when biased at voltages greater than V
(the pins do
CC
CC
CC
not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω (typical). These two pins will not latch up. The voltage at the
CC
CC
pins must be limited to less than 14V.
AC Electrical Characteristics
0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Condition
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Ext., Crystal/Resonator
(Div-by 10)
VCC ≥ 4.0V
2.3V ≤ VCC ≤ 4.0V
1
DC
DC
DC
DC
60
12
8
µs
µs
µs
µs
%
2.5
3
R/C Oscillator Mode
(Div-by 10)
VCC ≥ 4.0V
2.3V ≤ VCC ≤ 4.0V
fr = Max
7.5
40
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
ns
ns
tSETUP
VCC ≥ 4.0V
200
500
60
ns
ns
ns
ns
2.3V ≤ VCC ≤ 4.0V
VCC ≥ 4.0V
tHOLD
2.3V ≤ VCC ≤ 4.0V
CL = 100 pF, RL = 2.2 kΩ
150
Output Propagation Delay
tPD1, tPD0
SO, SK
VCC ≥ 4.0V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
2.5V ≤ VCC ≤ 4.0V
VCC ≥ 4.0V
All Others
2.5V ≤ VCC ≤ 4.0V
2.5
™
MICROWIRE Setup Time (tUWS
MICROWIRE Hold Time (tUWH
MICROWIRE Output Propagation
Delay (tUPD
)
20
56
)
220
ns
)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1.0
µs
Note 6: Parameter sampled (not 100% tested).
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4
COP820C/COP822C/COP840C/COP842C
Absolute Maximum Ratings (Note 7)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 7: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
50 mA
60 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at any Pin
)
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP82XC, COP84XC; −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
6.0
Units
2.5
V
V
Power Supply Ripple (Note 8)
Supply Current (Note 9)
CKI = 10 MHz
CKI = 4 MHz
Peak to Peak
0.1 VCC
VCC = 6V, tc = 1 µs
6.0
4.0
2.0
1.2
10
mA
mA
mA
mA
µA
VCC = 6V, tc = 2.5 µs
VCC = 4.0V, tc = 2.5 µs
VCC = 4.0V, tc = 10 µs
VCC = 6V, CKI = 0 MHz
CKI = 4 MHz
CKI = 1 MHz
<
HALT Current (Note 10)
Input Levels
1
RESET , CKI
Logic High
0.9 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
+2
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 6.0V
−2
µA
µA
V
VCC = 6.0V, VIN = 0V
−40
−250
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.5V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
All Others
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 3.2V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 0.4V
VCC = 2.5V, VOL = 0.4V
−10
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
µA
0.7
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
−2.0
+2.0
D Outputs (Sink)
All Others
15
3
mA
mA
Maximum Input Current (Note 11)
Without Latchup (Room Temp)
±
Room Temp
100
mA
RAM Retention Voltage, Vr
500 ns Rise and Fall Time
(Min)
2.0
V
Input Capacitance
7
pF
5
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DC Electrical Characteristics (Continued)
COP82XC, COP84XC; −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Condition
Min
Typ
Max
Units
Load Capacitance on D2
1000
pF
Note 8: Rate of voltage change must be less than 0.5V/ms.
Note 9: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 10: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G0 — G5 configured
CC
as outputs and set high. The D port set to zero.
Note 11: Except pin G7: +100 mA, −25 mA (COP820C only). Sampled and not 100% tested. Pins G6 and RESET are designed with a high voltage input network
for factory testing. These pins allow input voltages greater than V and the pins will have sink current to V when biased at voltages greater than V (the pins
CC
CC
CC
do not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω (typical). These two pins will not latch up. The voltage at
CC
CC
the pins must be limited to less than 14V.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Condition
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Ext. or Crystal/Resonator
(Div-by 10)
VCC ≥ 4.5V
1
DC
DC
DC
DC
60
12
8
µs
µs
µs
µs
%
<
2.5V ≤ VCC 4.5V
2.5
3
R/C Oscillator Mode
(Div-by 10)
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
7.5
40
CKI Clock Duty Cycle (Note 12)
Rise Time (Note 12)
Fall Time (Note 12)
Inputs
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
ns
ns
tSETUP
VCC ≥ 4.5V
200
500
60
ns
ns
ns
ns
<
2.5V ≤ VCC 4.5V
tHOLD
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
150
Output Propagation Delay
CL = 100 pF, RL = 2.2 kΩ
tPD1, tPD0
SO, SK
VCC ≥ 4.5V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
<
2.5V ≤ VCC 4.5V
All Others
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
2.5
MICROWIRE Setup Time (tUWS
MICROWIRE Hold Time (tUWH
MICROWIRE Output Propagation
Delay (tUPD
)
20
56
)
220
ns
)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1.0
µs
Note 12: Parameter sampled (not 100% tested).
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6
Timing Diagram
DS009103-19
FIGURE 2. MICROWIRE/PLUS Timing
7
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COP620C/COP622C/COP640C/COP642C
Absolute Maximum Ratings (Note 13)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 13: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
40 mA
48 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at any Pin
)
6V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP62XC, COP64XC; −55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
5.5
Units
4.5
V
V
Power Supply Ripple (Note 14)
Supply Current (Note 15)
CKI = 10 MHz
Peak to Peak
0.1 VCC
VCC = 5.5V, tc = 1 µs
VCC = 5.5V, tc = 2.5 µs
VCC = 5.5V, CKI = 0 MHz
6.0
4
mA
mA
µA
CKI = 4 MHz
<
HALT Current (Note 16)
Input Levels
10
30
RESET , CKI
Logic High
0.9 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
+5
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 5.5V
−5
µA
µA
V
VCC = 4.5V, VIN = 0V
−35
−300
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 4.5V, VOL = 1.0V
−0.35
9
mA
mA
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
VCC = 4.5V, VOH = 3.2V
VCC = 4.5V, VOH = 3.8V
VCC = 4.5V, VOL = 0.4V
−9
−0.35
1.4
−120
+5.0
µA
mA
mA
µA
−5.0
12
mA
mA
2.5
Maximum Input Current (Room Temp)
Without Latchup (Note 18)
±
Room Temp
100
mA
V
RAM Retention Voltage, Vr
500 ns Rise and Fall Time
(Min)
2.5
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
Note 14: Rate of voltage change must be less than 0.5V/ms.
Note 15: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 16: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G0 — G5 configured
CC
as outputs and set high. The D port set to zero.
Note 17: Except pin G7: +100 mA, −25 mA (COP620C only). Sampled and not 100% tested. Pins G6 and RESET are designed with a high voltage input network
for factory testing. These pins allow input voltages greater than V and the pins will have sink current to V when biased at voltages greater than V (the pins
CC
CC
CC
do not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω (typical). These two pins will not latch up. The voltage at
CC
CC
the pins must be limited to less than 14V.
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8
AC Electrical Characteristics
−55˚C ≤ TA≤+125˚C unless otherwise specified
Parameter
Condition
Min
1
Typ
Max
Units
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
VCC ≥ 4.5V
DC
µs
CKI Clock Duty Cycle (Note 18)
Rise Time (Note 18)
Fall Time (Note 18)
Inputs
fr = Max
40
60
12
8
%
ns
ns
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
tSETUP
VCC ≥ 4.5V
220
66
ns
ns
tHOLD
VCC ≥ 4.5V
Output Propagation Delay
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
VCC ≥ 4.5V
VCC ≥ 4.5V
0.8
1.1
µs
µs
ns
ns
All Others
MICROWIRE Setup Time (tUWS
MICROWIRE Hold Time (tUWH
MICROWIRE Output Valid Time
(tUPD
)
20
56
)
220
ns
)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1
µs
Note 18: Parameter sampled (not 100% tested).
Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C)
Halt—IDD
Dynamic—IDD (Crystal Clock Option)
DS009103-20
DS009103-21
9
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Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)
Port L/G Weak Pull-Up Source Current
Port L/G Push-Pull Source Current
DS009103-22
DS009103-23
Port L/G Push-Pull Sink Current
Port D Source Current
DS009103-24
DS009103-25
Port D Sink Current
DS009103-26
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10
Connection Diagrams
DUAL-IN-LINE PACKAGE
20 DIP
28 DIP
DS009103-3
Top View
Order Number COP622C-XXX/N,
COP642C-XXX/N, COP822C-XXX/N,
COP842C-XXX/N, COP922C-XXX/N,
COP942C-XXX/N, COP922CH-XXX/N or
COP942CH-XXX/N
DS009103-5
Order Number COP620C-XXX/N,
COP640C-XXX/N, COP820C-XXX/N,
COP840C-XXX/D,COP920C-XXX/N,
COP940C-XXX/N,
See NS Package Number N20A
COP920CH-XXX/N or
COP940CH-XXX/N
See NS Package Number N28B
SURFACE MOUNT
20 SO Wide
28-Lead SO
DS009103-2
Top View
Order Number COP822C-XXX/WM,
COP842C-XXX/WM, COP922C-XXX/WM,
COP942C-XXX/WM,
DS009103-18
Order Number COP820C-XXX/WM,
COP840C-XXX/WM,
COP922CH-XXX/WM or
COP920C-XXX/WM,
COP942CH-XXX/WM
COP940C-XXX/WM,
See NS Package Number M20B
COP920CH-XXX/WM or
COP940CH-XXX/WM
See NS Package Number M28B
11
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Connection Diagrams (Continued)
20 DIP/SO
28 DIP/SO
DS009103-6
DS009103-8
Six bits of Port G have alternate features:
G0 INTR (an external interrupt)
Pin Descriptions
VCC and GND are the power supply pins.
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
PORT I is a four bit Hi-Z input port.
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
PORT L is an 8-bit I/O port.
Pins G1 and G2 currently do not have any alternate func-
tions.
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
PORT D is a four bit output port that is set high when RESET
goes low. Care must be exercised with the D2 pin operation.
At RESET, the external load on this pin must ensure that the
output voltage stays above 0.9 VCC to prevent the device
from entering special modes. Also, keep the external loading
on the D2 pin to less than 1000 pf.
Port L
Port L
Port L
Setup
Config.
Data
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull “0” Output
Push-Pull “1” Output
Functional Description
Figure 1 shows the block diagram of the internal architec-
ture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
Three data memory address locations are allocated for
these ports, one for data register, one for configuration reg-
ister and one for the input pins.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown be-
low.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or shift
operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented.
Port G
Port G
Port G
Setup
Config.
Data
X is the 8-bit alternate address register, can be incremented
or decremented.
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull “0” Output
Push-Pull “1” Output
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
B, X and SP registers are mapped into the on chip RAM. The
B and X registers are used to address the on chip RAM. The
SP register is used to address the stack in RAM during sub-
routine calls and returns.
Three data memory address locations are allocated for
these ports, one for data register, one for configuration reg-
ister and one for the input pins. Since G6 and G7 are input
only pins, any attempt by the user to set them up as outputs
by writing a one to the configuration register will be disre-
garded. Reading the G6 and G7 configuration bits will return
zeros. Note that the chip will be placed in the HALT mode by
setting the G7 data bit.
PROGRAM MEMORY
Program memory for the COP820C family consists of 1024
bytes of ROM (2048 bytes of ROM for the COP840C family).
These bytes may hold program instructions or constant data.
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12
OSCILLATOR CIRCUITS
Functional Description (Continued)
Figure 4 shows the three clock oscillator configurations.
The program memory is addressed by the 15-bit program
counter (PC). ROM can be indirectly read by the LAID in-
struction for table lookup.
A. CRYSTAL OSCILLATOR
The device can be driven by a crystal clock. The crystal net-
work is connected between the pins CKI and CKO.
DATA MEMORY
Table 1 shows the component values required for various
standard crystal values.
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the in-
struction or indirectly by the B, X and SP registers.
B. EXTERNAL OSCILLATOR
The COP820C family has 64 bytes of RAM and the
COP840C family has 128 bytes of RAM. Sixteen bytes of
RAM are mapped as “registers” that can be loaded immedi-
ately, decremented or tested. Three specific registers: B, X
and SP are mapped into this space, the other bytes are
available for general usage.
CKI can be driven by an external clock signal. CKO is avail-
able as a general purpose input and/or HALT restart control.
C. R/C OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trig-
ger oscillator. CKO is available as a general purpose input
and/or HALT restart control.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except the A & PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested.
Table 2I shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports L and G are placed in
the TRI-STATE mode and the Port D is set high. The PC,
PSW and CNTRL registers are cleared. The data and con-
figuration registers for Ports L & G are cleared.
The external RC network shown in Figure 3 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
DS009103-10
FIGURE 4. Crystal and R-C Connection Diagrams
DS009103-9
OSCILLATOR MASK OPTIONS
RC ≥ 5X Power Supply Rise Time
The device can be driven by clock inputs between DC and
10 MHz.
FIGURE 3. Recommended Reset Circuit
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C
R1
(kΩ)
0
R2
(MΩ)
1
C1
(pF)
30
C2
(pF)
CKI Freq
(MHz)
10
Conditions
30–36
30–36
100–150
VCC = 5V
VCC = 5V
VCC = 5V
0
1
30
4
0
1
200
0.455
TABLE 2. RC Oscillator Configuration, TA = 25˚C
R
C
CKI Freq.
(MHz)
Instr. Cycle
(µs)
Conditions
(kΩ)
(pF)
82
3.3
5.6
6.8
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
VCC = 5V
VCC = 5V
VCC = 5V
100
100
Note 19: 3k ≤ R ≤ 200k, 50 pF ≤ C ≤ 200 pF
13
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ENI and ENTI bits select external and timer interrupt respec-
tively. Thus the user can select either or both sources to in-
terrupt the microcontroller when GIE is enabled.
Functional Description (Continued)
The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
IEDG selects the external interrupt edge (0 = rising edge, 1
= falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
•
•
•
Crystal (CKI/10) CKO for crystal configuration
External (CKI/10) CKO available as G7 input
R/C (CKI/10) CKO available as G7 input
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two bits
to determine which interrupt is pending. This permits the in-
terrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high in-
side the interrupt subroutine allows nested interrupts.
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.
HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock in-
put. In the HALT mode all internal processor activities includ-
ing the clock oscillator are stopped. The fully static architec-
ture freezes the state of the controller and retains all
information until continuing. In the HALT mode, power re-
quirements are minimal as it draws only leakage currents
and output current. The applied voltage (VCC) may be de-
creased down to Vr (minimum RAM retention voltage) with-
out altering the state of the machine.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At the
end of the interrupt subroutine, any of the following three in-
structions return the processor back to the main program:
RET, RETSK or RETI. Either one of the three instructions will
pop the stack into the program counter (PC). The stack
pointer is then incremented twice. The RETI instruction addi-
tionally sets the GIE bit to re-enable further interrupts.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address
0000H. A low to high transition on the CKO pin (only if the ex-
ternal or the R/C clock option is selected) causes the micro-
controller to continue with no reinitialization from the address
following the HALT instruction. This also resets the G7 data
bit.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
INTERRUPTS
There are three interrupt sources, as shown below.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset but
an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid this
scenario, the user should always use a two, three, or four cycle instruc-
tion to reset interrupt enable bits.
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to se-
lect one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
DS009103-11
FIGURE 5. Interrupt Block Diagram
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14
Master MICROWIRE/PLUS Operation
Functional Description (Continued)
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. (See Fig-
ure 7). The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting ap-
propriate bits in the Port G configuration register. Table 4
summarizes the bit settings required for Master mode of op-
eration.
DETECTION OF ILLEGAL CONDITIONS
The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding errors,
noise and ‘brown out’ voltage drop situations. Specifically it
detects cases of executing out of undefined ROM area and
unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also ’00’. Thus a program accessing undefined ROM will
cause a software interrupt.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table 4 summa-
rizes the settings required to enter the Slave mode of opera-
tion.
Reading an undefined RAM location returns an FF (hexa-
decimal). The subroutine stack grows down for each subrou-
tine call. By initializing the stack pointer to the top of RAM,
the first unbalanced return instruction will cause the stack
pointer to address undefined RAM. As a result the program
will attempt to execute from FFFF (hexadecimal), which is an
undefined ROM location and will trigger a software interrupt.
™
MICROWIRE/PLUS
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated. (See Figure 7.)
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with any of National Semi-
conductor’s MICROWIRE peripherals (i.e. A/D converters,
display drivers, EEPROMS, etc.) and with other microcon-
trollers which support the MICROWIRE/PLUS interface. It
consists of an 8-bit serial shift register (SIO) with serial data
input (SI), serial data output (SO) and serial shift clock (SK).
Figure 6 shows the block diagram of the MICROWIRE/PLUS
interface.
TABLE 4.
G4
G5
G4
G5
G6
Config. Config.
Operation
Fun.
Fun. Fun.
Bit
Bit
1
1
SO
TRI-STATE
SO
Int.
SK
SI
SI
SI
SI
MICROWIRE
Master
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS in-
terface with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE/
PLUS interface with an external shift clock is called the Slave
mode of operation.
0
1
0
1
0
0
Int.
SK
MICROWIRE
Master
Ext.
SK
MICROWIRE
Slave
TRI-STATE
Ext.
SK
MICROWIRE
Slave
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SL0 and SL1, in the
CNTRL register. Table 3I details the different clock rates that
may be selected.
TIMER/COUNTER
The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each orga-
nized as two 8-bit read/write registers. Control bits in the reg-
ister CNTRL allow the timer to be started and stopped under
software control. The timer-register pair can be operated in
one of three possible modes. Table 5 details various timer
operating modes and their requisite control settings.
TABLE 3.
SL1
0
SL0
SK Cycle Time
0
1
x
2tC
4tC
8tC
0
1
where,
tC is the instruction cycle clock.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the MICROWIRE/PLUS mode
either as a Master or as a Slave. Figure 7 shows how two mi-
crocontrollers and several peripherals may be intercon-
nected using the MICROWIRE/PLUS arrangement.
DS009103-12
FIGURE 6. MICROWIRE/PLUS Block Diagram
15
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to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are au-
tomatically copied into the counter. The underflow can also
be programmed to generate an interrupt. (See Figure 8)
Functional Description (Continued)
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the in-
struction cycle rate. Upon underflow the value in the register
R1 gets automatically reloaded into the timer which contin-
ues to count down. The timer underflow can be programmed
to interrupt the microcontroller. A bit in the control register
CNTRL enables the TIO (G3) pin to toggle upon timer under-
flows. This allow the generation of square-wave outputs or
pulse width modulated outputs under software control. (See
Figure 8)
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external fre-
quencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occur-
rence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger edge.
(See Figure 9.)
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
DS009103-13
FIGURE 7. MICROWIRE/PLUS Application
TABLE 5. Timer Operating Modes
CNTRL
Bits
Timer
Operation Mode
T Interrupt
Counts
7 6 5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
On
External Counter W/Auto-Load Reg.
External Counter W/Auto-Load Reg.
Not Allowed
Timer Underflow
Timer Underflow
Not Allowed
TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Timer W/Auto-Load Reg.
Timer W/Auto-Load Reg./Toggle TIO Out
Timer W/Capture Register
Timer W/Capture Register
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge
tC
tC
tC
tC
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16
Functional Description (Continued)
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG
External interrupt edge polarity select
(0 = rising edge, 1 = falling edge)
MSEL
Enable MICROWIRE/PLUS functions SO and
SK
TRUN
TC3
Start/Stop the Timer/Counter (1 = run, 0 = stop)
Timer input edge polarity select (0 = rising
edge, 1 = falling edge)
DS009103-15
TC2
TC1
Selects the capture mode
Selects the timer mode
FIGURE 8. Timer/Counter Auto
Reload Mode Block Diagram
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
Bit 7
Bit 0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
ENI
Global interrupt enable
External interrupt enable
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
DS009103-14
TPND Timer interrupt pending
FIGURE 9. Timer Capture Mode Block Diagram
C
Carry Flag
HC
Half carry Flag
TIMER PWM APPLICATION
Figure 10 shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Reload
mode. The timer is placed in the “Timer with auto reload”
mode and the TIO pin is selected as the timer output. At the
outset the TIO pin is set high, the timer T1 holds the on time
and the register R1 holds the signal off time. Setting TRUN
bit starts the timer which counts down at the instruction cycle
rate. The underflow toggles the TIO output and copies the off
time into the timer, which continues to run. By alternately
loading in the on time and the off time at each successive in-
terrupt a PWM frequency can be easily generated.
HC
Bit 7
C
TPND ENTI IPND BUSY ENI
GIE
Bit 0
Addressing Modes
REGISTER INDIRECT
This is the “normal” mode of addressing. The operand is the
memory addressed by the B register or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the oper-
and.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments
or decrements the B or X register after executing the instruc-
tion.
DS009103-16
RELATIVE
FIGURE 10. Timer Application
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program lo-
cation. JP has a range of from −31 to +32 to allow a one byte
relative jump (JP + 1 is implemented by a NOP instruction).
There are no ’pages’ when using JP, all 15 bits of PC are
used.
17
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Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
Contents
COP820C and COP840C Families
D7
Port I Input Pins (Read Only)
Reserved for Port C
D8–DB
DC
Address
Contents
Port D Data Register
Reserved for Port D
COP820C Family
DD–DF
00 to 2F
30 to 7F
On Chip RAM Bytes
E0 to EF On Chip Functions and Registers
Unused RAM Address Space (Reads as all
Ones)
E0–E7
E8
Reserved for Future Parts
Reserved
COP840C Family
00 to 6F
70 to 7F
On Chip RAM Bytes
E9
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Unused RAM Address Space (Reads as all
Ones)
EA
EB
Timer Upper Byte
COP820C and COP840C Families
EC
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
80 to BF
Expansion Space for on Chip EERAM
ED
C0 to CF Expansion Space for I/O and Registers
D0 to DF On Chip I/O and Registers
EE
EF
D0
D1
D2
D3
D4
D5
D6
Port L Data Register
F0 to FF
FC
On Chip RAM Mapped as Registers
X Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
FD
SP Register
FE
B Register
Port G Data Register
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
Port G Configuration Register
Port G Input Pins (Read Only)
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Symbols
[B]
[X]
Memory indirectly addressed by B register
Memory indirectly addressed by X register
Registers
A
B
X
8-bit Accumulator register
8-bit Address register
8-bit Address register
Mem Direct address memory or [B]
MemI Direct address memory or [B] or Immediate data
Imm 8-bit Immediate data
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU upper 7 bits of PC
Reg
Register memory: addresses F0 to FF (Includes B, X
and SP)
Bit
←
↔
Bit number (0 to 7)
Loaded with
PL lower 8 bits of PC
C
1-bit of PSW register for carry
Exchanged with
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
Instruction Set
←
ADD
ADC
add
A
A
A + MemI
←
←
add with carry
A + MemI + C, C
Carry
Carry
←
HC
Half Carry
←
←
SUBC
subtract with carry
A
A + MemI +C, C
←
HC
Half Carry
A and MemI
A or MemI
←
AND
OR
Logical AND
A
A
A
←
←
Logical OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
Logical Exclusive-OR
IF equal
A xor MemI
Compare A and MemI, Do next if A = MemI
>
Compare A and MemI, Do next if A MemI
IF greater than
IF B not equal
≠
Do next if lower 4 bits of B Imm
←
Reg − 1, skip if Reg goes to 0
Decrement Reg. ,skip if zero
Reg
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18
Instruction Set (Continued)
Instruction Set (Continued)
SBIT
RBIT
IFBIT
Set bit
Reset bit
If bit
1 to bit,
Mem (bit= 0 to 7 immediate)
0 to bit,
Mem
If bit,
Mem is true, do next instr.
↔
←
X
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
Clear A
A
A
Mem
LD A
LD mem
LD Reg
X
MemI
←
Mem
Reg
Imm
Imm
←
↔
←
←
←
←
±
B 1)
A
[B]
[X]
[B]
[X]
(B
(X
(B
(X
↔
±
X 1)
X
A
←
±
B 1)
LD A
LD A
LD M
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
A
←
±
X 1)
A
←
←
B 1)
±
[B]
Imm (B
←
A
A
A
A
A
C
0
←
←
←
←
→
Increment A
A + 1
A − 1
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
Set C
ROM(PU,A)
BCD correction (follows ADC, SUBC)
→
→
→
C
A7
…
A0
↔
A7 … A4
A3 … A0
←
←
←
C
C
1, HC
1
0
←
0, HC
RC
Reset C
IFC
If C
If C is true, do next instruction
IFNC
JMPL
JMP
If not C
If C is not true, do next instruction
←
ii (ii = 15 bits, 0 to 32k)
Jump absolute long
Jump absolute
PC
←
PC11..0
i (i = 12 bits)
PC + r (r is −31 to +32, not 1)
←
PC
JP
Jump relative short
Jump subroutine long
Jump subroutine
←
←
←
←
←
ii
JSRL
JSR
[SP]
[SP]
PL,[SP-1]
PL,[SP-1]
PU,SP-2,PC
←
PU,SP-2,PC11.. 0
i
←
ROM(PU,A)
JID
Jump indirect
PL
←
←
←
←
RET
Return from subroutine
Return and Skip
SP+2,PL
SP+2,PL
SP+2,PL
[SP],PU
[SP],PU
[SP],PU
[SP-1]
[SP-1],Skip next instruction
←
RETSK
RETI
INTR
NOP
←
←
Return from Interrupt
Generate an interrupt
No operation
[SP-1],GIE
1
←
←
←
PU,SP-2,PC 0FF
[SP]
PL,[SP−1]
←
PC
PC + 1
19
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Instruction Set (Continued)
0 – 3
B i t s
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20
Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instruction taking two bytes).
[B]
1/1
1/1
Direct
Immed.
IFGT
IFBNE
DRSZ
SBIT
3/4
2/2
Most single instructions take one cycle time to execute.
1/3
3/4
3/4
3/4
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
1/1
1/1
1/1
RBIT
IFBIT
See the BYTES and CYCLES per INSTRUCTION table for
details.
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do not
use these opcodes.
Bytes and Cycles per
Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Unused
Opcode
60
Unused
Opcode
A9
Instruction
Instruction
NOP
NOP
NOP
NOP
NOP
RET
NOP
NOP
61
AF
LD A, [B]
Arithmetic and Logic Instructions
→
HC
62
B1
C
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immed.
2/2
63
B4
NOP
NOP
ADD
ADC
SUBC
AND
OR
67
B5
3/4
2/2
8C
B7
X A, [X]
NOP
3/4
2/2
99
B9
3/4
2/2
#
9F
LD [B],
i
BF
LD A, [X]
3/4
2/2
A7
X A, [B]
NOP
XOR
IFEQ
3/4
2/2
A8
3/4
2/2
Memory Transfer Instructions
Register
Indirect
[B] [X]
1/1 1/3
1/1 1/3
Register Indirect
Auto Incr & Decr
Direct
Immed.
[B+, B−]
1/2
[X+, X−]
1/3
1/3
*
X A,
2/3
2/3
*
LD A,
2/2
1/1
2/3
1/2
<
(If B 16)
>
(If B 15)
LD B,Imm
LD B,Imm
LD Mem,Imm
LD Reg,Imm
2/2
3/3
2/2
2/3
>
Memory location addressed by B or X or directly.
*
Note 20:
=
Instructions Using A & C
Transfer of Control Instructions
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
RC
IFC
IFNC
21
www.national.com
COP8 Starter Kits and Hardware Target Solutions
Option List
•
COP8-EVAL-xxx: A variety of Multifunction Evaluation,
Design Test, and Target Boards for COP8 Families. Real-
time target design environments with a selection of pe-
ripherals and features including multi I/O, LCD display,
keyboard, A/D, D/A, EEPROM, USART, LEDs, and
bread-board area. Quickly design, test, and implement a
custom target system (some target boards are stand-
alone, and ready for mounting into a standard enclosure),
or just evaluate and test your code. Includes COP8-
NSDEV with IDE and Assembler, software routines, refer-
ence designs, and source code (no p/s).
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pat-
tern to provide the user with hardware flexibility to use a va-
riety of oscillator configuration.
OPTION 1: CKI INPUT
= 1 Crystal (CKI/10) CKO for crystal configuration
= 2 External (CKI/10) CKO available as G7 input
= 3 R/C
(CKI/10) CKO available as G7 input
OPTION 2: BONDING
= 1 28-pin DIP package
= 2 N.A.
COP8 Software Development Languages and Integrated
Environments
•
COP8-NSDEV: National’s COP8 Software Development
package for Windows on CD. A fully Integrated Develop-
ment Environment for COP8. Includes a fully licensed
WCOP8 IDE, COP8-NSASM. Plus Manuals, Applications
Software, and other COP8 technical information.
= 3 20-pin DIP package
= 4 20-SO package
= 5 28-SO package
The following option information is to be sent to National
along with the EPROM.
•
COP8C: ByteCraft - C Cross-Compiler and Code Devel-
opment System. Includes BCLIDE (Integrated Develop-
ment Environment) for Win32, editor, optimizing C Cross-
Compiler, macro cross assembler, BC-Linker, and
MetaLinktools support. (DOS/SUN versions available;
Compiler is linkable under WCOP8 IDE; Compatible with
DriveWay COP8)
Option Data
Option 1 Value__is: CKI Input
Option 2 Value__is: COP Bonding
•
EWCOP8, EWCOP8-M, EWCOP8-BL: IAR - ANSI
COP8 Tools Overview
C-Compiler and Embedded Workbench. (M version in-
cludes MetaLink debugger support) (BL version: 4k code
limit; no FP). A fully integrated Win32 IDE, ANSI
C-Compiler, macro assembler, editor, linker, librarian,
and C-Spy high-level simulator/debugger.
National is engaged with an international community of inde-
pendent 3rd party vendors who provide hardware and soft-
ware development tool support. Through National’s interac-
tion and guidance, these tools cooperate to form a choice of
tools that fits each developer’s needs.
COP8 Development Productivity Tools
This section provides a summary of the tool and develop-
ment kits currently available. Up-to-date information, selec-
tion guides, free tools, demos, updates, and purchase infor-
mation can be obtained at our web site at:
www.national.com/cop8.
•
DriveWay-COP8: Aisys Corporation - COP8 Peripherals
Code Generation tool. Automatically generates tested
and documented C or Assembly source code modules
containing I/O drivers and interrupt handlers for each on-
chip peripheral. Application specific code can be inserted
for customization using the integrated editor. (Compatible
with COP8-NSASM, COP8C, and WCOP8 IDE.)
SUMMARY OF TOOLS
COP8 Evaluation Software and Reference Designs
•
•
COP8-UTILS: COP8 assembly code examples, device
drivers, and utilities to speed up code development. (In-
cluded with COP8-NSDEV and COP8-NSEVAL.)
•
COP8–NSEVAL: Software Evaluation package for Win-
dows. A fully integrated evaluation environment for
COP8. Includes WCOP8 IDE evaluation version (Inte-
grated Development Environment), COP8-NSASM (Full
COP8 Assembler), COP8-MLSIM (COP8 Instruction
WCOP8 IDE: KKD - COP8 IDE (Integrated Development
Environment). Supports COP8C, COP8-NSASM, COP8-
MLSIM, DriveWay COP8, and MetaLink debugger under
a common Windows Project Management environment.
Code development, debug, and emulation tools can be
launched from a single project window framework. (In-
cluded in COP8-NSDEV and COP8-NSEVAL.)
™
Level Simulator), COP8C Compiler Demo, DriveWay
COP8 Device-Driver-Builder Demo, Manuals, Applica-
tions Software, and other COP8 technical information.
•
COP8–REF-xx: Reference Designs for COP8 Families.
Realtime hardware environment with a variety of func-
tions for demonstrating the various capabilities and fea-
tures of specific COP8 device families. Run Win 95 demo
reference software and exercise specific device capabili-
ties.
COP8 Hardware Debug Tools
•
COP8xx-DM: Metalink COP8 Debug Module for non-
flash COP8 Families. Windows based development and
real-time in-circuit emulation tool, with 100 frame trace,
32k s/w breaks, Enhanced User Interface, MetaLinkDe-
bugger, and COP8 OTP Programmer with sockets. In-
cludes COP8-NSDEV, power supply, DIP and/or SMD
emulation cables and adapters.
Includes PCB with pre-programmed COP8, 9v battery for
stand-alone operation, assembly listing, full applications
source code, BOM, and schematics.
(Add COP8-NSEVAL and an OTP programmer to imple-
ment your own software ideas in Assembly Code.)
www.national.com
22
•
Development: Metalink’s Debug Module includes devel-
opment device programming capability for COP8 de-
vices. Many other third-party programmers are approved
for development and engineering use.
COP8 Tools Overview (Continued)
•
IM-COP8: MetaLink iceMASTER® for non-flash COP8
devices. Windows based, full featured real-time in-circuit
emulator, with 4k trace, 32k s/w breaks, and MetaLink-
Windows Debugger. Includes COP8-NSDEV and power
supply. Package-specific probes and surface mount
adaptors are ordered separately. (Add COP8-PM and
adapters for OTP programming.)
•
•
Production: Third-party programmers and automatic
handling equipment cover needs from engineering proto-
type and pilot production, to full production environments.
Factory Programming: Factory programming available
for high-volume requirements.
COP8 Development and OTP Programming Tools
•
COP8-PM: COP8 Development Programming Module.
Windows programming tool for COP8 OTP Families. In-
cludes 40 DIP programming socket, control software,
RS232 cable, and power supply. (SMD and 87Lxx pro-
gramming adapters are extra.)
WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor
Home Office
U.S.A.: Santa Clara, CA
1-408-327-8820
Electronic Sites
Other Main Offices
Distributors
Aisys
www.aisysinc.com
@
info aisysinc.com
fax: 1-408-327-8830
U.S.A.
Byte Craft
IAR
www.bytecraft.com
Distributors
@
1-519-888-6911
info bytecraft.com
fax: 1-519-746-6751
Sweden: Uppsala
+46 18 16 78 00
fax: +46 18 16 78 38
www.iar.se
U.S.A.: San Francisco
1-415-765-5500
@
info iar.se
@
info iar.com
fax: 1-415-765-5503
U.K.: London
@
info iarsys.co.uk
@
info iar.de
+44 171 924 33 34
fax: +44 171 924 53 41
Germany: Munich
+49 89 470 6022
fax: +49 89 470 956
Switzeland: Hoehe
+41 34 497 28 20
fax: +41 34 497 28 21
ICU
Sweden: Polygonvaegen
+46 8 630 11 20
www.icu.se
@
support icu.se
@
fax: +46 8 630 11 70
Denmark:
support icu.ch
KKD
www.kkd.dk
MetaLink
U.S.A.: Chandler, AZ
1-800-638-2423
www.metaice.com
Germany: Kirchseeon
80-91-5696-0
@
sales metaice.com
@
fax: 1-602-926-1198
support metaice.com
fax: 80-91-2386
@
bbs: 1-602-962-0013
www.metalink.de
islanger metalink.de
Distributors Worldwide
National
U.S.A.: Santa Clara, CA
1-800-272-9959
www.national.com/cop8
Europe: +49 (0) 180 530 8585
fax: +49 (0) 180 530 8586
Distributors Worldwide
@
support nsc.com
@
europe.support nsc.com
fax: 1-800-737-7018
The following companies have approved COP8 program-
mers in a variety of configurations. Contact your local office
or distributor. You can link to their web sites and get the lat-
est listing of approved programmers from National’s COP8
OTP Support page at: www.national.com/cop8.
Logical Devices; MQP; Needhams; Phyton; SMS; Stag Pro-
grammers; System General; Tribal Microsystems; Xeltek.
CUSTOMER SUPPORT
Complete product information and technical support is avail-
able from National’s customer response centers, and from
our on-line COP8 customer support sites.
Advantech; Dataman; EE Tools; Minato; BP Microsystems;
Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research;
23
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Surface Mount Package (M)
Order Number COP820C-XXX/WM, COP840C-XXX/WM, COP920C-XXX/WM,
COP940C-XXX/WM, COP920CH-XXX/WM or COP940CH-XXX/WM
NS Package Number M28B
www.national.com
24
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Surface Mount Package (M)
Order Number COP822C-XXX/WM, COP842C-XXX/WM, COP922C-XXX/WM,
COP942C-XXX/WM, COP922CH-XXX/WM or COP942CH-XXX/WM
NS Package Number M20B
20-Lead Molded Dual-in-Line Package (N)
Order Number COP622C-XXX/N, COP642C-XXX/N, COP822C-XXX/N, COP842C-XXX/N,
COP922C-XXX/N, COP942C-XXX/N, COP922CH-XXX/N or COP942CH-XXX/N
NS Package Number N20A
25
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Molded Dual-in-Line Package (N)
Order Number COP620C-XXX/N, COP640C-XXX/N, COP820C-XXX/N, COP840C-XXX/N,
COP920C-XXX/N, COP940C-XXX/N, COP920CH-XXX/N or COP940CH-XXX/N
NS Package Number N28B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Email: nsj.crc@jksmtp.nsc.com
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 87 90
Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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