CSD13383F4 [TI]
采用 1mm x 0.6mm LGA 封装、具有栅极 ESD 保护的单路、44mΩ、12V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD13383F4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1mm x 0.6mm LGA 封装、具有栅极 ESD 保护的单路、44mΩ、12V、N 沟道 NexFET™ 功率 MOSFET 栅 开关 晶体管 栅极 |
| 文件： | 总15页 (文件大小：1738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD13383F4
ZHCSD46C –DECEMBER 2014 –REVISED FEBRUARY 2022
CSD13383F4 12V N 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
12
单位
V
漏源电压
• 低导通电阻
• 超低Qg 和Qgd
Qg
2.0
nC
总栅极电荷(4.5V)
Qgd
0.6
nC
• 超小封装尺寸（0402 外壳尺寸）
– 1.0mm × 0.6mm
• 薄型封装
栅极电荷（栅极到漏极）
漏源导通电阻
VGS = 2.5V
VGS = 4.5V
1.0
53
37
RDS(on)
VGS(th)
mΩ
V
阈值电压
– 厚度为0.36mm
• 集成型ESD 保护二极管
.
订购信息
– 额定值> 2kV 人体放电模型(HBM)
– 额定值> 2kV 充电器件模型(CDM)
• 无铅且无卤素
器件(1)
数量
3000
250
介质
封装
配送
卷带包装
CSD13383F4
CSD13383F4T
Femto (0402) 1.0mm ×
0.6mm 无引线SMD
7 英寸卷
带
• 符合RoHS
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 针对负载开关应用进行了优化
• 针对通用开关应用进行了优化
• 单节电池应用
绝对最大额定值
TA = 25°C
值
12
单位
V
VDS
• 手持式和移动类应用
漏源电压
VGS
ID
±10
V
栅源电压
3 说明
持续漏极电流(1)
脉冲漏极电流(1) (2)
持续栅极钳位电流
脉冲栅极钳位电流(1) (2)
功率耗散
2.9
18.5
25
A
A
该 37mΩ、12V N 沟道 FemtoFET™ MOSFET 技术经
过设计和优化，能够最大限度地减小在许多手持式和移
动应用中占用的空间。这项技术能够在替代标准小信号
MOSFET 的同时将封装尺寸减小至少60%。
IDM
IG
mA
250
500
2
PD
mW
kV
人体放电模型(HBM)
充电器件模型(CDM)
.
.
ESD
等级
2
kV
TJ、
Tstg
–55 至
150
工作结温
贮存温度
°C
雪崩能量，单脉冲ID = 6.7，
L = 0.1mH，RG = 25Ω
EAS
2.2
mJ
0.36 mm
(1) 典型RθJA = 250°C/W。
(2) 脉冲持续时间≤100μs，占空比≤1%.
1.00 mm
0.60 mm
D
图3-1. 典型器件尺寸
.
.
G
S
图3-2. 顶视图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS517
CSD13383F4
ZHCSD46C –DECEMBER 2014 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................3
6 Device and Documentation Support..............................7
6.1 支持资源......................................................................7
6.2 Trademarks.................................................................7
6.3 Electrostatic Discharge Caution..................................7
6.4 术语表......................................................................... 7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (December 2017) to Revision C (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• 将超薄型封装图片中的厚度从0.35mm 更新为0.36mm..................................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision A (January 2016) to Revision B (December 2017)
Page
• 将IDM 值从27A 更改为18.5A（位于绝对最大额定值表中）.............................................................................1
• Updated 图5-1. ................................................................................................................................................. 3
• Updated 图5-10 using Typ RθJA = 250°C/W. ................................................................................................... 3
• Updated all mechanical drawings, increased the size of the pads in the 节7.3 section. .................................. 8
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5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
12
V
µA
µA
V
VGS = 0 V, IDS = 250 μA
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 9.6 V
VDS = 0 V, VGS = 10 V
VDS = VGS, IDS = 250 μA
VGS = 2.5 V, IDS = 0.5 A
VGS = 4.5 V, IDS = 0.5 A
VDS = 6 V, IDS = 0.5 A
1
10
IGSS
VGS(th)
0.70
1.00
53
1.25
65
mΩ
mΩ
S
RDS(on)
gfs
Drain-to-source on-resistance
Transconductance
37
44
5.4
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
224
68
291
88
pF
pF
pF
VGS = 0 V, VDS = 6 V,
ƒ= 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
47
61
240
2.0
0.6
0.4
0.1
0.9
46
Ω
Qg
2.6
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 6 V, IDS = 0.5 A
VDS = 6 V, VGS = 0 V
Turn on delay time
Rise time
122
250
290
ns
VDS = 6 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 2 Ω
td(off)
tf
Turn off delay time
Fall time
ns
ns
DIODE CHARACTERISTICS
VSD Diode forward voltage
ISD = 0.5 A, VGS = 0 V
0.7
1.0
V
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
MIN
TYP
90
MAX
UNIT
RθJA
°C/W
250
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
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ZHCSD46C –DECEMBER 2014 –REVISED FEBRUARY 2022
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图5-1. Transient Thermal Impedance
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
TC = 125°C
TC = 25°C
TC = -55°C
0
0.1
0.2
VDS - Drain-to-Source Voltage (V)
0.3
0.4
0.5
0.6
0
0.2 0.4 0.6 0.8
1
VGS - Gate-to-Source Voltage (V)
1.2 1.4 1.6 1.8
2
D002
D003
VDS = 5 V
图5-2. Saturation Characteristics
图5-3. Transfer Characteristics
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5
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
4
3
2
1
0
0
2
4
6
8
VDS - Drain-to-Source Voltage (V)
10
12
0
0.25 0.5 0.75
1
1.25 1.5 1.75
Qg - Gate Charge (nC)
2
2.25 2.5
D005
D004
图5-5. Capacitance
ID = 0.5 A VDS = 6 V
图5-4. Gate Charge
1.45
1.3
90
80
70
60
50
40
30
TC = 25°C, ID = 0.5 A
TC = 125°C, ID = 0.5 A
1.15
1
0.85
0.7
0.55
0.4
20
0
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
2
4
6
VGS - Gate-to-Source Voltage (V)
8
10
D006
D007
ID = 250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
10
1.5
TC = 25°C
TC = 125°C
VGS = 2.5 V
VGS = 4.5 V
1.4
1.3
1.2
1.1
1
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD - Source-to-Drain Voltage (V)
1
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
D009
D008
图5-9. Typical Diode Forward Voltage
ID = 0.5 A
图5-8. Normalized On-State Resistance vs
Temperature
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ZHCSD46C –DECEMBER 2014 –REVISED FEBRUARY 2022
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100
10
1
10
TC = 25èC
TC = 125èC
100 ms
10 ms
1 ms
100 µs
10 µs
0.1
0.1
1
0.01
1
10
VDS - Drain-To-Source Voltage (V)
50
0.1
TAV - Time in Avalanche (ms)
1
D010
D011
Single Pulse, Typ RθJA = 250°C/W
图5-11. Single Pulse Unclamped Inductive
Switching
图5-10. Maximum Safe Operating Area (SOA)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
TC - Case Temperature (°C)
75
100 125 150 175
D012
图5-12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
6.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
1.04
B
A
0.96
PIN 1 INDEX AREA
0.64
0.56
0.36 MAX
C
SEATING PLANE
0.65
0.325
0.175
2
3
0.51
0.35
0.49
1
0.16
2X
0.14
0.26
0.015
C B
A
2X
0.26
0.24
0.015
0.24
C A
B
A. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME
Y14.5M.
B. This drawing is subject to change without notice.
C. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device data sheet or contact a
local TI representative.
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7.2 Recommended Minimum PCB Layout
(0.25)
2X (0.25)
PKG
0.05 MIN
ALL AROUND
2X (0.15)
1
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
PKG
2X (0.2)
(0.25)
1
SYMM
(0.5)
(0.4)
3
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
SOLDER PASTE EXAMPLE
A. All dimensions are in millimeters.
B. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design
recommendations.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD13383F4
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJC
YJC
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
GC
GC
CSD13383F4T
NIAU
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD13383F4
CSD13383F4
CSD13383F4T
CSD13383F4T
PICOST
AR
YJC
YJC
YJC
YJC
3
3
3
3
3000
3000
250
180.0
178.0
178.0
180.0
8.4
8.4
8.4
8.4
0.7
0.7
0.7
0.7
1.1
1.1
1.1
1.1
0.46
0.46
0.46
0.46
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
PICOST
AR
PICOST
AR
PICOST
AR
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD13383F4
CSD13383F4
CSD13383F4T
CSD13383F4T
PICOSTAR
PICOSTAR
PICOSTAR
PICOSTAR
YJC
YJC
YJC
YJC
3
3
3
3
3000
3000
250
182.0
220.0
220.0
182.0
182.0
220.0
220.0
182.0
20.0
35.0
35.0
20.0
250
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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