CSD15571Q2 [TI]
20-V N-Channel NexFET Power MOSFETs; 20 -V N通道NexFET功率MOSFET
| 型号： | CSD15571Q2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-V N-Channel NexFET Power MOSFETs |
| 文件： | 总10页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD15571Q2
www.ti.com
SLPS435 –AUGUST 2013
20-V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD15571Q2
1
FEATURES
PRODUCT SUMMARY
Drain to Source Voltage
2
•
•
•
•
•
•
•
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
VDS
Qg
20
2.5
V
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
nC
nC
mΩ
mΩ
V
Qgd
0.66
VGS = 4.5V
VGS = 10V
1.45
16
12
Pb Free Terminal Plating
RoHS Compliant
RDS(on) Drain to Source On Resistance
VGS(th) Threshold Voltage
Halogen Free
SON 2-mm × 2-mm Plastic Package
ORDERING INFORMATION
Device
CSD15571Q2
Package
Media
Qty
Ship
APPLICATIONS
SON 2-mm × 2-mm
Plastic Package
7-Inch
Reel
Tape and
Reel
3000
•
•
•
•
Optimized for Load Switch Applications
Storage, Tablets, and Handheld Devices
Optimized for Control FET Applications
Point of Load Synchronous Buck Converters
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
V
VDS
VGS
Drain to Source Voltage
20
Gate to Source Voltage
±20
22
V
DESCRIPTION
Continuous Drain Current (Package Limit)
Continuous Drain Current(1)
Pulsed Drain Current, TA = 25°C(2)
Power Dissipation(1)
A
ID
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion and load
management applications. The SON 2x2 offers
excellent thermal performance for the size of the
package.
10
A
IDM
PD
TJ,
52
A
2.5
W
Operating Junction and Storage
–55 to 150
18
°C
TSTG Temperature Range
Avalanche Energy, single pulse
ID = 19A, L = 0.1mH, RG = 25Ω
Top View
EAS
mJ
(1) RθJA = 50 on 1in² Cu (2 oz.) on .060" thick FR4 PCB.
D
D
G
1
2
3
6
5
4
D
D
S
D
(2) Pulse duration 10μs, duty cycle ≤2%
S
P0108-01
RDS(on) vs VGS
GATE CHARGE
30
28
26
24
22
20
18
16
14
12
10
8
10
TC = 25°C,I D = 5A
TC = 125°C,I D = 5A
ID = 5A
VDS =10V
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD15571Q2
SLPS435 –AUGUST 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise specified
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN TYP MAX UNIT
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
20
V
μA
nA
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
VGS = 0V, VDS = 20V
VDS = 0V, VGS = 20V
VDS = VGS, IDS = 250μA
VGS = 4.5V, IDS = 5A
VGS = 10V, IDS = 5A
VDS = 16V, IDS = 5A
1
IGSS
100
VGS(th)
1.10 1.45 1.90
16.0 19.2
12.0 15.0
25
mΩ
mΩ
S
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
Dynamic Characteristics
CISS
COSS
CRSS
Rg
Input Capacitance
320
184
32
419
239
42
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge Total (10V)
Gate Charge – Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0V, VDS = 10V, f = 1MHz
3.8
7.6
3.3
6.7
Qg
2.5
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
5.1
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
VDS = 10V, IDS = 5A
VDS = 10V, VGS = 0V
0.66
0.93
0.52
4.1
Turn On Delay Time
Rise Time
4.7
17.2
9.9
VDS = 10V, VGS = 4.5V, IDS = 5A
RG = 2Ω
td(off)
tf
Turn Off Delay Time
Fall Time
4.1
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
IDS = 5A, VGS = 0V
0.82
10.7
19
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDD = 10V, IF = 5A, di/dt = 300A/μs
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case(1)
Thermal Resistance Junction to Ambient(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
4.5
65
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
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Product Folder Links: CSD15571Q2
CSD15571Q2
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SLPS435 –AUGUST 2013
GATE
Source
GATE
Source
Max RθJA = 65 when
mounted on 1 inch2
(6.45 cm2) of 2-oz.
(0.071-mm thick) Cu.
Max RθJA = 235 when
mounted on minimum
pad area of 2-oz.
(0.071-mm thick) Cu.
DRAIN
DRAIN
M0164-02
M0164-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
50
45
40
35
30
25
20
15
10
5
30
27
24
21
18
15
12
9
VDS = 5V
VGS =10V
VGS =6V
VGS =4.5V
TC = 125°C
TC = 25°C
TC = −55°C
6
3
0
0
0
0.3
0.6
0.9
1.2
1.5
0
0.5
1
1.5
2
2.5
3
3.5
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2013, Texas Instruments Incorporated
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SLPS435 –AUGUST 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
1000
100
10
ID = 5A
VDS =10V
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
3
6
9
12
15
18
20
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
Figure 5. Capacitance
TEXT ADDED FOR SPACING
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
30
28
26
24
22
20
18
16
14
12
10
8
ID = 250uA
TC = 25°C,I D = 5A
TC = 125°C,I D = 5A
0.9
0.8
−75
−25
25
75
125
175
0
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
TEXT ADDED FOR SPACING
1.8
1.6
1.4
1.2
1
10
VGS = 4.5V
VGS = 10V
ID = 5A
TC = 25°C
TC = 125°C
1
0.1
0.01
0.001
0.0001
0.8
0.6
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
4
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CSD15571Q2
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SLPS435 –AUGUST 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
100
10
100
10
1
TC = 25ºC
TC = 125ºC
1ms
100ms
1s
DC
10ms
1
0.1
0.01
Single Pulse
TypicalRthetaJA =190ºC/W(min Cu)
0.1
0.001
0.01
0.1
1
10
50
0.01
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
27.0
24.0
21.0
18.0
15.0
12.0
9.0
6.0
3.0
0.0
−50 −25
0
25
50
75
100 125 150 175
TA - AmbientTemperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2013, Texas Instruments Incorporated
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SLPS435 –AUGUST 2013
www.ti.com
MECHANICAL DATA
Q2 Package Dimensions
D2
D
K2
K1
K3
6
5
4
4
5
6
1
2
3
3
2
1
Pin 1 ID
b
e
Pin 1 Dot
Top View
D1
Bottom View
Front View
M0165-01
DIM
MILLIMETERS
NOM
INCHES
NOM
MIN
MAX
0.800
0.050
0.350
MIN
MAX
0.032
0.002
0.014
A
A1
b
0.700
0.000
0.250
0.750
0.028
0.000
0.010
0.030
0.300
0.203 TYP
2.000 TYP
0.950
0.012
C
0.008 TYP
0.080 TYP
0.038
D
D1
D2
E
0.900
0.900
1.000
1.100
0.036
0.036
0.040
0.044
0.300 TYP
2.000 TYP
1.000
0.012 TYP
0.080 TYP
0.040
E1
E2
E3
e
0.280 TYP
0.470 TYP
0.650 BSC
0.280 TYP
0.350 TYP
0.200 TYP
0.200 TYP
0.470 TYP
0.25
0.0112 TYP
0.0188 TYP
0.026 TYP
0.0112 TYP
0.014 TYP
0.008 TYP
0.008 TYP
0.0188 TYP
0.010
K
K1
K2
K3
K4
L
0.200
0.300
0.008
0.012
6
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CSD15571Q2
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SLPS435 –AUGUST 2013
Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Pattern
Note: All dimensions are in mm, unless otherwise specified.
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www.ti.com
Q2 Tape and Reel Information
4.00 0.10
2.00 0.0ꢀ
Ø 1.ꢀ0 0.10
10° Max
4.00 0.10
Ø 1.00 0.2ꢀ
1.00 0.0ꢀ
0.2ꢀ4 0.02
10° Max
2.30 0.0ꢀ
M0168-01
Notes: 1. Measured from centerline of sprocket hole to centerline of pocket
2. Cumulative tolerance of 10 sprocket holes is ±0.20
3. Other material available
4. Typical SR of form tape Max 109 OHM/SQ
5. All dimensions are in mm, unless otherwise specified.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CSD15571Q2
ACTIVE
SON
DQK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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