CSD17382F4T [TI]
采用 1mm x 0.6mm LGA 封装、具有栅极 ESD 保护的单路、67mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150;
| 型号： | CSD17382F4T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1mm x 0.6mm LGA 封装、具有栅极 ESD 保护的单路、67mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150 栅 开关 脉冲 晶体管 栅极 |
| 文件： | 总13页 (文件大小：1172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD17382F4
SLPS562C – APRIL 2016 – REVISED FEBRUARY 2022
CSD17382F4 30-V N-Channel FemtoFET™ MOSFET
Product Summary
1 Features
TA = 25°C
TYPICAL VALUE
UNIT
V
•
•
•
•
Low on-resistance
Low Qg and Qgd
Low threshold voltage
Ultra-small footprint (0402 case size)
– 1.0 mm × 0.6 mm
Ultra-low profile
VDS
Qg
Drain-to-Source Voltage
30
2.1
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
nC
nC
mΩ
mΩ
mΩ
mΩ
V
Qgd
0.63
VGS = 1.8 V
110
67
VGS = 2.5 V
VGS = 4.5 V
VGS = 8.0 V
RDS(on) Drain-to-Source On-Resistance
•
•
56
– 0.36-mm height
54
Integrated ESD protection diode
– Rated > 3-kV HBM
– Rated > 2-kV CDM
Lead and halogen free
RoHS compliant
VGS(th) Threshold Voltage
0.9
.
Device Information
•
•
DEVICE(1)
CSD17382F4
CSD17382F4T
QTY
3000
250
MEDIA
PACKAGE
SHIP
7-Inch
Reel
Femto (0402) 1.0-mm ×
0.6-mm SMD Lead Less
Tape and
Reel
2 Applications
•
•
Optimized for load switch applications
Optimized for general purpose switching
applications
Single-cell battery applications
Handheld and mobile applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
•
•
TA = 25°C
VALUE
UNIT
V
VDS
VGS
ID
Drain-to-Source Voltage
30
3 Description
Gate-to-Source Voltage
Continuous Drain Current(1)
Pulsed Drain Current(2)
Power Dissipation(1)
10
V
This 30-V, 54-mΩ, N-Channel FemtoFET™ MOSFET
technology is designed and optimized to minimize the
footprint in many handheld and mobile applications.
This technology is capable of replacing standard
small signal MOSFETs while providing at least a 60%
reduction in footprint size.
2.3
A
IDM
PD
14.8
500
A
mW
V
Human Body Model (HBM)
Charged Device Model (CDM)
3000
2000
ESD
Rating
V
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 150
2.1
°C
.
Avalanche Energy, Single Pulse ID = 6.5 A,
L = 0.1 mH, RG = 25 Ω
EAS
mJ
(1) Typical RθJA = 245°C/W on 1-in2 (6.45-cm2), 2-oz.
0.36 mm
(0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4
PCB.
(2) Pulse duration ≤100 μs, duty cycle ≤1%.
1.00 mm
0.60 mm
D
Typical Part Dimensions
.
.
.
.
G
S
Top View
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17382F4
SLPS562C – APRIL 2016 – REVISED FEBRUARY 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
6 Device and Documentation Support..............................7
6.1 Support Resources..................................................... 7
6.2 Receiving Notification of Documentation Updates......7
6.3 Trademarks.................................................................7
6.4 Electrostatic Discharge Caution..................................7
6.5 Glossary......................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
7.4 CSD17382F4 Embossed Carrier Tape Dimensions..10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2021) to Revision C (February 2022)
Page
•
•
•
•
Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1
Updated ultra-low profile image height from 0.35 mm to 0.36 mm.....................................................................1
Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision A (December 2016) to Revision B (October 2021)
Page
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Changes from Revision * (April 2016) to Revision A (December 2016)
Page
•
Changed the TEST CONDITIONS for gfsTransconductance From: VDS = 15 V To: VDS = 3 V in the Section
5.1 section. ........................................................................................................................................................ 3
Added Section 6.2 in the Section 6 section. ...................................................................................................... 7
Updated all mechanical drawings. .....................................................................................................................8
•
•
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SLPS562C – APRIL 2016 – REVISED FEBRUARY 2022
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
30
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = 10 V
VDS = VGS, IDS = 250 μA
VGS = 1.8 V, IDS =0.5 A
VGS = 2.5 V, IDS =0.5 A
VGS = 4.5 V, IDS = 0.5 A
VGS = 8.0 V, IDS = 0.5 A
VDS = 3 V, IDS = 0.5 A
1
5
µA
µA
V
IGSS
VGS(th)
0.7
0.9
110
67
1.2
180
82
mΩ
mΩ
mΩ
mΩ
S
RDS(on)
Drain-to-source on-resistance
56
67
54
64
gfs
Transconductance
5.9
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
267
31.0
15.0
220
2.1
347
40.3
19.5
pF
pF
pF
Ω
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
Qg
2.7
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
0.63
0.41
0.12
1.53
59
VDS = 15 V, IDS = 0.5 A
VDS = 15 V, VGS = 0 V
Turn on delay time
Rise time
111
VDS = 15 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 0 Ω
td(off)
tf
Turn off delay time
Fall time
279
270
DIODE CHARACTERISTICS
VSD Diode forward voltage
ISD = 0.5 A, VGS = 0 V
0.7
1.0
V
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
TYPICAL VALUES
UNIT
°C/W
°C/W
85
RθJA
245
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz. (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 5-1. Transient Thermal Impedance
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
VGS = 1.8 V
VGS = 2.5 V
VGS = 4.5 V
VGS = 8.0 V
TC = 125°C
TC = 25°C
TC = -55°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VDS - Drain-to-Source Voltage (V)
1
0
0.5
1
1.5
VGS - Gate-to-Source Voltage (V)
2
2.5
3
D002
D003
VDS = 5 V
Figure 5-2. Saturation Characteristics
Figure 5-3. Transfer Characteristics
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8
7
6
5
4
3
2
1
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
0
0
3
6
9
12
15
18
21
VDS - Drain-to-Source Voltage (V)
24
27
30
0.4 0.8 1.2 1.6
2
Qg - Gate Charge (nC)
2.4 2.8 3.2 3.6
4
D005
D004
Figure 5-5. Capacitance
ID = 0.5 A
VDS = 15 V
Figure 5-4. Gate Charge
1.3
1.2
1.1
1
130
120
110
100
90
TC = 25°C, ID = 0.5 A
TC = 125°C, ID = 0.5 A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
80
70
60
50
40
0
1
2
3
4
5
6
7
VGS - Gate-to-Source Voltage (V)
8
9
10
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
D007
D006
Figure 5-7. On-State Resistance vs Gate-to-Source
Voltage
ID = 250 µA
Figure 5-6. Threshold Voltage vs Temperature
10
1.5
TC = 25èC
TC = 125èC
VGS = 2.5 V
VGS = 8.0 V
1.4
1.3
1.2
1.1
1
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.2
0.4
0.6
VSD - Source-To-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
75 100 125 150 175
D009
TC - Case Temperature (èC)
D008
Figure 5-9. Typical Diode Forward Voltage
ID = 0.5 A
Figure 5-8. Normalized On-State Resistance vs
Temperature
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100
10
1
100
10
1
TC = 25è C
TC = 125è C
0.1
100 ms
10 ms
1 ms
100 µs
10 µs
0.01
0.1
0.1
0.001
1
10
VDS - Drain-To-Source Voltage (V)
100
0.01
TAV - Time in Avalanche (ms)
0.1
D010
D011
Single Pulse, Typ RθJA = 245°C/W (min Cu)
Figure 5-11. Single Pulse Unclamped Inductive
Switching
Figure 5-10. Maximum Safe Operating Area (SOA)
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
TA - Ambient Temperature (°C)
75
100 125 150 175
D012
Typical RθJA = 245°C/W (min Cu)
Figure 5-12. Maximum Drain Current vs Temperature
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SLPS562C – APRIL 2016 – REVISED FEBRUARY 2022
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6 Device and Documentation Support
6.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
6.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.3 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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SLPS562C – APRIL 2016 – REVISED FEBRUARY 2022
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
1.04
B
A
0.96
PIN 1 INDEX AREA
0.64
0.56
0.36 MAX
C
SEATING PLANE
0.65
0.325
0.175
2
3
0.51
0.35
0.49
1
0.16
2X
0.14
0.26
0.015
C B
A
2X
0.26
0.24
0.015
0.24
C A
B
A. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME
Y14.5M.
B. This drawing is subject to change without notice.
C. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device datasheet or contact a
local TI representative.
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7.2 Recommended Minimum PCB Layout
(0.25)
2X (0.25)
PKG
0.05 MIN
ALL AROUND
2X (0.15)
1
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
PKG
2X (0.2)
(0.25)
1
SYMM
3
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
SOLDER PASTE EXAMPLE
A. All dimensions are in millimeters.
B. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design
recommendations.
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7.4 CSD17382F4 Embossed Carrier Tape Dimensions
A. Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD17382F4
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJC
YJC
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
HM
HM
CSD17382F4T
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
Addendum-Page 2
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相关型号：
CSD17484F4T
采用 1mm x 0.6mm LGA 封装、具有栅极 ESD 保护的单路、128mΩ、30V、N 沟道 NexFET™ 功率 MOSFET | YJJ | 3 | -55 to 150
TI
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