CSD17570Q5B [TI]
采用 5mm x 6mm SON 封装的单路、0.92mΩ、30V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD17570Q5B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的单路、0.92mΩ、30V、N 沟道 NexFET™ 功率 MOSFET |
| 文件： | 总13页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
CSD17570Q5B 30V N 沟道 NexFET™功率金属氧化物半导体场效应晶体
管 (MOSFET)
1 特性
产品概要
1
•
•
•
•
•
•
•
超低电阻
TA = 25°C
VDS
典型值
30
单位
V
低热阻
漏源电压
雪崩级
Qg
栅极电荷总量 (4.5V)
栅极电荷（栅极到漏极）
93
nC
nC
mΩ
mΩ
V
无铅引脚镀层
Qgd
34
VGS = 4.5V
VGS = 10V
1.5
0.74
0.56
符合 RoHS 标准
RDS(on) 漏源导通电阻
VGS(th) 阈值电压
无卤素
小外形尺寸无引线 (SON) 5mm x 6mm 塑料封装
订购信息(1)
2 应用
器件
数量
2500 13 英寸卷带
250 7 英寸卷带
介质
封装
出货
卷带封装
•
ORing 和热插拔 应用
CSD17570Q5B
CSD17570Q5BT
SON 5mm x 6mm
塑料封装
3 说明
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
这款 30V，0.56mΩ，SON 5mm × 6mmNexFET™功
率 MOSFET 旨在最大限度地减小 ORing 和热拔插应
用的 电阻， 不可用于开关 应用。
绝对最大额定值
TA = 25°C
值
30
单位
V
VDS
VGS
漏源电压
顶部图标
栅源电压
±20
100
V
持续漏极电流（受封装限制）
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
持续漏极电流（受芯片限制），TC = 25°C
时测得
ID
407
A
持续漏极电流，TA = 25°C 时测得(1)
脉冲漏极电流，TA = 25°C 时测得(2)
功率耗散(1)
53
400
3.2
IDM
PD
A
W
TJ， 运行结温和
-55 至 150
°C
Tstg
储存温度范围
D
D
雪崩能量，单脉冲
ID = 90A，L = 0.1mH，RG = 25Ω
EAS
450
mJ
P0093-01
(1) RθJA = 40°C/W，这是在厚度为 0.06 英寸的环氧板 (FR4) 印刷
电路板 (PCB) 上的 1 英寸2 2 盎司的铜焊盘上测得的典型值。
.
.
(2) 脉冲持续时间 ≤ 100μs，占空比 ≤ 2%
.
RDS(on) 与 VGS 对比
栅极电荷
2
1.8
1.6
1.4
1.2
1
10
TC = 25°C,I D = 50A
TC = 125°C,I D = 50A
ID = 50A
VDS = 15V
9
8
7
6
5
4
3
2
1
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
0
20
40
60
80 100 120 140 160 180 200
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS471
CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
www.ti.com.cn
目录
6.1 接收文档更新通知 ..................................................... 7
6.2 社区资源.................................................................... 7
6.3 商标........................................................................... 7
6.4 静电放电警告............................................................. 7
6.5 Glossary.................................................................... 7
机械、封装和可订购信息 ......................................... 8
7.1 Q5B 封装尺寸............................................................ 8
7.2 建议 PCB 布局 .......................................................... 9
7.3 建议模板布局........................................................... 10
7.4 Q5B 卷带信息.......................................................... 10
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
器件和文档支持........................................................ 7
7
6
4 修订历史记录
Changes from Revision C (January 2015) to Revision D
Page
•
•
已添加 “接收文档更新通知”和“社区资源”部分添加到了“器件和文档支持”。............................................................................ 7
已更改 将建议 PCB 布局 部分方框图中.................................................................................................................................. 9
Changes from Revision B (August 2014) to Revision C
Page
•
已将脉冲漏极电流更正为 400A。 ........................................................................................................................................... 1
Changes from Revision A (May 2014) to Revision B
Page
•
•
Updated Figure 1 to state Max RθJC = 0.8ºC/W. .................................................................................................................... 4
Updated the SOA in Figure 10. ............................................................................................................................................. 6
Changes from Original (February 2014) to Revision A
Page
•
更新了机械制图。................................................................................................................................................................... 8
2
版权 © 2014–2017, Texas Instruments Incorporated
CSD17570Q5B
www.ti.com.cn
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
30
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 50 A
VGS = 10 V, ID = 50 A
VDS = 15 V, ID = 50 A
1
100
1.9
μA
nA
V
IGSS
VGS(th)
1.1
1.5
0.74
0.56
271
0.92
0.69
mΩ
mΩ
S
RDS(on)
gfs
Drain-to-Source On-Resistance
Transconductance
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input Capacitance
10400 13600
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 15 V, ƒ = 1 MHz
1450
877
1.8
93
1890
1140
3.6
Qg
121
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
34
VDS = 15 V, ID = 50 A
VDS = 15 V, VGS = 0 V
27
17
40
Turn On Delay Time
Rise Time
5
36
VDS = 15 V, VGS = 10 V,
IDS = 50 A, RG = 0 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
144
74
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
ISD = 50 A, VGS = 0 V
0.8
34
51
1
V
nC
ns
VDS= 15 V, IF = 50 A,
di/dt = 300 A/μs
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-Case Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(1)(2)
MIN
TYP
MAX
UNIT
RθJC
RθJA
0.8
50
°C/W
(1)
R
θJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
Copyright © 2014–2017, Texas Instruments Incorporated
3
CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
www.ti.com.cn
GATE
Source
GATE
Source
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2 oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
Copyright © 2014–2017, Texas Instruments Incorporated
CSD17570Q5B
www.ti.com.cn
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
200
200
180
160
140
120
100
80
VDS = 5V
180
160
140
120
100
80
60
60
VGS =10V
VGS =6V
VGS =4.5V
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
40
20
0
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
VDS - Drain-to-Source Voltage (V)
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
100000
10000
1000
ID = 50A
VDS = 15V
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
100
0
20
40
60
80 100 120 140 160 180 200
3
6
9
12
15
18
21
24
27
30
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
2
1.8
1.6
1.4
1.2
1
ID = 250uA
TC = 25°C,I D = 50A
TC = 125°C,I D = 50A
0.8
0.6
0.4
0.2
0
−75 −50 −25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2014–2017, Texas Instruments Incorporated
5
CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
1.8
100
10
VGS = 4.5V
VGS = 10V
TC = 25°C
TC = 125°C
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
ID =50A
−75 −50 −25
0
25 50 75 100 125 150 175 200
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
5000
200
100
TC = 25ºC
TC = 125ºC
10us
100us
1ms
10ms
DC
1000
100
10
1
Single Pulse
Max RthetaJC = 0.8ºC/W
0.1
0.1
10
0.01
1
10
100
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
120
100
80
60
40
20
0
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
6
Copyright © 2014–2017, Texas Instruments Incorporated
CSD17570Q5B
www.ti.com.cn
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
6 器件和文档支持
6.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
6.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2014–2017, Texas Instruments Incorporated
7
CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
www.ti.com.cn
7 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
7.1 Q5B 封装尺寸
K
c1
H
L
E1
•
d1
d2
Top View
Side View
Bottom View
•
Front View
毫米
标称值
1.00
0.41
0.20
0.20
0.25
5.00
4.22
4.00
0.25
DIM
最小值
0.80
0.36
0.15
0.15
0.20
4.90
4.12
3.90
0.20
最大值
1.05
0.46
0.25
0.25
0.30
5.10
4.32
4.10
0.30
A
b
c
c1
c2
D1
D2
D3
d
d1
d2
E
0.085 典型值
0.369
0.319
4.90
5.90
3.48
0.419
5.10
6.10
3.68
5.00
E1
E2
e
6.00
3.58
1.27 典型值
0.46
H
0.36
0.46
0.57
0°
0.56
0.66
0.77
-
L
0.56
L1
θ
0.67
-
K
1.40 典型值
8
版权 © 2014–2017, Texas Instruments Incorporated
CSD17570Q5B
www.ti.com.cn
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
7.2 建议 PCB 布局
，焊盘 3 和 4 之间的尺寸从 0.028 英寸更改为了 0.050 英寸
要获得与印刷电路板 (PCB) 设计相关的建议电路布局布线，请参见《应用说明》SLPA005 - 通过 PCB 布局布线技
巧来减少振铃。
版权 © 2014–2017, Texas Instruments Incorporated
9
CSD17570Q5B
ZHCSC48D –FEBRUARY 2014–REVISED MAY 2017
www.ti.com.cn
7.3 建议模板布局
(0.020)
(0.014)
0.350
0.508
x4
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
(0.086)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.050)
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
7.4 Q5B 卷带信息
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
注释：
1. 10 个链齿孔的累积容差为 ±0.2
2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积
3. 材料：黑色抗静电聚苯乙烯
4. 全部尺寸单位为 mm（除非另外注明）。
5. 高于孔眼底部 0.3mm 的平面上测量得到 A0 和 B0 值.
10
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD17570Q5B
CSD17570Q5BT
ACTIVE
VSON-CLIP
VSON-CLIP
DNK
8
8
RoHS-Exempt
& Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD17570
CSD17570
ACTIVE
DNK
RoHS-Exempt
& Green
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
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