CSD18512Q5B [TI]
采用 5mm x 6mm SON 封装的单路、1.6mΩ、40V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD18512Q5B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的单路、1.6mΩ、40V、N 沟道 NexFET™ 功率 MOSFET 局域网 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总14页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
CSD18512Q5B 40V N 通道 NexFET™ 功率 MOSFET
1 特性
产品概要
1
•
•
•
•
•
•
•
•
低 RDS(ON)
TA = 25°C
VDS
典型值
单位
V
低热阻
漏源电压
40
75
雪崩级
Qg
栅极电荷总量 (10V)
栅漏栅极电荷
nC
nC
mΩ
mΩ
V
逻辑电平
Qgd
13.3
VGS = 4.5V
VGS = 10V
1.6
1.8
1.3
无铅端子镀层
符合 RoHS
无卤素
RDS(on) 漏源导通电阻
VGS(th) 阈值电压
SON 5mm x 6mm 塑料封装
订购信息(1)
器件
数量
2500 13 英寸卷带
250 7 英寸卷带
包装介质
封装
配送
卷带封装
2 应用
CSD18512Q5B
CSD18512Q5BT
SON 5mm × 6mm
塑料封装
•
•
•
直流/直流转换
次级侧同步整流器
电机控制
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
绝对最大额定值
3 说明
TA = 25°C
值
40
单位
V
这款 40V、1.3mΩ、5mm × 6mmNexFET™功率
MOSFET 旨在用于最大程度降低功率转换应用中的 损
耗。
VDS
VGS
漏源电压
栅源电压
±20
100
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
TC = 25°C 时测得
持续漏极电流(1)
脉冲漏极电流(2)
功耗(1)
ID
211
A
俯视图
32
400
3.1
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
IDM
PD
A
W
功耗，TC = 25°C
139
TJ、 工作结温、
–55 至 150
°C
Tstg
贮存温度
雪崩能量，单一脉冲
ID = 64A，L = 0.1mH，RG = 25Ω
D
EAS
205
mJ
D
(1) RθJA = 40°C/W，这是在厚度为 0.06 英寸的环氧板 (FR4) 印刷
电路板 (PCB) 上的 1 英寸2 2 盎司的铜焊盘上测得的典型值。
P0093-01
(2) 最大 RθJC = 0.9°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%
RDS(on) 与 VGS 对比
栅极电荷
8
7
6
5
4
3
2
1
0
10
TC = 25°C, I D = 30 A
TC = 125°C, I D = 30 A
ID = 30 A, VDS = 20 V
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
10
20
30
40
50
60
70
80
VGS - Gate-to-Source Voltage (V)
Qg - Gate Charge (nC)
D007
D004
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS624
CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
www.ti.com.cn
目录
6.1 社区资源.................................................................... 7
6.2 商标........................................................................... 7
6.3 静电放电警告............................................................. 7
6.4 术语表 ....................................................................... 7
"机械、封装和可订购信息........................................ 8
7.1 Q5B 封装尺寸............................................................ 8
7.2 建议 PCB 布局 .......................................................... 9
7.3 建议模板布局............................................................. 9
7.4 Q5B 卷带信息.......................................................... 10
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
器件和文档支持........................................................ 7
7
6
4 修订历史记录
Changes from Original (December 2016) to Revision A
Page
•
Corrected the SOA in Figure 10 ............................................................................................................................................ 5
2
版权 © 2016–2019, Texas Instruments Incorporated
CSD18512Q5B
www.ti.com.cn
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain to source voltage
VGS = 0 V, ID = 250 μA
40
V
Drain to source leakage current
Gate to source leakage current
Gate to source threshold voltage
VGS = 0 V, VDS = 32 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 30 A
VGS = 10 V, ID = 30 A
VDS = 20 V, ID = 30 A
1
100
2.2
2.3
1.6
μA
nA
V
IGSS
VGS(th)
1.3
1.6
1.8
1.3
136
mΩ
mΩ
S
RDS(on)
gfs
Drain to source on resistance
Transconductance
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
5480
537
256
1.0
37
7120
699
333
2.0
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate to drain
Gate charge gate to source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 20 V, ƒ= 1 MHz
Qg
48
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
75
98
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 20 V, ID = 30 A
VDS = 20 V, VGS = 0 V
13.3
15.1
8.2
23
Turn on delay time
Rise time
7
16
VDS = 20 V, VGS = 10 V,
IDS = 30 A, RG = 0 Ω
td(off)
tf
Turn off delay time
Fall time
31
7
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 30 A, VGS = 0 V
0.75
22
1.0
V
nC
ns
VDS= 20 V, IF = 30 A,
di/dt = 300 A/μs
17
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
Junction-to-case (top of package) thermal resistance(1)
Junction-to-ambient thermal resistance(1)(2)
0.9
50
(1)
R
θJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm ×
3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
Copyright © 2016–2019, Texas Instruments Incorporated
3
CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
www.ti.com.cn
GATE
Source
GATE
Source
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2
oz. (0.071 mm thick)
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of 2
oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
Copyright © 2016–2019, Texas Instruments Incorporated
CSD18512Q5B
www.ti.com.cn
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
200
200
180
160
140
120
100
80
180
160
140
120
100
80
60
60
40
40
VGS = 4.5 V
TC = 125°C
VGS = 6 V
VGS = 10 V
TC = 25°C
TC = -55°C
20
0
20
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
VDS - Drain-to-Source Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
VGS - Gate-to-Source Voltage (V)
D002
D0032
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
1000
100
10
9
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
10
20
30
40
50
60
70
80
0
4
8
12
16
20
24
28
32
36
40
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
D004
D005
ID = 30 A
VDS = 20 V
Figure 4. Gate Charge
Figure 5. Capacitance
2.2
2
8
7
6
5
4
3
2
1
TC = 25°C, I D = 30 A
TC = 125°C, I D = 30 A
1.8
1.6
1.4
1.2
1
0.8
0.6
0
0
-75 -50 -25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (°C)
VGS - Gate-to-Source Voltage (V)
D006
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2016–2019, Texas Instruments Incorporated
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CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
www.ti.com.cn
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
10
2
TC = 25°C
TC = 125°C
VGS = 4.5 V
VGS = 10 V
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD - Source-to-Drain Voltage (V)
1
TC - Case Temperature (°C)
D008
D009
ID = 30 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
10
1
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
TC = 25èC
TC = 125èC
0.1
0.1
1
10
100
0.01
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (ms)
D010
D011
Single pulse, Max RθJC= 0.9°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature (°C)
D012
Max RθJC= 0.9°C/W
Figure 12. Maximum Drain Current vs Temperature
6
Copyright © 2016–2019, Texas Instruments Incorporated
CSD18512Q5B
www.ti.com.cn
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
6 器件和文档支持
6.1 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2016–2019, Texas Instruments Incorporated
7
CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
www.ti.com.cn
7 "机械、封装和可订购信息
7.1 Q5B 封装尺寸
K
c1
H
L
E1
ө
d1
d2
Top View
Side View
Bottom View
ө
Front View
毫米
标称值
1.00
DIM
最小值
最大值
A
b
0.80
0.36
0.15
0.15
0.20
4.90
4.12
3.90
0.20
1.05
0.46
0.25
0.25
0.30
5.10
4.32
4.10
0.30
0.41
c
0.20
c1
c2
D1
D2
D3
d
0.20
0.25
5.00
4.22
4.00
0.25
d1
d2
E
0.085 典型值
0.369
5.00
0.319
4.90
5.90
3.48
0.419
5.10
6.10
3.68
E1
E2
e
6.00
3.58
1.27 典型值
0.46
H
0.36
0.46
0.57
0°
0.56
0.66
0.77
-
L
0.56
L1
θ
0.67
-
K
1.40 典型值
8
版权 © 2016–2019, Texas Instruments Incorporated
CSD18512Q5B
www.ti.com.cn
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
7.2 建议 PCB 布局
要获得与印刷电路板 (PCB) 设计相关的建议电路布局布线，请参阅《应用说明》SLPA005 - 通过 PCB 布局布线技
巧来减少振铃。
7.3 建议模板布局
(0.020)
(0.014)
0.508
x4
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
0.350
(0.086)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.050)
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
版权 © 2016–2019, Texas Instruments Incorporated
9
CSD18512Q5B
ZHCSFS9A –DECEMBER 2016–REVISED MARCH 2019
www.ti.com.cn
7.4 Q5B 卷带信息
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
注释：
1. 10 个链齿孔的累积容差为 ±0.2。
2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积。
3. 材料：黑色抗静电聚苯乙烯。
4. 全部尺寸为 mm（除非另外注明）。
5. 高于孔眼底部 0.3mm 的平面上测量得到 A0 和 B0 值.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD18512Q5B
CSD18512Q5BT
ACTIVE
VSON-CLIP
VSON-CLIP
DNK
8
8
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD18512
CSD18512
ACTIVE
DNK
RoHS-Exempt
& Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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The NexFET power MOSFET has been designed to minimize losses in power conversion applications.
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