CSD19502Q5BT [TI]
采用 5mm x 6mm SON 封装的单路、4.1mΩ、80V、N 沟道 NexFET™ 功率 MOSFET | DNK | 8 | -55 to 150;
| 型号： | CSD19502Q5BT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的单路、4.1mΩ、80V、N 沟道 NexFET™ 功率 MOSFET | DNK | 8 | -55 to 150 局域网 开关 脉冲 光电二极管 晶体管 功率场效应晶体管 |
| 文件： | 总13页 (文件大小：1376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD19502Q5B
www.ti.com
SLPS413 –DECEMBER 2013
80 V N-Channel NexFET™ Power MOSFET
Check for Samples: CSD19502Q5B
1
FEATURES
PRODUCT SUMMARY
2
•
•
•
•
•
•
•
•
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
TA = 25°C
VDS
TYPICAL VALUE
UNIT
V
Drain-to-Source Voltage
Gate Charge Total (10 V)
Gate Charge Gate to Drain
80
48
Qg
nC
nC
mΩ
mΩ
V
Qgd
8.6
Logic Level
VGS = 6 V
3.8
3.4
Pb-Free Terminal Plating
RoHS Compliant
RDS(on) Drain-to-Source On Resistance
VGS(th) Threshold Voltage
VGS = 10 V
2.7
Halogen Free
SON 5-mm × 6-mm Plastic Package
ORDERING INFORMATION
Device
CSD19502Q5B
Package
Media
Qty
Ship
APPLICATIONS
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
2500
•
•
Secondary Side Synchronous Rectifier
Motor Control
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
VALUE
UNIT
V
DESCRIPTION
This 3.4 mΩ, 80 V, SON 5 mm × 6 mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
VDS
VGS
Drain-to-Source Voltage
80
Gate-to-Source Voltage
±20
100
V
Continuous Drain Current (Package limited)
Continuous Drain Current (Silicon limited),
TC = 25°C
ID
138
A
Top View
Continuous Drain Current(1)
Pulsed Drain Current(2)
Power Dissipation(1)
20
200
3.2
IDM
PD
TJ,
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
Operating Junction and
–55 to 150
312
°C
TSTG Storage Temperature Range
Avalanche Energy, single pulse
EAS
mJ
ID = 79 A, L = 0.1 mH, RG = 25 Ω
D
D
(1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-
inch thick FR4 PCB.
P0093-01
(2) Pulse duration ≤300 μs, duty cycle ≤2%
RDS(on) vs VGS
GATE CHARGE
20
18
16
14
12
10
8
10
TC = 25°C,I D = 19A
TC = 125°C,I D = 19A
ID = 19A
VDS = 40V
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
35
40
45
50
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD19502Q5B
SLPS413 –DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
80
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 64 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 6 V, ID = 19 A
VGS = 10 V, ID = 19 A
VDS = 8 V, ID = 19 A
1
100
3.3
4.8
4.1
μA
nA
V
IGSS
VGS(th)
2.2
2.7
3.8
3.4
88
mΩ
mΩ
S
RDS(on)
Drain-to-Source On Resistance
gfs
Transconductance
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
3750
925
17
1.2
48
8.6
14
10
130
8
4870
1202
22
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (10 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 40 V, f = 1 MHz
2.4
Qg
62
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 40 V, ID = 19 A
VDS = 40 V, VGS = 0 V
Turn On Delay Time
Rise Time
6
VDS = 40 V, VGS = 10 V,
IDS = 19 A, RG = 0 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
22
7
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 19 A, VGS = 0 V
0.8
275
72
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 40 V, IF = 19 A,
di/dt = 300 A/μs
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case(1)
Thermal Resistance Junction to Ambient(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
0.8
50
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
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Product Folder Links: CSD19502Q5B
CSD19502Q5B
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SLPS413 –DECEMBER 2013
GATE
Source
GATE
Source
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2-
oz. (0.071-mm thick)
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2013, Texas Instruments Incorporated
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SLPS413 –DECEMBER 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
200
180
160
140
120
100
80
200
180
160
140
120
100
80
VDS = 5V
60
60
VGS = 10V
VGS = 8V
VGS = 6V
TC = 125°C
TC = 25°C
TC = −55°C
40
40
20
20
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
10
ID = 19A
VDS = 40V
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
5
10
15
20
25
30
35
40
45
50
10
20
30
40
50
60
70
80
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
20
18
16
14
12
10
8
ID = 250uA
TC = 25°C,I D = 19A
TC = 125°C,I D = 19A
6
4
2
0
−75
−25
25
75
125
175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs. Temperature
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
4
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19502Q5B
CSD19502Q5B
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SLPS413 –DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.2
2
100
10
VGS = 6V
VGS = 10V
TC = 25°C
TC = 125°C
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
ID =19A
175
−75
−25
25
75
125
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10000
100
TC = 25ºC
TC = 125ºC
10us
100us
1ms
10ms
DC
1000
100
10
1
Single Pulse Width
Max RthetaJC = 0.8ºC/W
0.1
0.1
10
0.01
1
10
100
1000
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
120
100
80
60
40
20
0
−50 −25
0
25
50
75
100 125 150 175
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2013, Texas Instruments Incorporated
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CSD19502Q5B
SLPS413 –DECEMBER 2013
www.ti.com
MECHANICAL DATA
Q5B Package Dimensions
K
c1
H
L
E1
ө
Top View
Side View
Bottom View
Front View
MILLIMETERS
NOM
1.00
DIM
MIN
0.80
0.36
0.15
0.15
0.20
4.90
4.12
0.20
4.90
5.90
3.48
MAX
A
b
1.05
0.46
0.25
0.25
0.30
5.10
4.32
0.30
5.10
6.10
3.68
0.41
c
0.20
c1
c2
D1
D2
d
0.20
0.25
5.00
4.22
0.25
E
5.00
E1
E2
e
6.00
3.58
1.27 TYP
0.460
0.56
H
0.360
0.46
0°
0.560
0.66
–
L
θ
–
K
1.40 TYP
6
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19502Q5B
CSD19502Q5B
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SLPS413 –DECEMBER 2013
Recommended PCB Pattern
(0.175)
4.440
(0.023)
0.590
(0.043)
1.100
C
L
(0.028)
0.710
(0.028)
1.270
SYM
(0.178)
4.520
C
L
0.560 (0.022)
0.710 (0.028)
(0.039)
0.984
(0.054)
1.372
(0.136)
3.456
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Pattern
(0.020)
(0.014)
0.508
x4
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
0.350
(0.086)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.050)
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
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CSD19502Q5B
SLPS413 –DECEMBER 2013
www.ti.com
Q5B Tape and Reel Information
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket
8
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD19502Q5B
ACTIVE
VSON
DNK
8
2500 Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD19502Q5B
VSON
DNK
8
2500
330.0
12.8
6.5
5.3
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON DNK
SPQ
Length (mm) Width (mm) Height (mm)
335.0 335.0 32.0
CSD19502Q5B
8
2500
Pack Materials-Page 2
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