CSD23382F4T [TI]
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150;型号: | CSD23382F4T |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150 栅 开关 晶体管 栅极 |
文件: | 总15页 (文件大小:1446K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CSD23382F4
ZHCSCO2E –MAY 2014 –REVISED JANUARY 2022
CSD23382F4 12V P 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
–12
1.04
单位
V
漏源电压
• 低导通电阻
• 超低Qg 和Qgd
• 超小封装尺寸(0402 外壳尺寸)
Qg
nC
nC
栅极电荷总量(-4.5V)
栅极电荷(栅漏极)
Qgd
0.15
VGS = -1.8V
149
90
– 1.0mm × 0.6mm
• 薄型封装
RDS(on)
VGS = -2.5V
VGS = -4.5V
mΩ
漏源导通电阻
阈值电压
66
– 最大高度为0.36mm
• 集成型ESD 保护二极管
VGS(th)
-0.8
V
– 额定值> 2kV HBM
– 额定值> 2kV CDM
• 铅端子镀层
• 无卤素
• 符合RoHS
订购信息(1)
介质
器件
数量
封装
配送
Femto (0402)
1.0mm × 0.6mm
基板栅格阵列(LGA)
CSD23382F4 3000
CSD23382F4T 250
7 英寸卷带
7 英寸卷带
卷带包装
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
2 应用
• 针对负载开关应用进行了优化
• 针对通用开关应用进行了优化
• 电池应用
绝对最大额定值
TA = 25°C
值
–12
±8
单位
V
VDS
漏源电压
• 手持式和移动类应用
VGS
ID
V
栅源电压
持续漏极电流(1)
–3.5
–22
-35
-350
500
2
3 说明
A
脉冲漏极电流,TA = 25°C(2)
持续栅极钳位电流
脉冲栅极钳位电流(2)
功率耗散(1)
IDM
A
此 66mΩ、12V P 沟道 FemtoFET™ MOSFET 经过设
计和优化,能够尽可能减小许多手持式和移动应用中的
空间占用。这项技术能够在替代标准小信号 MOSFET
的同时将封装尺寸减小至少60%。
IG
mA
PD
mW
kV
人体放电模型(HBM)
充电器件模型(CDM)
V(ESD)
.
2
kV
TJ、
Tstg
运行结温和
贮存温度范围
°C
-55 至150
0.36 mm
(1)
RθJA = 85°C/W(0.06 英寸(1.52mm) 厚FR4 PCB 上1 平方
英寸(6.45cm2) 2oz
(0.071mm) 厚的铜焊盘上的典型值)。
(2) 脉冲持续时间≤100μs,占空比≤1%
1.00 mm
0.60 mm
D
典型器件尺寸
.
.
G
S
顶视图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLPS453
CSD23382F4
ZHCSCO2E –MAY 2014 –REVISED JANUARY 2022
www.ti.com.cn
Table of Contents
6.1 Trademarks.................................................................7
6.2 Electrostatic Discharge Caution..................................7
6.3 术语表......................................................................... 7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
7.4 CSD23382F4 Embossed Carrier Tape Dimensions..10
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
6 Device and Documentation Support..............................7
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision D (October 2021) to Revision E (January 2022)
Page
• 将特性部分中的最大高度从“0.35mm”更改为“0.36mm”............................................................................ 1
• 将典型器件尺寸中的最大高度从“0.35mm”更改为“0.36mm”..................................................................... 1
• Changed maximum height from "0.35-mm" to "0.36-mm" in Mechanical Dimensions section...........................8
Changes from Revision C (October 2014) to Revision D (October 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added footnote with link to support document....................................................................................................9
Changes from Revision B (July 2014) to Revision C (October 2014)
Page
• Corrected timing VDS to read –6 V ...................................................................................................................3
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5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-Source Voltage
V
VGS = 0 V, IDS = –250 μA
VGS = 0 V, VDS = –9.6 V
VDS = 0 V, VGS = –8 V
–12
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
–1
–10
–1.1
199
μA
μA
V
IGSS
VGS(th)
VDS = VGS, IDS = 250 μA
VGS = –1.8 V, IDS = –0.1 A
VGS = –2.5 V, IDS = –0.5 A
VGS = –4.5 V, IDS = –0.5 A
VDS = –10 V, IDS = –0.5 A
–0.5
–0.8
149
90
mΩ
mΩ
mΩ
S
105
RDS(on)
Drain-to-Source On-Resistance
Transconductance
66
76
gƒs
3.4
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input Capacitance
180
118
12.8
350
1.04
0.15
0.50
0.18
1.08
28
235
154
pF
pF
pF
VGS = 0 V, VDS = –6 V,
ƒ= 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (–4.5 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at Vth
Output Charge
16.6
Ω
Qg
1.35
nC
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
nC
nC
nC
nC
ns
VDS = –6 V, IDS = –0.5 A
VDS = –6 V, VGS = 0 V
Turn On Delay Time
Rise Time
25
ns
VDS = –6 V, VGS = –4.5 V,
IDS = –0.5 A,RG = 2 Ω
td(off)
tƒ
Turn Off Delay Time
Fall Time
66
ns
41
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
V
ISD = –0.5 A, VGS = 0 V
–0.75
1.8
–1
nC
ns
VDS= –6 V, IF = –0.5 A, di/dt = 200 A/
μs
8.4
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-Ambient Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(2)
TYP
85
UNIT
RθJA
°C/W
245
(1) Device mounted on FR4 material with 1-inch2 (6.45 cm2), 2-oz. (0.071-mm thick) Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
图5-1. Transient Thermal Impedance
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
TC = 125°C
TC = 25°C
TC = −55°C
VGS = −4.5V
VGS = −2.5V
VGS = −1.8V
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
−VDS • Drain•to•Source Voltage (V)
−VGS • Gate•to•Source Voltage (V)
G001
G001
图5-2. Saturation Characteristics
VDS = –5 V
图5-3. Transfer Characteristics
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5.3 Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
4.5
4
300
270
240
210
180
150
120
90
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
3.5
3
2.5
2
1.5
1
60
0.5
0
30
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Qg • Gate Charge (nC)
1
1.1
0
2
4
6
8
10
12
−VDS • Drain•to•Source Voltage (V)
图5-5. Capacitance
G001
G001
VDS = 6 V
图5-4. Gate Charge
ID = –0.5 A
1.1
1
200
180
160
140
120
100
80
TC = 25°C, ID = −0.5A
TC = 125°C, ID = −0.5A
0.9
0.8
0.7
0.6
0.5
0.4
60
40
20
0
−75
−25
25
75
125
175
0
1
2
3
4
5
6
7
8
TC • Case Temperature (ºC)
−VGS • Gate•to• Source Voltage (V)
G001
G001
图5-7. On-State Resistance vs Gate-to-Source Voltage
ID = –250 µA
图5-6. Threshold Voltage vs Temperature
1.4
1.3
1.2
1.1
1
10
TC = 25°C
TC = 125°C
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC • Case Temperature (ºC)
−VSD − Source•to•Drain Voltage (V)
G001
G001
图5-9. Typical Diode Forward Voltage
VGS = –4.5 V
ID = –0.5 A
图5-8. Normalized On-State Resistance vs Temperature
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5.3 Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10
1
0.1
100us
1ms
10ms
100ms
DC
0.01
0.01
0.1
1
10
50
−50 −25
0
25
50
75
100 125 150 175
−VDS • Drain•to•Source Voltage (V)
TA • AmbientTemperature (ºC)
G001
G001
图5-11. Maximum Drain Current vs Temperature
Single Pulse
Typ RθJA = 245°C/W
图5-10. Maximum Safe Operating Area
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6 Device and Documentation Support
6.1 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
6.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.3 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
1.04
B
A
0.96
PIN 1 INDEX AREA
0.64
0.56
0.36 MAX
C
SEATING PLANE
0.65
0.325
0.175
2
3
0.51
0.35
0.49
1
0.16
2X
0.14
0.26
0.015
C B
A
2X
0.26
0.24
0.015
0.24
C A
B
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a PB-free solder land design.
Pin Configuration
Position
Designation
Pin 1
Gate
Pin 2
Source
Drain
Pin 3
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7.2 Recommended Minimum PCB Layout
(0.25)
2X (0.25)
PKG
0.05 MIN
ALL AROUND
2X (0.15)
1
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
(0.65)
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
PKG
2X (0.2)
(0.25)
1
SYMM
3
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
(0.65)
2X SOLDER MASK EDGE
A. All dimensions are in millimeters.
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7.4 CSD23382F4 Embossed Carrier Tape Dimensions
A. Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD23382F4
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJC
YJC
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 0
EM
EM
Samples
Samples
CSD23382F4T
NIAU
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD23382F4
CSD23382F4
CSD23382F4T
PICOSTAR YJC
PICOSTAR YJC
PICOSTAR YJC
3
3
3
3000
3000
250
178.0
180.0
180.0
8.4
8.4
8.4
0.7
0.7
0.7
1.1
1.1
1.1
0.46
0.46
0.46
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD23382F4
CSD23382F4
CSD23382F4T
PICOSTAR
PICOSTAR
PICOSTAR
YJC
YJC
YJC
3
3
3
3000
3000
250
220.0
182.0
182.0
220.0
182.0
182.0
35.0
20.0
20.0
Pack Materials-Page 2
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相关型号:
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