CSD25480F3T [TI]
采用 0.6mm x 0.7mm LGA 封装、具有栅极 ESD 保护的单路、159mΩ、-20V、P 沟道 NexFET™ 功率 MOSFET | YJM | 3 | -55 to 150;型号: | CSD25480F3T |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 0.6mm x 0.7mm LGA 封装、具有栅极 ESD 保护的单路、159mΩ、-20V、P 沟道 NexFET™ 功率 MOSFET | YJM | 3 | -55 to 150 栅 开关 晶体管 栅极 |
文件: | 总12页 (文件大小:1339K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CSD25480F3
ZHCSEW4B –APRIL 2016 –REVISED FEBRUARY 2022
CSD25480F3 -20V P 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
单位
• 低导通电阻
• 超低Qg 和Qgd
• 超小尺寸
-20
V
漏源电压
Qg
0.7
nC
nC
栅极电荷总量(-4.5V)
Qgd
0.10
栅极电荷(栅极到漏极)
– 0.73mm × 0.64mm
• 薄型封装
420
203
132
110
VGS = –1.8V
VGS = -2.5V
VGS = -4.5V
VGS = -8.0V
-0.95
漏源
导通电阻
RDS(on)
mΩ
V
– 最大厚度为0.36mm
• 集成型ESD 保护二极管
• 无铅且无卤素
• 符合RoHS
VGS(th)
阈值电压
器件信息(1)
介质
2 应用
器件
数量
封装
配送
CSD25480F3
3000
Femto
0.73mm × 0.64mm
基板栅格阵列(LGA)
• 针对负载开关应用进行了优化
• 针对通用开关应用进行了优化
• 电池应用
卷带
包装
7 英寸卷带
CSD25480F3T
250
• 手持式和移动类应用
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
3 说明
绝对最大额定值
TA = 25°C(除非另外注明)
该 -20V、110mΩ P 沟道 FemtoFET™ MOSFET 经过
设计和优化,能够最大限度地减小在许多手持式和移动
应用中占用的空间。这项技术能够在替代标准小信号
MOSFET 的同时大幅减小封装尺寸。
值
单位
V
VDS
VGS
ID
-20
-12
漏源电压
V
栅源电压
持续漏极电流(1)
脉冲漏极电流(1) (2)
功率耗散(1)
–1.7
–10.6
500
A
IDM
PD
A
mW
4000
2000
人体放电模型(HBM)
充电器件模型(CDM)
0.36 mm
V(ESD)
V
TJ、
Tstg
–55 至
150
工作结温、
贮存温度
°C
0.73 mm
0.64 mm
(1) 安装在覆铜区域最小的FR4 电路板上时的典型RθJA
255°C/W。
=
(2) 脉冲持续时间≤100μs,占空比≤1%。
典型器件尺寸...............
G
D
S
顶视图.........
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLPS578
CSD25480F3
ZHCSEW4B –APRIL 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Trademarks.................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
4 Revision History
Changes from Revision A (August 2017) to Revision B (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• 将超薄型封装图片中的厚度从0.35mm 更新为0.36mm..................................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision * (April 2016) to Revision A (August 2017)
Page
• Added the 节6.1 section in 节6 ........................................................................................................................7
• Added Recommended Minimum PCB Layout ................................................................................................... 9
• Updated the 节7.3 .............................................................................................................................................9
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
V
nA
nA
V
VGS = 0 V, IDS = –250 μA
VGS = 0 V, VDS = –16 V
–20
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
–50
–25
–1.20
840
IGSS
VDS = 0 V, VGS = –12 V
VGS(th)
VDS = VGS, IDS = –250 μA
VGS = –1.8 V, IDS = –0.1 A
VGS = –2.5 V, IDS = –0.4 A
VGS = –4.5 V, IDS = –0.4 A
VGS = –8 V, IDS = –0.4 A
VDS = –10 V, IDS = –0.4 A
–0.70
–0.95
420
203
132
110
260
RDS(on)
Drain-to-source on-resistance
mΩ
159
132
gfs
Transconductance
8.0
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
119
48
155
62
pF
pF
pF
VGS = 0 V, VDS = –10 V,
ƒ= 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (–4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
3.6
16
4.7
Ω
Qg
0.70
0.10
0.26
0.15
1.3
9
0.91
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = –10 V, IDS = –0.4 A
VDS = –10 V, VGS = 0 V
Turnon delay time
Rise time
5
ns
VDS = –10 V, VGS = –4.5 V,
IDS = –0.4 A, RG = 10 Ω
td(off)
tf
Turnoff delay time
Fall time
13
ns
7
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
V
ISD = –0.4 A, VGS = 0 V
–0.78
1.2
–1.0
nC
ns
VDS= –10 V, IF = –0.4 A, di/dt = 100 A/
μs
6.4
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
TYPICAL VALUES
UNIT
90
RθJA
°C/W
255
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz. (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
10
9
5
4.5
4
TC = 125° C
TC = 25° C
TC = -55° C
8
3.5
3
7
6
2.5
2
5
4
1.5
1
3
2
VGS = -2.5 V
VGS = -4.5 V
VGS = -8.0 V
0.5
0
1
0
0
0.5
1
1.5
2
-VGS - Gate-To-Source Voltage (V)
2.5
3
0
0.2 0.4 0.6 0.8
1
-VDS - Drain-to-Source Voltage (V)
1.2 1.4 1.6 1.8
2
D003
D002
VDS = –5 V
图5-1. Saturation Characteristics
图5-2. Transfer Characteristics
图5-3. Transient Thermal Impedance
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8
7
6
5
4
3
2
1
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10
2
0
0
0
2
4
6
8
10
12
14
-VDS - Drain-to-Source Voltage (V)
16
18
20
0.2
0.4
0.6 0.8
Qg - Gate Charge (nC)
1
1.2
1.4
D005
D004
图5-5. Capacitance
ID = –0.4 A
VDS = –10 V
图5-4. Gate Charge
1.25
1.15
1.05
0.95
0.85
0.75
0.65
0.55
400
350
300
250
200
150
100
50
TC = 25° C, ID = -0.4 A
TC = 125° C, ID = -0.4 A
0
-75 -50 -25
0
25
50
75 100 125 150 175
0
2
4
6
8
-VGS - Gate-To-Source Voltage (V)
10
12
TC - Case Temperature (èC)
D006
D007
ID = –250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
10
1.4
TC = 25èC
TC = 125èC
VGS = -2.5 V
VGS = -8.0 V
1.3
1
0.1
1.2
1.1
1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.2
0.4
0.6
-VSD - Source-To-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
75 100 125 150 175
D009
TC - Case Temperature (èC)
D008
图5-9. Typical Diode Forward Voltage
ID = –0.4 A
图5-8. Normalized On-State Resistance vs
Temperature
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100
10
1
3
2.5
2
1.5
1
0.1
0.5
100 ms
10 ms
1 ms
100 µs
10 µs
0.01
0.1
0
-50
1
10
-VDS - Drain-To-Source Voltage (V)
100
-25
0
25
50
75
100 125 150 175
D010
TA - Ambient Temperature (èC)
D011
Single pulse, max RθJA = 245°C/W
图5-11. Maximum Drain Current vs Temperature
图5-10. Maximum Safe Operating Area
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.73
B
A
0.65
PIN 1 INDEX AREA
0.64
0.56
0.36 MAX
C
SEATING PLANE
0.4
0.225
2
3
0.175
0.51
0.35
0.49
1
0.16
2X
0.14
0.16
0.14
0.015
C B
A
0.015
C A
B
0.26
2X
0.24
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a lead-free solder land design.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
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7.2 Recommended Minimum PCB Layout
(0.15)
2X (0.25)
0.05 MIN
ALL AROUND
TYP
2X (0.15)
1
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
TYP
PKG
(0.4)
METAL UNDER
SOLDER MASK
TYP
(0.175)
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
(0.15)
2X (0.2)
1
3
SYMM
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
PKG
2X SOLDER MASK EDGE
(0.175)
(0.4)
A. All dimensions are in millimeters.
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PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD25480F3
CSD25480F3T
CSD25480F3T
PICOSTAR YJM
PICOSTAR YJM
PICOSTAR YJM
3
3
3
3000
250
180.0
180.0
178.0
8.4
8.4
8.4
1.94
1.94
0.7
0.79
0.79
0.79
0.44
0.44
0.44
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD25480F3
CSD25480F3T
CSD25480F3T
PICOSTAR
PICOSTAR
PICOSTAR
YJM
YJM
YJM
3
3
3
3000
250
182.0
182.0
220.0
182.0
182.0
220.0
20.0
20.0
35.0
250
Pack Materials-Page 2
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Copyright © 2023,德州仪器 (TI) 公司
相关型号:
CSD25484F4T
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、109mΩ、-20V、P 沟道 NexFET™ 功率 MOSFET | YJJ | 3 | -55 to 150
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CSD25485F5T
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