CV245-10PAGG4中文资料_数据手册_规格书

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

512 × 18-Bit Organization Array (SN74V215)

Asynchronous or Coincident Read and

Write Clocks

1024 × 18-Bit Organization Array

(SN74V225)

Asynchronous or Synchronous

Programmable Almost-Empty and

Almost-Full Flags With Default Settings

2048 × 18-Bit Organization Array

(SN74V235)

Half-Full Flag Capability

4096 × 18-Bit Organization Array

(SN74V245)

Output Enable Puts Output Data Bus in

High-Impedance State

7.5-ns Read/Write Cycle Time

High-Performance Submicron CMOS

Technology

3.3-V V , 5-V Input Tolerant

CC

First-Word or Standard Fall-Through

Timing

Packaged in 64-Pin Thin Quad Flat Package

DSP and Microprocessor Interface Control

Logic

Single or Double Register-Buffered Empty

and Full Flags

Provide a DSP Glueless Interface to Texas

Instruments TMS320 DSPs

Easily Expandable in Depth and Width

description

TheSN74V215, SN74V225, SN74V235, andSN74V245areveryhigh-speed, low-powerCMOSclockedfirst-in

first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast

as 5 ns. These DSP-Sync FIFO memories feature read and write controls for use in applications such as

DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data

communications.

These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers

through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals.

The continuous clocks for each port are independent of one another and can be asynchronous or coincident.

The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or

buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output.

The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR),

and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the

programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A

half-full flag (HF) is available when the FIFO is used in a single-device configuration.

Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and

standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three

transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.

In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a

specific read operation is performed. A read operation, which consists of activating REN and enabling a rising

RCLK edge, shifts the word from internal memory to the data output lines.

These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are

used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and

set to high for all other devices in the daisy chain.

The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DSP-SYNC and TMS320 are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

PAG PACKAGE

(TOP VIEW)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Q14

Q13

GND

Q12

Q11

V

CC

Q10

Q9

9

GND

Q8

Q7

Q6

Q5

10

11

12

13

14

15

16

D4

D3

D2

D1

GND

Q4

D0

V

CC

2

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

functional block diagram

D0–D17

LD

59

19

Offset

Register

WCLK

Input

Register

20

WEN

Write-Control

Logic

25

23

54

17

26

FF/IR

PAF

EF/OR

PAE

HF/(WXO)

Flag

Logic

RAM ARRAY

Write

512 × 18, 1024 × 18,

2048 × 18, 4096 × 18

Pointer

Read

18

FL

Pointer

21

WXI

Expansion

26

(HF)/WXO

Logic

24

RXI

Read-Control

Logic

27

RXO

Reset

Logic

57

Output

Register

RS

58

OE

61

60

REN

RCLK

Q0–Q17

3

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1–16, 63,

D0–D17

I

Data inputs. Data inputs for an 18-bit bus.

64

Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected. EF indicates

whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether

there is valid data available at the outputs.

EF/OR

FF/IR

54

25

O

Memory-full/space-availableflag. In the standard mode, the FF function is selected. FF indicates whether

theFIFOmemoryisfull. IntheFWFTmode, theIR function is selected. IRindicateswhetherthereisspace

available for writing to the FIFO memory.

Mode selection. In the single-device or width-expansion configuration, FL, together with WXI and RXI,

determines if the mode is standard mode or first-word fall-through (FWFT) mode, as well as whether the

PAE/PAF flags are synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion

configuration, FL is grounded on the first device (first-load device) and set to high for all other devices in

the daisy chain.

FL

18

I

30, 35, 40,

46, 51, 55,

62

GND

Ground

Read/write control. When LD is low, data on the inputs D0–D11 is written to the offset and depth registers

on the low-to-high transition of the WCLK, when WEN is low. When LD is low, data on the outputs Q0–Q11

is read from the offset and depth registers on the low-to-high transition of RCLK when REN is low.

LD

59

58

17

I

Output enable. When OE is low, the data output bus is active. If OE is high, the output data bus is in the

high-impedance state.

OE

PAE

Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the offset

programmedintotheFIFO. Thedefaultoffsetatresetis63fromemptyforSN74V215, and127fromempty

for SN74V225, SN74V235, and SN74V245.

O

Programable almost-full flag. When PAF is low, the FIFO is almost full, based on the offset programmed

into the FIFO. The default offset at reset is 63 from full for SN74V215, and 127 from full for SN74V225,

SN74V235, and SN74V245.

PAF

23

O

28, 29, 31,

32, 34,

36–39, 41,

42, 44, 45,

47, 48, 50,

52, 53

Q0–Q17

Data outputs. Data outputs for an 18-bit bus.

Read clock. When REN is low, data is read from the FIFO on a low-to-high transition of RCLK, if the FIFO

is not empty.

RCLK

REN

RS

61

60

57

I

Readenable. When REN is low, data is read from the FIFO on every low-to-high transition of RCLK. When

REN is high, the output register holds the previous data. Data is not read from the FIFO if EF is low.

Reset. When RS is set low, internal read and write pointers are set to the first location of the RAM array,

FF and PAF go high, and PAE and EF go low. A reset is required before an initial write after power up.

Read expansion. In the single-device or width-expansion configuration, RXI, together with FL and WXI,

determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are

synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, RXI is

connected to RXO (read expansion out) of the previous device.

RXI

24

27

I

Last-location-read flag. In the depth-expansion configuration, a pulse is sent from RXO to RXI of the next

device when the last location in the FIFO is read.

RXO

O

22, 33, 43,

49, 56

V

CC

Supply voltage. +3.3-V power-supply pins.

Write clock. When WEN is low, data is written into the FIFO on a low-to-high transition of WCLK if the FIFO

is not full.

WCLK

19

I

4

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

Write enable. When WEN is low, data is written into the FIFO on every low-to-high transition of WCLK.

When WEN is high, the FIFO holds the previous data. Data is not written into the FIFO if FF is low.

WEN

20

I

Width expansion. In the single-device or width-expansion configuration, WXI, together with FL and RXI,

determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are

synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, WXI is

connected to WXO (write expansion out) of the previous device.

WXI

21

I

Half-full flag. In the single-device or width-expansion configuration, the device is more than half full when

HF is low. In the depth-expansion configuration, a pulse is sent from WXO to WXI of the next device when

the last location in the FIFO is written.

WXO/HF

26

O

detailed description

INPUTS:

DATA IN (D0–D17)

Data inputs for 18-bit-wide data.

CONTROLS:

RESET (RS)

Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the

first location. A reset is required after power up before a write operation can take place. The half-full flag (HF)

and programmable almost-full flag (PAF) is reset to high after t . The programmable almost-empty flag (PAE)

RSF

is reset to low after t

. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode,

RSF

but resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset

registers are initialized to their default values.

WRITE CLOCK (WCLK)

A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with

respect to the low-to-high transition of WCLK.

The write and read clocks can be asynchronous or coincident.

WRITE ENABLE (WEN)

When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the

device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.

When WEN is high, no new data is written in the RAM array on each WCLK cycle.

Topreventdataoverflowinthestandardmode, FFgoeslow, inhibitingfurtherwriteoperations. Uponcompletion

of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK.

To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion

of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated on the rising edge of WCLK.

WEN is ignored when the FIFO is full in either FWFT or standard mode.

READ CLOCK (RCLK)

Data can be read on the outputs on the low-to-high transition of RCLK when OE is low.

The write and read clocks can be asynchronous or coincident.

5

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

detailed description (continued)

READ ENABLE (REN)

When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK

cycle if the device is not empty.

When REN is high, the output register holds the previous data and no new data is loaded into the output register.

Data outputs Q0–Qn maintain the previous data value.

In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be

requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting

further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high,

allowing a read to occur. The EF flag is updated on the rising edge of RCLK.

In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third

valid low-to-high transition of RCLK + t

after the first write. REN need not be asserted low. To access all

SKEW

other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been

read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read

operations. REN is ignored when the FIFO is empty.

OUTPUT ENABLE (OE)

When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output

data bus is in the high-impedance state.

LOAD (LD)

The SN74V215, SN74V225, SN74V235, and SN74V245 devices contain two 12-bit offset registers with data

on the inputs, or read on the outputs. When LD is low and WEN is low, data on the inputs D0–D11 is written into

the empty offset register on the first low-to-high transition of the write clock (WCLK). When LD and WEN are

held low, data is written into the full offset register on the second low-to-high transition of WCLK (see Tables 1

and 2). The third transition of WCLK again writes to the empty-offset register.

However, writing to all offset registers need not occur at one time. One or two offset registers can be written and

then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low,

the next offset register in sequence is written.

Table 1. Writing to Offset Registers

†

LD

WEN WCLK

SELECTION

Writing to offset registers:

Empty offset

L

↑

Full offset

L

H

L

↑

No operation

Write into FIFO

No operation

H

†

Thesame selection sequence applies to reading from the

registers. REN is enabled and read is performed on the

low-to-high transition of RCLK.

6

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DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

detailed description (continued)

†

Table 2. Offset Register Location and Default Values

17

12 11

0

Empty Offset Register

Default Value

003FH (74V215):

007FH (74V225/74V235/74V245)

Not used

17

12 11

Full Offset Register

Default Value

003FH (74V215):

Not used

007FH (74V225/74V235/74V245)

†

Any bits of the offset register not being programmed should be set to zero.

When LD is low and WEN is high, the WCLK input is disabled; then, a signal at this input can neither increment

the write-offset-register pointer, nor execute a write.

The contents of the offset registers can be read on the output lines when LD is low and REN is low; then, data

can be read on the low-to-high transition of RCLK. Reading the control registers employs a dedicated

read-offset-register pointer. (The read and write pointers operate independently.) Offset register content can be

read out in the standard mode only. It is inhibited in the FWFT mode.

A read from and a write to the offset registers should not be performed simultaneously.

FIRST LOAD (FL)

For the single-device mode, see Table 5 for additional information. In the daisy-chain depth-expansion

configuration, FL is grounded to indicate it is the first device loaded and is set high for all other devices in the

daisy chain (see Operating Configurations for further details).

WRITE EXPANSION INPUT (WXI)

This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. WXI is connected

to write expansion out (WXO) of the previous device in the daisy-chain depth-expansion mode.

READ EXPANSION INPUT (RXI)

This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. RXI is connected to

read expansion out (RXO) of the previous device in the daisy-chain depth-expansion mode.

OUTPUTS:

FULL FLAG/INPUT READY (FF/IR)

This is a dual-purpose pin. In FWFT mode, the input ready (IR) function is selected. IR goes low when memory

space is available for writing data. When there is no free space left, IR goes high, inhibiting further write

operations.

In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write

operations. When FF is high, the FIFO is not full. If no reads are performed after a reset, FF goes low after

D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096

for the SN74V245.

IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the

SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due to the capacity of the

memory plus output register.

FF/IR is synchronous and updated on the rising edge of WCLK.

7

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DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

detailed description (continued)

EMPTY FLAG/OUTPUT READY (EF/OR)

This is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time the first

word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition

that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with

REN low). The previous data stays at the outputs, indicating that the last word was read. Further data reads

are inhibited until OR goes low again.

In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read

operations. When EF is high, the FIFO is not empty.

EF/OR is synchronous and updated on the rising edge of RCLK.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if no reads are performed, PAF

goes low after 513 – m for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the

SN74V245. Default values for m are in Table 3 and Table 4.

In standard mode, if no reads are performed after reset (RS), PAF goes low after (512 – m) writes for the

SN74V215, (1024 – m) writes for the SN74V225, (2048 – m) writes for the SN74V235, and (4096 – m) writes

for the SN74V245. The offset m is defined in the full offset register.

If asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK. PAF

is reset to high on the low-to-high transition of RCLK. IfsynchronousPAFconfigurationisselected(seeTable 5),

PAF is updated on the rising edge of WCLK.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there

are n + 1 words, or fewer, in the FIFO. In standard mode, PAE goes low when there are n words or fewer in the

FIFO. The offset n is defined as the empty offset. The default values for n are noted in Table 3 and Table 4.

If there is no empty offset specified, PAE is low when the device is 63 away from completely empty for

SN74V215, and 127 away from completely empty for SN74V225, SN74V235, and SN74V245.

IfasynchronousPAEconfigurationisselected, PAEisassertedlowonthelow-to-hightransitionofthereadclock

(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE

configuration is selected (see Table 5), PAE is updated on the rising edge of RCLK.

WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)

This is a dual-purpose output. In the single-device and width-expansion mode, when write expansion in (WXI)

and/or read expansion in (RXI) are grounded, this output acts as an indication of a half-full memory.

After one-half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag

(HF) goes low and remains set until the difference between the write pointer and read pointer is less than or

equal to one-half of the total memory of the device. HF is then reset to high by the low-to-high transition of the

read clock (RCLK). HF is asynchronous.

In the daisy-chain depth-expansion mode, WXI is connected to WXO of the previous device. This output acts

as a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last

location of memory.

READ EXPANSION OUT (RXO)

In the daisy-chain depth-expansion configuration, read expansion in (RXI) is connected to read expansion out

(RXO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a

pulse when the previous device reads from the last location of memory.

8

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

detailed description (continued)

DATA OUTPUTS (Q0–Q17)

Q0–Q17 are data outputs for 18-bit-wide data.

functional description

TIMING MODES:

STANDARD vs FIRST-WORD FALL-THROUGH (FWFT) MODE

The SN74V215, SN74V225, SN74V235, and SN74V245 support two different timing modes. The selection of

the mode of operation is determined during configuration at reset (RS). During an RS operation, the first load

(FL), read expansion input ( RXI), and write-expansion input (WXI) pins are used to select the timing mode as

shown in the truth table (see Table 5). In standard mode, the first word written to an empty FIFO does not appear

on the data output lines unless a specific read operation is performed. A read operation, which consists of

activating read enable (REN) and enabling a rising read clock (RCLK) edge, shifts the word from internal

memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to

the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted to access

the first word.

Various signals, both input and output signals, operate differently, depending on which timing mode is in effect.

FIRST-WORD FALL-THROUGH MODE (FWFT)

In this mode, status flags IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 3. To write data

into the FIFO, WEN must be low. Data presented to the data-in lines is clocked into the FIFO on subsequent

transitions of WCLK. After the first write is performed, the output ready (OR) flag goes low. Subsequent writes

continue to fill the FIFO. PAE goes high after n + 2 words have been loaded into the FIFO, where n is the empty

offset value. The default setting for this value is stated in the footnote of Table 3. This parameter also is user

programmable. See the Programmable Flag Offset Loading section.

If data continues to be written into the FIFO, and no read operations are taking place, HF switches to low when

the 258th (SN74V215), 514th (SN74V225), 1026th (SN74V235), and 2050th (SN74V245) word, respectively,

is written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. Again, if no reads are

performed, PAF goes low after (513 – m) writes for the SN74V215, (1025 – m) writes for the SN74V225,

(2049 – m) writes for the SN74V235, and (4097 – m) writes for the SN74V245, where m is the full offset value.

The default setting for this value is stated in the footnote of Table 3.

When the FIFO is full, the input ready (IR) flag goes high, inhibiting further write operations. If no reads are

performed after a reset, IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the

SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due

to the capacity of the memory plus output register.

If the FIFO is full, the first read operation causes the IR flag to go low. Subsequent read operations cause PAF

and HF to go high at the conditions described in Table 3. If further read operations occur without write

operations, PAE goes low when there are n + 1 words in the FIFO, where n is the empty offset value. If there

is no empty offset specified, PAE is low when the device is 64 away from empty for SN74V215, and 128 away

from empty for SN74V225, SN74V235, and SN74V245. Continuing read operations cause the FIFO to be

empty. When the last word has been read from the FIFO, OR goes high, inhibiting further read operations. REN

is ignored when the FIFO is empty.

9

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

functional description (continued)

Table 3. Status Flags for FWFT Mode

NUMBER OF WORDS IN FIFO

IR

PAF

HF

PAE

OR

SN74V215

SN74V225

SN74V235

SN74V245

0

L

H

L

H

L

H

L

†

1 to (n+1)

(n+2) to 257

258 to [513–(m+1)]

(513–m) to 512

513

(n+2) to 513

514 to [1025–(m+1)]

(1025–m) to 1024

1025

(n+2) to 1025

1026 to [2049–(m+1)]

(2049–m) to 2048

2049

(n+2) to 2049

2050 to [4097–(m+1)]

(4097–m) to 4096

4097

H

‡

L

†

‡

n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)

m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)

STANDARD MODE

In this mode, status flags FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 4. To write data into

the FIFO, write enable (WEN) must be low. Data presented to the data-in lines is clocked into the FIFO on

subsequent transitions of the write clock (WCLK). After the first write is performed, the empty flag (EF) goes

high. Subsequent writes continue to fill the FIFO. The programmable almost-empty flag (PAE) goes high after

n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value

is stated in the footnote of Table 4. This parameter also is user programmable. See the Programmable Flag

Offset Loading section.

If data continues to be written into the FIFO, and no read operations are taking place, the half-full flag (HF)

switchesto low when the 257th (SN74V215), 513th (SN74V225), 1025th (SN74V235), and 2049th (SN74V245)

word, is written into the FIFO. Continuing to write data into the FIFO causes the programmable almost-full flag

(PAF) to go low. Again, if no reads are performed, PAF goes low after (512 – m) writes for the SN74V215, (1024

– m) writes for the SN74V225, (2048 – m) writes for the SN74V235 and (4096 – m) writes for the SN74V245.

Offset m is the full offset value. This parameter also is user programmable. See the Programmable Flag Offset

Loading section. If there is no full offset specified, PAF is low when the device is 63 away from full for SN74V215,

and 127 away from full for the SN74V225, SN74V235, and SN74V245.

When the FIFO is full, the full flag (FF) goes low, inhibiting further write operations. If no reads are performed

after a reset, FF goes low after D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048

for the SN74V235, and 4096 for the SN74V245.

If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and

the half-full flag (HF) to go high under the conditions described in Table 4. If further read operations occur,

without write operations, the programmable almost-empty flag (PAE) goes low when there are n words in the

FIFO, where n is the empty offset value. If there is no empty offset specified, PAE is low when the device is 63

away from completely empty for SN74V215, and 127 away from completely empty for SN74V225, SN74V235,

and SN74V245. Continuing read operations cause the FIFO to be empty. When the last word has been read

from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

functional description (continued)

Table 4. Status Flags for Standard Mode

NUMBER OF WORDS IN FIFO

SN74V225 SN74V235

FF

PAF

HF

PAE

EF

SN74V215

SN74V245

0

H

L

H

L

H

L

†

1 to n

H

(n+1) to 256

257 to [512–(m+1)]

(512–m) to 511

512

(n+1) to 512

513 to [1025–(m+1)]

(1024–m) to 1023

1024

(n+1) to 1024

1025 to [2048–(m+1)]

(2048–m) to 2047

2048

(n+1) to 2048

2049 to [4096–(m+1)]

(4096–m) to 4095

4096

H

‡

L

†

‡

n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)

m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)

PROGRAMMABLE FLAG LOADING

Full- and empty-flag offset values can be user programmable. The SN74V215, SN74V225, SN74V235, and

SN74V245 have internal registers for these offsets. Default settings are stated in the footnotes of Table 3 and

Table 4. Offset values are loaded into the FIFO using the data input lines D0–D11. To load the offset registers,

the load (LD) pin and WEN pin must be held low. Data present on D0–D11 is transferred to the empty offset

register on the first low-to-high transition of WCLK. By continuing to hold the LD and WEN pins low, data present

on D0–D11 is transferred into the full offset register on the next transition of the WCLK. The third transition again

writes to the empty offset register. Writing to all offset registers does not have to occur at the same time. One

or two offset registers can be written and, then, by bringing the LD pin high, the FIFO is returned to normal

read/write operation. When the LD pin and WEN again are set low, the next offset register in sequence is written.

The contents of the offset registers can be read on the data output lines Q0–Q11 when the LD pin is set low,

andRENissetlow. Datathencanbereadonthenextlow-to-hightransitionofRCLK. ThefirsttransitionofRCLK

presents the empty offset value to the data output lines. The next transition of RCLK presents the full offset

value. Offset register content can be read in the standard mode only. It cannot be read in the FWFT mode.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION

The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset

cycle (see Table 5) with either asynchronous or synchronous timing for PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected (see Table 5), the PAE is asserted low on the low-to-high

transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, the PAF is asserted

low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. For

detailed timing diagrams, see Figure 9 for asynchronous PAE timing and Figure 10 for asynchronous PAF

timing.

If synchronous PAE/PAF configuration is selected, PAE is asserted and updated on the rising edge of RCLK

only, but not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, but not RCLK.

For detailed timing diagrams, see Figure 18 for synchronous PAE timing and Figure 19 for synchronous PAF

timing.

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

functional description (continued)

Table 5. Truth Table for Configuration at Reset

FL

RXI

WXI

EF/OR

FF/IR

PAE, PAF

FIFO TIMING MODE

Single register-buffered

empty flag

Single register-buffered

full flag

0

Asynchronous

Standard

Triple register-buffered

output-ready flag

Double register-buffered

input ready flag

0

1

0

1

0

1

0

1

0

1

Asynchronous

Synchronous

Asynchronous

FWFT

Double register-buffered Double register-buffered

Standard

FWFT

empty flag

full flag

Single register-buffered

empty flag

Single register-buffered

full flag

†

0

Single register-buffered

empty flag

Single register-buffered

full flag

1

Triple register-buffered

output-ready flag

Double register-buffered

input ready flag

1

Double register-buffered Double register-buffered

Standard

empty flag

full flag

Single register-buffered

empty flag

Single register-buffered

full flag

‡

1

†

‡

In daisy-chain depth expansion, FL is held low for the first-load device. The RXI and WXI inputs are driven by the

corresponding RXO and WXO outputs of the preceding device.

In daisy-chain depth expansion, FL is held high for members of the expansion other than the first-load device. The RXI and

WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.

REGISTER-BUFFERED FLAG OUTPUT SELECTION

The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset

cycle (see Table 7) with single, double, or triple register-buffered flag output signals. The various combinations

available are described in Table 6 and Table 7. In general, going from single to double or triple register-buffered

flag outputs removes the possibility of metastable flag indications on boundary states (empty or full conditions).

The tradeoff is the addition of clock-cycle delays for the respective flag to be asserted. Not all combinations of

register-buffered flag outputs are supported. Register-buffered outputs apply to the empty flag and full flag only.

Partial flags are not affected. Table 6 and Table 7 summarize the options available.

Table 6. Register-Buffered Flag Output Options, FWFT Mode

PROGRAMMING

FLAG TIMING

DIAGRAMS

OUTPUT READY INPUT READY

PARTIAL

FLAGS

AT RESET

(OR)

(IR)

FL

0

RXI

0

WXI

1

Triple

Double

Asynchronous

Synchronous

Figure 23

1

0

1

Figure 16, Figure 17

Table 7. Register-Buffered Flag Output Options, Standard Mode

PROGRAMMING AT

EMPTY FLAG

(EF)

FULL FLAG

(FF)

PARTIAL

FLAGS

FLAG TIMING

DIAGRAMS

RESET

BUFFERED OUTPUT BUFFERED OUTPUT TIMING MODE

FL

0

RXI

0

WXI

0

Single

Double

Single

Double

Asynchronous

Synchronous

Asynchronous

Synchronous

Figure 5, Figure 6

Figure 20, Figure 22

1

0

1

0

1

0

12

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

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t

RS

t

RSR

REN, WEN, LD

t

RSS

FL, RXI, WXI

(see Note A)

Configuration Setting

(see Note C)

RCLK, WCLK

(see Note B)

t

RSF

Standard Mode

FWFT Mode

FF/IR

RSF

FWFT Mode

EF/OR

Standard Mode

t

RSF

PAF,

WXO/HF, RXO

t

PAE

t

OE = 1

(see Note D)

Q0–Q17

OE = 0

NOTES: A. Single-device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to V

or GND).

CC

B. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.

C. In FWFT mode, IR goes low based on the WCLK edge after reset.

D. After reset, the outputs are low if OE = 0 and 3-state if OE = 1.

Figure 1. Reset Timing

13

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLK

t

CLKL

CLKH

WCLK

t

DH

DS

Data

Invalid

D0–D17

t

ENS

ENH

WEN

No Operation

t

WFF

FF

t

(see Note A)

SKEW1

RCLK

REN

NOTES: A.

t

is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current

SKEW1

clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t

state until the next WCLK edge.

, FF might not change

SKEW1

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 2. Write-Cycle Timing With Single Register-Buffered FF (Standard Mode)

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLK

t

CLKL

CLKH

RCLK

t

ENH

ENS

No Operation

REN

EF

t

REF

t

A

Q0–D17

OE

t

OLZ

t

OHZ

t

OE

t

SKEW1

(see Note A)

WCLK

WEN

NOTES: A.

t

is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high during the current

SKEW1

clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than t

state until the next RCLK edge.

, EF might not change

SKEW1

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 3. Read-Cycle Timing With Single Register-Buffered EF (Standard Mode)

15

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

WCLK

t

DS

D0–D17

D1

D2

D3

D4

D0 (First Valid Write)

t

ENS

WEN

t

FRL

(see Note A)

t

SKEW1

RCLK

EF

t

REF

t

ENS

REN

t

A

D0

D1

Q0–Q17

t

OLZ

t

OE

NOTES: A. When t

is at the minimum specification, t

(maximum) = t

+ t

. When t

SKEW1

is less than the

SKEW1

FRL

CLK

+ t

minimum specification, t

FRL

empty boundary (EF is low).

B. The first word always is available the cycle after EF goes high.

(maximum) = either (2 × t

) + t

or t

. The latency timing applies only at the

CLK SKEW1

SKEW1

C. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 4. First-Data-Word Latency with Single Register-Buffered EF (Standard Mode)

16

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

No Write

WCLK

D0–D17

FF

t

SKEW1

(see Note A)

SKEW1

t

DS

(see Note A)

Data

Write

Data Write

t

WFF

WEN

RCLK

t

ENS

t

ENH

REN

OE

Low

t

A

Data In Output Register

Data Read

Next Data Read

Q0–Q17

NOTES: A.

t

is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current

SKEW1

clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t

state until the next WCLK edge.

, FF might not change

SKEW1

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 5. Single Register-Buffered Full-Flag Timing (Standard Mode)

17

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DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

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WCLK

t

DS

D0–D17

Data Write 1

Data Write 2

t

ENS

t

ENS

t

ENH

WEN

t

FRL

(see Note A)

FRL

(see Note A)

t

SKEW1

RCLK

EF

t

REF

REN

OE

Low

t

A

Data In Output Register

Data Read

Q0–Q17

NOTES: A. When t

is at the minimum specification, t

(maximum) = t

or t

SKEW1

+ t

CLK SKEW1

. When t

is less than the minimum

SKEW1

specification, t

FRL

) + t

CLK SKEW1

(maximum) = either (2 × t

+ t . The latency timing applies only at the empty

FRL

boundary (EF is low).

CLK

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 6. Single Register-Buffered Empty Flag Timing (Standard Mode)

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

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t

CLK

t

CLKL

CLKH

WCLK

t

ENH

ENS

LD

WEN

t

DH

DS

PAE Offset

D0–D15

D0–D11

PAE Offset

PAF Offset

Figure 7. Write Programmable Registers (Standard and FWFT Modes)

t

CLK

t

CLKL

CLKH

RCLK

t

ENH

ENS

LD

REN

t

A

Q0–Q15

Unknown

PAE Offset

PAF Offset

PAE Offset

Figure 8. Read Programmable Registers (Standard Mode)

19

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLKL

CLKH

WCLK

t

ENH

ENS

WEN

PAE

n Words in FIFO

(see Note B)

n + 1 Words in FIFO

(see Note C)

n Words in FIFO

(see Note B)

n + 1 Words in FIFO

(see Note C)

t

PAEA

n + 1 Words in FIFO

(see Note B)

n + 2 Words in FIFO

(see Note C)

t

PAEA

RCLK

REN

t

ENS

NOTES: A. n = PAE offset

B. For standard mode

C. For FWFT mode

D. PAE is asserted low on RCLK transition and reset to high on WCLK transition.

E. Select the asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.

Figure 9. Asynchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)

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t

CLKL

CLKH

WCLK

t

ENH

ENS

WEN

PAF

t

PAFA

D – m Words

D – (m + 1) Words

D – (m + 1) Words in FIFO

in FIFO

(see Notes A and B)

t

PAFA

RCLK

t

ENS

REN

NOTES: A. m = PAF offset

B. D = maximum FIFO depth

In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245

In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245

C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.

D. Select asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.

Figure 10. Asynchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)

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t

CLKL

CLKH

WCLK

t

ENH

ENS

WEN

HF

D/2+1 Words in FIFO,

(see Notes A and B)

t

HF

Words in FIFO

(see Notes A

and C)

D – 1

+ 2

D/2 Words in FIFO,

(see Notes A and B)

D/2 Words in FIFO,

(see Notes A and B)

2

Words in FIFO

(see Notes A

and C)

Words in FIFO

(see Notes A and C)

D – 1

2

D – 1

2

+ 1

t

HF

RCLK

REN

t

ENS

NOTES: A. D = maximum FIFO depth

In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245

In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245

B. For standard mode

C. For FWFT mode

D. Select single-device mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset.

Figure 11. Half-Full-Flag Timing (Standard and FWFT Modes)

t

CLKH

See

WCLK

Note A

t

XO

WXO

WEN

t

ENS

NOTE A: Write to last physical location.

Figure 12. Write-Expansion-Out Timing

22

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t

CLKH

RCLK

See

Note A

t

XO

RXO

REN

t

ENS

NOTE A: Read from last physical location.

Figure 13. Read-Expansion-Out Timing

t

XI

WXI

t

XIS

WCLK

Figure 14. Write-Expansion-In Timing

t

XI

RXI

t

XIS

RCLK

Figure 15. Read-Expansion-In Timing

23

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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLKH

CLKL

WCLK

t

ENS

ENH

WEN

PAE

n Words in FIFO,

(see Note B)

n + 1 Words in FIFO

(see Note C)

n Words in FIFO

(see Note B),

n + 1 Words in FIFO

(see Note C)

n + 1 Words in FIFO,

(see Note B)

n + 2 Words in FIFO

(see Note C)

t

PAES

t

PAES

(see Note C)

SKEW2

(see Note D)

RCLK

REN

t

ENS

ENH

NOTES: A. n = PAE offset

B. For standard mode

C. For FWFT mode

D.

t

istheminimumtimebetweenarisingWCLKedgeandarisingRCLKedgeforPAEtogohighduringthecurrentclockcycle.

SKEW2

IfthetimebetweentherisingedgeofWCLKandtherisingedgeofRCLKislessthant

one extra RCLK cycle.

,thePAEdeassertionmightbedelayed

SKEW2

E. PAE is asserted and updated on the rising edge of RCLK only.

F. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.

Figure 18. Synchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)

26

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLKH

CLKL

WCLK

t

ENS

ENH

WEN

PAF

t

PAFS

D – (m + 1) Words

in FIFO

D – m Words in FIFO

D – (m + 1) Words in FIFO

t

SKEW2

(see Note C)

PAFS

RCLK

REN

t

ENS

ENH

NOTES: A. m = PAF offset

B. D = maximum FIFO depth

In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245.

In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096 for the SN74V245.

C.

t

istheminimumtimebetweenarisingRCLKedgeandarisingWCLKedgeforPAFtogohighduringthecurrentclockcycle.

SKEW2

If the time between the rising edge of RCLK and the rising edge of WCLK is less than t

be delayed an extra WCLK cycle.

, the PAF deassertion time might

SKEW2

D. PAF is asserted and updated on the rising edge of WCLK only.

E. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.

Figure 19. Synchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)

27

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SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

No

Write

WCLK

1

2

1

2

t

SKEW1

(see Note A)

SKEW1

(see Note A)

t

DS

D0–D17

Wd

Data Write

t

WFF

t

WFF

t

WFF

FF

WEN

RCLK

t

ENS

t

ENH

REN

OE

Low

t

A

Data in Output Register

Data Read

Next Data Read

Q0–Q17

NOTES: A.

t

is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK

SKEW1

cycle plus t

. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t

WFF

, the FFdeassertion

SKEW1

time might be delayed an extra WCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

Figure 20. Double Register-Buffered Full-Flag Timing (Standard Mode)

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLK

t

CLKH

t

CLKL

WCLK

1

2

t

DS

t

DH

Data in

Valid

D0–D17

t

ENS

t

ENH

WEN

FF

No Operation

t

WFF

t

SKEW1

(see Note A)

RCLK

REN

NOTES: A.

t

is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK

SKEW1

cycle plus t

. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t

RFF

, the FF deassertion

SKEW1

might be delayed an extra WCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

Figure 21. Write-Cycle Timing With Double Register-Buffered FF (Standard Mode)

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

t

CLK

t

CLKH

t

CLKL

RCLK

1

2

t

ENS

t

ENH

No Operation

REN

t

REF

EF

t

A

Q0–Q17

Last Word

t

OLZ

t

OHZ

t

OE

t

SKEW1

(see Note A)

WCLK

t

ENS

t

ENH

WEN

t

DS

t

DH

D0–D17

First Word

NOTES: A.

t

SKEW1

is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high after one RCLK

cycle plus t

. If the time between the rising edge of WCLK and the rising edge of RCLK is less than t , the EFdeassertion

REF SKEW1

might be delayed an extra RCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

Figure 22. Read-Cycle Timing With Double Register-Buffered EF (Standard Timing)

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

WCLK

t

ENS

t

ENH

WEN

t

DS

t

DS

t

DH

D0–D17

W1

W2

W3

W4

W[n+2]

W[n+3]

t

SKEW1

(see Note A)

RCLK

REN

1

2

3

t

A

Data In Output Register

W1

Q0–Q17

t

REF

t

REF

OR

NOTES: A.

t

is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go high during the current cycle. If

SKEW1

the time between the rising edge of WLCK and the rising edge of RCLK is less than t

one extra RCLK cycle.

, the OR deassertion might bedelayed

SKEW1

B. LD is high, OE is low.

C. Select FWFT mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during reset.

Figure 23. OR-Flag Timing and First Word Fall Through When FIFO is Empty (FWFT mode)

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

operating configurations

SINGLE-DEVICE CONFIGURATION

A single SN74V215, SN74V225, SN74V235, or SN74V245 can be used when the application requirements are

for 512/1024/2048/4096 words or fewer, respectively. These FIFOs are in a single-device configuration when

the first load (FL), write expansion in (WXI) and read expansion in (RXI) control inputs are configured as

(FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (see Figure 24).

Reset (RS)

Read Clock (RCLK)

Read Enable (REN)

Output Enable (OE)

Write Clock (WCLK)

Write Enable (WEN)

Load (LD)

74V215

74V225

74V235

74V245

Data In (D0–D17)

Data Out (Q0–Q17)

Empty Flag/Output Ready (EF/OR)

Programmable (PAF)

Full Flag/Input Ready (FF/IR)

Programmable (PAE)

Half-Full Flag (HF)

FL

RXI

WXI

Figure 24. Block Diagram of Single 512 × 18, 1024 × 18, 2048 × 18, or 4096 × 18 Synchronous FIFO

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

operating configurations (continued)

WIDTH-EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control signals of multiple devices. Status flags

can be detected from any one device. The exceptions are the empty flag/output ready and full flag/input ready.

Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary

by one cycle between FIFOs. To avoid problems, the user must create composite flags by gating the empty

flags/output ready of every FIFO, and separately gating all full flags/input ready. Figure 25 demonstrates a

36-word width by using two SN74V215, SN74V225, SN74V235, or SN74V245 memories. Any word width can

be attained by adding additional SN74V215, SN74V225, SN74V235, or SN74V245 memories. These FIFOs

are in a single-device configuration when the first load (FL), write expansion in (WXI), and read expansion in

(RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during

reset (see Figure 25).

Reset (RS)

18

Data In (D)

18

36

Read Clock (RCLK)

Read Enable (REN)

Write Clock (WCLK)

Write Enable (WEN)

Output Enable (OE)

Programmable (PAF)

Load (LD)

74V215

74V225

74V235

74V245

74V215

74V225

74V235

74V245

Programmable (PAE)

Half-Full Flag (HF)

Empty Flag/

Output Ready

(EF/OR)

Full Flag/

Input Ready

(FF/IR)

FF/IR

EF/OR

FF/IR

EF/OR

Data Out (Q)

18

36

FL WXI RXI

18

NOTE A: Do not connect any output control signals directly together.

Figure 25. Block Diagram of 512 × 36, 1024 × 36, 2048 × 36, or 4096 × 36

Synchronous FIFO Memory Used in a Width-Expansion Configuration

DEPTH-EXPANSION CONFIGURATION, DAISY-CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS)

These devices can be adapted easily to applications requiring more than 512, 1024, 2048, or 4096 words of

buffering. Figure 26 shows depth expansion using three SN74V215, SN74V225, SN74V235, or SN74V245

memories. Maximum depth is limited only by signal loading.

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

WXO RXO

WCLK

WEN

RCLK

REN

OE

RS

LD

74V215

74V225

74V235

74V245

Qn

Dn

V

CC

FL

EF/OR

PAE

FF/IR

PAF

WXI

RXI

WXO RXO

WCLK

WEN

RS

RCLK

REN

OE

LD

Data In

Data Out

74V215

74V225

74V235

74V245

Qn

Dn

V

CC

FL

FF/IR

PAF

EF/OR

PAE

WXI

RXI

WXO RXO

WCLK

Write Clock

Write Enable

Reset

Read Clock

RCLK

WEN

Read Enable

Output Enable

REN

OE

RS

Dn

LD

74V215

Qn

74V225

74V235

74V245

Load

FF/IR

EF/OR

PAE

EF/OR

FF/IR

PAF

PAE

RXI

PAF

WXI

First Load (FL)

NOTES: A. The first device must be designated by grounding the first load (FL) control input.

B. All other devices must have FL in the high state.

C. The write expansion out (WXO) pin of each device must be tied to the write expansion in (WXI) pin of the next device.

D. The read expansion out (RXO) pin of each device must be tied to the read expansion in (RXI) pin of the next device.

E. All load (LD) pins are tied together.

F. The half-full flag (HF) is not available in this depth-expansion configuration.

G. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flag for monitoring. The composite

PAE and PAF flags are not precise.

H. In daisy-chain mode, the flag outputs are single-register buffered and the partial flags are in asynchronous timing mode.

Figure 26. Block Diagram of 1536 × 18, 3072 × 18, 6144 × 18, 12288 × 18

Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

operating configurations (continued)

DEPTH-EXPANSION CONFIGURATION (FWFT MODE)

InFWFTmode, theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnectedtothedatainputs

of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to

the sum of the depths associated with each single FIFO. NO TAG shows a depth expansion using two

SN74V215, SN74V225, SN74V235, or SN74V245 memories.

Care should be taken to select FWFT mode during master reset for all FIFOs in the depth expansion

configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)

until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK

of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s

OR line goes low, enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low

(i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum

of the delays for each individual FIFO:

(N – 1) × (4 × transfer clock) + 3 × T

RCLK

Where: N is the number of FIFOs in the expansion and T

is the RCLK period. Extra cycles should be added

RCLK

for the possibility that the t

specification is not met between WCLK and transfer clock, or RCLK and

SKEW1

transfer clock, for the OR flag.

The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration.

There is no delay evident for subsequent words written to the configuration.

Thefirstfreelocationcreatedbyreadingfromafulldepth-expansionconfigurationbubblesupfromthelastFIFO

to the previous one until finally it moves into the first FIFO of the chain. Each time a free location is created in

one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it.

For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after

a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

(N – 1) × (3 × transfer clock) + 2T

WCLK

Where:NisthenumberofFIFOsintheexpansionandT

istheWCLKperiod.Extracyclesshouldbeadded

WCLK

for the possibility that the t

specification is not met between RCLK and transfer clock, or WCLK and

SKEW1

transfer clock, for the IR flag.

The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result

in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

HF

PAF

PAE

Transfer Clock

Write Clock

Write Enable

Input Ready

Read Clock

WCLK

WEN

RCLK

OR

WCLK

WEN

RCLK

REN

Read Enable

74V215

74V225

74V235

74V245

74V215

74V225

74V235

74V245

Output Ready

Output Enable

n

Data Out

IR

REN

IR

OR

OE

Qn

GND

n

Data In

Dn

Qn

FL RXI WXI

(0,1)

FL RXI WXI

(0,1)

V

CC

V

CC

GND

Figure 27. Block Diagram of 1024 × 18, 2048 × 18, 4096 × 18, 8192 × 18

Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5 V

CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Storage temperature range, T

O

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

3.0

0

TYP

3.3

0

MAX

3.6

0

UNIT

V

Supply voltage

CC

GND Supply voltage

V

High-level input voltage

Low-level input voltage

2

5

V

IH

0.8

70

V

IL

T

A

Operating free-air temperature

0

°C

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= 3.0 V,

= 3.6 V,

= 3.3 V,

= 3.6 V,

I

= –2 mA

2.4

OH

OL

CC

OH

V

= 8 mA

0.4

±1

±10

35

V

OL

I

V = V

to 0.4 V

µA

mA

pF

I

CC

OE ≥ V

,

V

O

= V

to 0.4 V

CC

OZ

IH

See Notes 1, 2, and 3

See Notes 1 and 4

f = 1 MHz

CC1

CC2

5

C

V = 0, T = 25°C,

I

10

IN

A

V

O

= 0, T = 25°C,

f = 1 MHz, Output deselected, (OE ≥ V )

IH

OUT

A

NOTES: 1. Tested with outputs disabled (I

OUT

= 0)

2. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.

3. Typical I = 2.04 + 0.88 × f + 0.02 × C × f (in mA). These equations are valid under the following conditions:

CC1

S

L

S

V

= 3.3 V, T = 25°C, f = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f /2, C = capacitive

CC

A

S

L

load (in pF).

4. All inputs = (V

– 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, which switch at 20 MHz.

CC

37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figure 28 through Figure 23)

’74V215-7

’74V225-7

’74V235-7

’74V245-7

’74V215-10

’74V225-10

’74V235-10

’74V245-10

’74V215-15

’74V225-15

’74V235-15

’74V245-15

’74V215-20

’74V225-20

’74V235-20

’74V245-20

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

f

t

Clock cycle frequency

Data access time

Clock cycle time

Clock high time

Clock low time

133

5

100

6.5

66.7

10

50

12

MHz

ns

clock

2

7.5

3.5

2.5

0.5

2.5

0.5

3.5

0.5

10

2

10

4.5

3

2

15

6

2

20

8

A

CLK

CLKH

CLKL

DS

6

8

Data setup time

Data hold time

4

5

0.5

3

1

DH

Enable setup time

Enable hold time

Load setup time

Load hold time

4

5

ENS

ENH

LDS

LDH

RS

0.5

3.5

0.5

10

8

1

4

1

†

Reset pulse width

Reset setup time

15

10

20

12

8

RSS

RSR

RSF

OLZ

OE

Reset recovery time

8

Reset to flag and output time

Output enable to output in low Z

Output enable to output valid

Output enable to output in high Z

Write clock to Full flag

15

20

0

1

0

1

0

3

0

3

6

5

6

8

10

12

OHZ

WFF

REF

6.5

10

Read clock to Empty flag

Clock to asynchronous programmable

Almost-Full flag

t

12.5

5

17

8

20

10

20

10

22

12

22

12

ns

PAFA

PAFS

PAEA

PAES

Write clock to synchronous programmable

Almost-Full flag

Clock to asynchronous programmable

Almost-Empty flag

12.5

5

17

8

Read clock to synchronous programmable

Almost-Empty flag

t

Clock to Half-Full flag

12.5

5

17

20

10

22

12

ns

HF

XO

XI

Clock to expansion out

Expansion in pulse duration

Expansion in setup time

6.5

2.5

3

6.5

5

8

XIS

Skew time between read clock and write clock for

FF/IR and EF/OR

t

5

7

5

6

8

ns

SKEW1

SKEW2

Skew time between read clock and write clock for

PAE and PAF (synchronous only)

t

14

18

20

†

Pulse durations less than minimum values are not allowed.

38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74V215, SN74V225, SN74V235, SN74V245

512 × 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

PARAMETER MEASUREMENT INFORMATION

AC TEST CONDITIONS

V

CC

/2

GND to 3.0 V

3 ns

Input Pulse Levels

Input Rise/Fall Times

50 Ω

1.5 V

Input Timing Reference Levels

Output Reference Levels

1.5 V

See A

Output Load for t

= 10 ns, 15 ns

Z

O

= 50 Ω

CLK

I/O

See B and C

= 7.5 ns

B. AC TEST LOAD FOR 7.5 SPEED GRADE

3.3 V

6

5

4

3

2

1

0

330 Ω

From Output

Under Test

30 pF

(see Note A)

510 Ω

0

20 40 60 80 100 120 140 160 180 200

Capacitance – pF

A. OUTPUT LOAD CIRCUIT

C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING

FOR 10, 15, AND 20 SPEED GRADES

NOTE A: Includes probe and jig capacitance

Figure 28. Load Circuits

39

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

CV215-10PAGG4

CV235-7PAGG4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TQFP

PAG

64

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TQFP

PAG

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

CV245-10PAGG4

CV245-7PAGG4

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

SN74V215-10PAG

SN74V215-15PAG

SN74V215-20PAG

SN74V215-7PAG

SN74V225-10PAG

SN74V225-15PAG

SN74V225-20PAG

SN74V225-7PAG

SN74V235-10PAG

SN74V235-15PAG

SN74V235-20PAG

SN74V235-7PAG

SN74V245-10PAG

SN74V245-15PAG

SN74V245-20PAG

SN74V245-7PAG

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

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Addendum-Page 2

MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PAG (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

48

M

0,08

33

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

11,80

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4040282/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP, TQFP64,.47SQ	针数：	64
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.73
最长访问时间：	6.5 ns	最大时钟频率 (fCLK)：	100 MHz
周期时间：	10 ns	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e4	长度：	10 mm
内存密度：	73728 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	64
字数：	4096 words	字数代码：	4000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4KX18
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP64,.47SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	FIFOs
最大压摆率：	0.035 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

型号	制造商	描述	替代类型	文档
SN74V245-10PAG	TI	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES	完全替代
72V245L10TF8	IDT	TQFP-64, Reel	类似代替

型号	制造商	描述	价格	文档
CV245-7PAGG4	TI	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES	获取价格
CV24S12-3000	WALL	Output Current up to 3A	获取价格
CV24S5-3000	WALL	Output Current up to 3A	获取价格
CV25-1R0-JB	RCD	General Purpose Inductor, 1uH, 5%, 1 Element,	获取价格
CV25-1R0-JBQ	RCD	General Purpose Inductor, 1uH, 5%, 1 Element,	获取价格
CV25-1R0-KBQ	RCD	General Purpose Inductor, 1uH, 10%, 1 Element,	获取价格
CV25-1R0-KBW	RCD	General Purpose Inductor, 1uH, 10%, 1 Element, ROHS COMPLIANT	获取价格
CV251HA40	IXYS	RESISTOR, VOLTAGE DEPENDENT, 330V, CHASSIS MOUNT	获取价格
CV271HA32	IXYS	RESISTOR, VOLTAGE DEPENDENT, 369V, CHASSIS MOUNT	获取价格
CV271HA40	IXYS	RESISTOR, VOLTAGE DEPENDENT, 369V, CHASSIS MOUNT	获取价格

CV245-10PAGG4

CV245-10PAGG4 概述

CV245-10PAGG4 规格参数

CV245-10PAGG4 数据手册

CV245-10PAGG4 替代型号

CV245-10PAGG4 相关器件

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