CY29FCT52CTQC [TI]
8-Bit Registered Transceiver; 8位寄存收发器
| 型号： | CY29FCT52CTQC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit Registered Transceiver |
| 文件： | 总10页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM2952
Reduced V
of Equivalent FCT Functions
(Typically = 3.3 V) Versions
B
B
B
B
B
B
B
B
V
A
A
A
A
A
A
A
A
1
24
23
22
21
20
19
18
17
16
15
14
OH
7
6
5
4
3
2
1
0
CC
7
2
3
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
6
4
5
5
4
6
3
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
7
2
8
1
OEB
CPA
CEA
9
– 1000-V Charged-Device Model (C101)
0
OEA
CPB
10
11
I
Supports Partial-Power-Down Mode
off
Operation
GND 12
13 CEB
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
64-mA Output Sink Current
32-mA Output Source Current
description
The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two
bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each
register. Both A outputs and B outputs are specified to sink 64 mA.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
DESCRIPTION
A
B
A register inputs or B register outputs
B register inputs or A register outputs
CPA
Clock for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal.
ClockenablefortheAregister.WhenCEAislow,dataenterstheAregisteronthelow-to-hightransitionoftheCPAsignal.WhenCEA
is high, the A register holds its contents, regardless of CPA signal transitions.
CEA
OutputenablefortheAregister.WhenOEAislow,theAregisteroutputsareenabledontotheBlines.WhenOEAishigh,theAoutputs
are in the high-impedance state.
OEA
CPB
CEB
Clock for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal.
Clock enable for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. When
CEB is high, the B register holds its contents, regardless of CPA signal transitions.
OutputenablefortheBregister.WhenOEBislow,theBregisteroutputsareenabledontotheAlines.WhenOEBishigh,theBoutputs
are in the high-impedance state.
OEB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
(ns)
6.3
6.3
6.3
QSOP – Q
SOIC – SO
Tape and reel
Tube
CY29FCT52CTQCT
CY29FCT52CTSOC
CY29FCT52CTSOCT
29FCT52C
–40°C to 85°C
29FCT52C
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Function Tables
FUNCTION TABLE
INPUTS
INTERNAL
Q
FUNCTION
Hold data
Load data
D
X
L
CP
CE
H
X
NC
L
L
H
L
H
H = High logic level, L = Low logic level, X = Don’t care,
NC = No change
OUTPUT CONTROL
INTERNAL
Q
Y
OE
FUNCTION
OUTPUTS
H
L
L
X
L
Z
L
Disable outputs
Enable outputs
H
H
H = High logic level, L = Low logic level, X = Don’t care,
Z = High impedance (off) state.
logic diagram
CPA
CEA
OEB
CE CP
A
0
D
0
Q
0
B
0
A
1
B
1
D
1
Q
1
A
2
B
2
D
2
Q
2
A
3
B
3
D
3
Q
3
B
4
A
4
D
4
Q
4
B
A
5
5
D
Q
5
5
A
6
B
6
D
6
Q
6
A
7
B
7
D
7
Q
7
Q
0
D
0
Q
1
D
1
Q
2
D
2
Q
3
D
3
Q
4
D
4
Q
5
D
5
Q
6
D
6
CE CP
Q
7
D
7
OEA
CPB
CEB
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
†
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance,
(see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 135 C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.75
2
5
5.25
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–32
64
V
IL
I
mA
mA
°C
OH
OL
I
T
A
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 4.75 V,
= 4.75 V
= 4.75 V,
I
I
I
I
= –18 mA
–0.7
–1.2
V
IK
CC
CC
CC
IN
= –32 mA
= –15 mA
= 64 mA
2
OH
OH
OL
V
OH
V
2.4
3.3
0.3
0.2
V
V
0.55
V
OL
All inputs
V
H
I
I
I
I
I
I
V
V
V
V
V
V
V
V
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
= V
CC
5
±1
µA
µA
µA
mA
µA
mA
mA
I
CC
CC
CC
CC
CC
CC
CC
CC
IN
= 2.7 V
= 0.5 V
IH
IN
±1
IL
IN
‡
= 0 V
–60
–120
–225
±1
OS
off
CC
OUT
OUT
= 4.5 V
= 5.25 V, V < 0.2 V, V ≥ V
IN IN
– 0.2 V
0.1
0.5
0.2
2
CC
§
∆I
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
CC
1
= 5.25 V, One input switching at 50% duty cycle, Outputs open,
– 0.2 V
mA/
MHz
¶
I
0.06
0.12
CCD
OEA or OEB = GND, V < 0.2 V or V > V
IN IN CC
V
V
< 0.2 V or
One bit switching
IN
IN
0.7
1.2
1.6
1.4
3.4
> V
– 0.2 V
at f = 5 MHz
CC
1
V
= 5.25 V,
CC
= 10 MHz,
at 50% duty cycle
V
IN
= 3.4 V or GND
f
#
I
C
mA
Outputs open,
V
IN
V
IN
< 0.2 V or
Eight bits switching
||
||
3.2
OEA or OEB = GND
> V
– 0.2 V
at f = 2.5 MHz
CC
1
at 50% duty cycle
V
IN
= 3.4 V or GND
3.9 12.2
C
C
5
9
10
12
pF
pF
i
o
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL driven input (V = 3.4 V); all other inputs at V
tests should be performed last.
OS
§
¶
#
or GND
IN CC
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC
H
T
CCD
0
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
formula.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
PARAMETER
MIN
3
MAX
UNIT
t
t
Pulse duration, clock
ns
w
Data
2.5
3
ns
ns
Setup time, before CPA↑ or CPB↑
su
CEA or CEB
Data
1.5
2
t
h
Hold time, after CPA↑ or CPB↑
CEA or CEB
switching characteristics over operating free-air temperature range (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
t
2
2
6.3
6.3
7
PLH
PHL
PZH
PZL
PHZ
PLZ
CPA, CPB
OEA or OEB
OEA or OEB
A, B
ns
1.5
1.5
1.5
1.5
A or B
A or B
ns
ns
7
6.5
6.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
/t
S1
t
Open
7 V
PLH PHL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2005
PACKAGING INFORMATION
Orderable Device
CY29FCT52CTQC
Status (1)
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
24
24
24
24
24
24
55
TBD
Call TI
Call TI
CY29FCT52CTQCT
CY29FCT52CTQCTE4
CY29FCT52CTSOC
CY29FCT52CTSOCE4
CY29FCT52CTSOCT
CY29FCT52CTSOCTE4
SSOP/
QSOP
DBQ
DBQ
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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