CY74FCT163501CPACT [TI]
18-Bit Registered Transceivers; 18位寄存收发器
| 型号： | CY74FCT163501CPACT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit Registered Transceivers |
| 文件： | 总9页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
18-Bit Registered Transceivers
• Eliminates the need for external pull-up or pull-down
resistors
Features
• Low power, pin-compatible replacement for LCX and
LPT families
Functional Description
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
CY74FCT163501 Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 3.3V,
TA= 25˚C
The CY74FCT163H501 is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
CY74FCT163H501 Features:
• Bus hold retains the last active state
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Pin Configuration
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
SSOP/TSSOP
Top View
OEAB
LEAB
1
2
56
55
GND
CLKAB
A
1
B
1
GND
3
4
54
53
GND
A
2
B
2
5
6
7
8
9
52
51
50
49
48
OEAB
CLKBA
LEBA
A
B
3
3
V
CC
V
CC
A
4
B
4
A
A
B
5
5
6
B
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEBA
CLKAB
LEAB
GND
GND
A
7
B
7
A
A
B
8
8
9
B
9
A
A
A
B
10
10
C
D
C
D
B
11
B
1
11
12
A
1
B
12
GND
GND
B
13
A
13
C
D
C
D
A
B
14
14
A
B
15
15
V
CC
V
CC
A
A
B
16
16
17
B
17
GND
GND
B
18
FCT163501-1
TO 17 OTHER CHANNELS
A
18
CLKBA
GND
OEBA
LEBA
FCT163501-2
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163501
CY74FCT163H501
Maximum Ratings[6, 7]
Pin Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Name
Description
OEAB
OEBA
LEAB
LEBA
A-to-B Output Enable Input
Storage Temperature .....................................−55°C to +125°C
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
B-to-A Latch Enable Input
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Operating Range
Function Table[2, 3]
Ambient
Range
Industrial
Temperature
VCC
Inputs
Outputs
B
−40°C to +85°C
2.7V to 3.6V
OEAB
LEAB
CLKAB
A
L
H
H
H
X
H
H
L
X
X
X
X
L
Z
L
H
L
H
L
H
L
H
H
H
H
L
L
L
X
X
B[4]
B[5]
H
1. On the 74FCT163H501 these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT163501
CY74FCT163H501
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC = 2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min.
Typ.[8] Max.
Unit
V
VIH
VIL
VH
VIK
IIH
2.0
5.5
Input LOW Voltage
Input Hysteresis[9]
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
VCC=Min., IIN=–18 mA
VCC=Max., VI=5.5
–0.7
–1.2
±1
µA
IIL
Input LOW Current
VCC=Max., VI=GND
±1
±1
µA
µA
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=5.5V
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[10]
VCC=Max., VOUT=GND
–60
–135
–240
±100
10
mA
µA
µA
IOFF
ICC
Power-Off Disable
VCC=0V, VOUT≤4.5V
Quiescent Power Supply Current
VIN≤0.2V,
VCC=Max.
0.1
2.0
VIN>VCC–0.2V
VIN=VCC–0.6V[11] VCC=Max.
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
30
µA
Notes:
8. Typical values are at VCC=3.3V, TA = +25˚C ambient.
9. This parameter is specified but not tested.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
3
CY74FCT163501
CY74FCT163H501
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min. Typ.[8] Max.
Unit
V
VIH
VIL
VH
VIK
IIH
2.0
VCC
0.8
Input LOW Voltage
Input Hysteresis[9]
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
VCC=Min., IIN=–18 mA
VCC=Max., VI=VCC
–0.7
–1.2
±100
µA
IIL
Input LOW Current
VCC=Max., VI=GND
±100
µA
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold Input[12] VCC=Min.
VI=2.0V
VI=0.8V
–50
+50
µA
µA
µA
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[12] VCC=Max., VI=1.5V
±500
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=VCC
VCC=Max., VOUT=GND
±1
±1
µA
µA
IOZL
High Impedance Output Current
(Three-State Output pins)
IOS
Short Circuit Current[10]
VCC=Max., VOUT=GND
–60
–135 –240
±100
mA
µA
µA
IOFF
ICC
Power-Off Disable
VCC=0V, VOUT≤4.5V
Quiescent Power Supply Current
VIN≤0.2V,
VCC=Max.
+40
VIN>VCC–0.2V
∆
Quiescent Power supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[11] VCC=Max.
+350
µA
ICC
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.[8] Max.
Unit
IODL
Output LOW Dynamic Current[10]
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
45
180
mA
IODH
VOH
Output HIGH Dynamic Current[10]
Output HIGH Voltage
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–45
–180
mA
VCC=Min., IOH= –0.1 mA VCC–0.2
V
V
V
V
VCC=3.0V, IOH= –8 mA
VCC=3.0V, IOH= –24 mA
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
2.4[13]
3.0
3.0
0.2
2.0
VOL
Output LOW Voltage
0.3
0.55
Capacitance[9](TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.[8]
Max.
Unit
CIN
VIN = 0V
4.5
5.5
6.0
8.0
pF
pF
COUT
VOUT = 0V
Notes:
12. Pins with bus hold are described in Pin Description.
13. OH=VCC – 0.6V at rated current.
V
4
CY74FCT163501
CY74FCT163H501
Power Supply Characteristics
Sym.
Parameter
Test Conditions[14]
Min. Typ.[8]
Max.
Unit
ICCD
Dynamic Power Supply
Current[15]
VCC=Max., Outputs Open
VIN=VCC or
VIN=GND
—
75
120
µA/
MHz
OEAB=OEBA=VCC or GND
One Input Toggling,
50% Duty Cycle
IC
Total Power Supply
Current[16]
VCC=Max., Outputs Open
f0 =10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB = GND, One Bit Toggling
f1 = 5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND
—
—
0.8
1.3
1.7
3.2
mA
VIN=3.4V or
VIN=GND
VCC=Max., Outputs Open
f0 = 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND
—
—
3.8
8.5
6.5[17]
VIN=3.4V or
VIN=GND
20.8[17]
Eighteen Bits Toggling
f1=2.5MHz, 50% Duty Cycle
Notes:
14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
15. This parameter is not directly testable, but is derived for use in Total Power Supply Current.
16. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
=
=
=
=
=
=
=
=
=
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC
∆ICC
DH
NT
ICCD
f0
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
f1
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
5
CY74FCT163501
CY74FCT163H501
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[18]
CY74FCT163501C
CY74FCT163H501C
Parameter
Description
CLKAB or CLKBA frequency[9]
Min.
—
Max.
150
4.6
Unit Fig.No.[19]
fMAX
MHz
ns
—
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
1,3
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
1.5
1.5
5.3
5.3
ns
ns
1,5
1,5
tPLH
tPHL
Propagation Delay
CLKBA to A,
CLKAB to B
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
1.5
1.5
3.0
5.6
5.2
—
ns
ns
ns
1,7,8
1,7,8
4
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
tSU
Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
tH
Hold Time
0
—
ns
4
HIGH or LOW
A to CLKAB,
B to CLKBA
tSU
Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Clock LOW
Clock HIGH
3.0
1.5
—
—
ns
ns
4
4
tH
Hold Time, HIGH or LOW, A to LEAB,
B to LEBA
1.5
—
ns
4
tW
tW
LEAB or LEBA Pulse Width HIGH[9]
CLKAB or CLKBA Pulse Width HIGH or LOW[9]
Output Skew[20]
3.0
3.0
—
—
—
ns
ns
ns
5
5
tSK(O)
0.5
—
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
6
CY74FCT163501
CY74FCT163H501
Ordering Information CY74FCT163501T
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT163501CPACT
CY74FCT163501CPVC/PVCT
Name
Package Type
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
4.6
Z56
Industrial
O56
Ordering Information CY74FCT163H501T
Speed
(ns)
Package
Operating
Range
Ordering Code
74FCT163H501CPACT
CY74FCT163H501CPVC
74FCT163H501CPVCT
Name
Package Type
4.6
Z56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
Industrial
O56
O56
Package Diagrams
56-Lead Shrunk Small Outline Package O56
7
CY74FCT163501
CY74FCT163H501
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package Z56
8
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
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