CY74FCT163652APAC [TI]
16-Bit Registered Transceiver; 16位寄存收发器
| 型号： | CY74FCT163652APAC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Registered Transceiver |
| 文件： | 总12页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163652
SCCS052 - March 1997 - Revised March 2000
16-Bit Registered Transceiver
Features
Functional Description
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
The CY74FCT163652 is a 16-bit, high-speed, low-power,
registered transceiver that is organized as two independent
8-bit bus transceivers with three-state D-type registers and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal storage
registers. OEAB and OEBA control pins are provided to control
the transceiver functions. SAB and SBA control pins are
provided to select either real-time or stored data transfer.
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CLKAB or CLKBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration, each output reinforces
its input. Thus, when all other data sources to the two sets of
bus lines are at high impedance, each set of bus lines will
remain at its last state.
The CY74FCT163652 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs were designed to be capable of being driven by
5.0V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power-off disable feature enabling them to be used in
applications requiring live insertion.
Logic Block Diagrams
OEAB
1
OEAB
2
OEBA
1
OEBA
2
CLKBA
1
1
CLKBA
2
SBA
2
SBA
1
CLKAB
CLKAB
2
SAB
2
SAB
1
B REG
D
B REG
D
C
C
A
1
2
A
1
1
A REG
A REG
D
C
D
C
B
B
1
1
1
2
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163652
Pin Configuration
SSOP/TSSOP
Top View
OEAB
OEBA
1
1
2
56
55
1
CLKBA
CLKAB
1
1
SAB
1
SBA
3
4
54
53
1
GND
A
GND
B
B
5
6
7
52
51
50
1
1
1
2
1
1
1
2
A
V
CC
V
CC
A
3
B
3
1
1
1
8
9
49
48
1
1
1
A
4
B
4
A
B
5
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
GND
GND
A
A
A
B
B
B
B
B
B
1
1
1
6
7
8
1
1
1
2
2
2
6
7
8
1
2
3
A
A
2
2
1
2
A
3
2
GND
GND
B
B
B
A
2
2
2
4
5
6
2
4
A
A
2
2
5
6
V
2
V
CC
CC
B
7
A
2
2
7
8
A
B
8
2
24
25
26
33
32
31
30
29
GND
SBA
GND
SAB
2
2
CLKAB
OEAB
27
28
CLKBA
OEBA
2
2
2
2
Pin Description
Name
Description
A
Data Register A Inputs, Data Register B Outputs
Data Register B Inputs, Data Register A Outputs
Clock Pulse Inputs
B
CLKAB, CLKBA
SAB, SBA
OEAB, OEBA
Output Data Source Select Inputs
Output Enable Inputs
2
CY74FCT163652
Function Table[1]
Inputs
OEBA CLKAB CLKBA
Data I/O[2]
OEAB
SAB
SBA
A
B
Operation or Function
L
L
H
H
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
X
H
H
H
H or L
X
X
X
Input
Input
Unspecified[2] Store A, Hold B
X[3]
Output
Store A in Both Registers
L
L
X
L
H or L
X
X
X
Unspecified[2]
Input
Input
Hold A, Store B
Store B in both Registers
X[3]
L
L
L
L
X
X
X
X
X
L
H
Output
Input
Input
Output
Output
Real Time B Data to A Bus
Stored B Data to A Bus
H or L
H
H
H
H
X
X
X
L
H
X
X
Real Time A Data to B Bus
Stored A Data to B Bus
H or L
H
L
H or L
H or L
H
H
Output
Stored A Data to B Bus and
Stored B Data to A Bus
Notes:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care,
= LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.
3
CY74FCT163652
BUS A
BUS B
BUS A
BUS B
OEAB
L
OEBA
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
OEAB
H
OEBA
L
CLKAB
X
CLKBA
X
SAB
L
SBA
X
Real-Time Transfer
BusB to BusA
Real-Time Transfer
BusA to BusB
BUS A
BUS B
BUS A
BUS A
OEAB
OEBA
SAB
SBA
X
X
OEAB
H
OEBA
L
SAB
H
SBA
H
CLKAB
X
CLKBA
X
CLKAB
H or L
CLKBA
H or L
X
L
L
H
X
H
X
X
X
X
Storage from
A and/or B
Transfer Stored Data
to A and/or B
Maximum Ratings[4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
Storage Temperature .............................. −55°C to +125°C
Power Dissipation..........................................................1.0W
Ambient Temperature with
Power Applied.......................................... −55°C to +125°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Supply Voltage Range ..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
Operating Range
Ambient
Range
Industrial
Temperature
VCC
–40°C to +85°C
2.7V to 3.6V
Note:
4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
CY74FCT163652
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Condition
Min.
Typ.[5]
Max.
5.5
Unit
V
VIH
VIL
VH
VIK
IIH
All Inputs
2.0
Input LOW Voltage
Input Hysteresis[6]
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
VCC=Max., VI=5.5V
VCC=Max., VI=GND
VCC=Max., VOUT=5.5V
−0.7
−1.2
±1
µA
µA
µA
IIL
±1
IOZH
High Impedance Output Current
(Three-State Output pins)
±1
IOZL
IODL
IODH
VOH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
mA
mA
V
Output LOW Dynamic Current[7]
Output HIGH Dynamic Current[7]
Output HIGH Voltage
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
45
180
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–45
–180
VCC=Min., IOH= –0.1 mA
VCC=3.0V, IOH= –8 mA
VCC=3.0V, IOH= –24 mA
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
VCC=Max., VOUT=GND
VCC=0V, VOUT≤4.5V
VCC–0.2
2.4[8]
2.0
3.0
3.0
VOL
Output LOW Voltage
0.2
0.5
V
0.3
IOS
Short Circuit Current[7]
Power-Off Disable[7]
–60
–135
–240
±100
mA
IOFF
µA
Capacitance[6] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
4.5
Max.
6.0
Unit
pF
CIN
VIN = 0V
VOUT = 0V
COUT
5.5
8.0
pF
Notes:
5. Typical values are at VCC=3.3V, +25°C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. VOH=VCC–0.6V at rated current.
5
CY74FCT163652
Power Supply Characteristics
Parameter
Description
Test Conditions
VIN<0.2V
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply Current VCC=Max.
0.1
10
µA
VIN>VCC−0.2V
∆ICC
Quiescent Power Supply Current VCC = Max.
TTL Inputs HIGH
VIN=VCC–0.6V[9]
2.0
50
30
75
µA
ICCD
Dynamic Power Supply
Current[10]
VCC=Max., Outputs Open
VIN=VCC or
VIN=GND
µA/MHz
OEAB=OEAB=GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current[11]
VCC=Max., Outputs Open
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
One-Bit Toggling, f1=5 MHz
50% Duty Cycle
VIN=VCC or
VIN=GND
0.5
0.5
0.8
0.8
mA
mA
VIN=VCC–0.6V
or VIN=GND
VCC=Max., Outputs Open
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
Sixteen Bits Toggling
f1=2.5 MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND
2.5
2.6
3.8[12]
4.1[12]
mA
mA
VIN=VCC–0.6V
or VIN=GND
Notes:
9. Per TTL driven input; all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
11. IC
IC
=
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
NC
f1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Number of clock inputs changing at f1
Input signal frequency
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
6
CY74FCT163652
Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[13,14]
CY74FCT163652A CY74FCT163652C
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.[15]
tPLH
tPHL
Propagation Delay
Bus to Bus
1.5
6.3
1.5
5.4
ns
1, 3
tPZH
tPHL
Output Enable Time
OEAB or OEBA to Bus
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
9.8
6.3
6.3
7.7
—
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
7.8
6.3
5.7
6.2
—
ns
ns
ns
ns
ns
ns
ns
ns
1, 7, 8
1, 7, 8
1, 5
1, 5
4
tPHZ
tPLZ
Output Disable Time
OEAB or OEBA to Bus
tPLH
tPHL
Propagation Delay
Clock to Bus
tPLH
tPHL
Propagation Delay
SBA or SAB to Bus
tSU
Set-Up time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
—
—
4
tW
Clock Pulse Width
HIGH or LOW
—
—
5
tSK(O)
Output Skew[16]
0.5
0.5
Ordering Information CY74FCT163652
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT163652CPACT
CY74FCT163652CPVC/PVCT
CY74FCT163652APACT
Package Type
5.4
Z56
O56
Z56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
Industrial
6.3
Industrial
Notes:
13. Minimum limits are specified, but not tested, on propagation delays.
14. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
15. See “Parameter Measurement Information” in the General Information section.
16. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
7
CY74FCT163652
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
8
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DGG
DGG
DGG
DGG
DL
CY74FCT163652APAC
CY74FCT163652APACT
CY74FCT163652CPAC
CY74FCT163652CPACT
CY74FCT163652CPVC
CY74FCT163652CPVCT
OBSOLETE TSSOP
OBSOLETE TSSOP
OBSOLETE TSSOP
OBSOLETE TSSOP
56
56
56
56
56
56
TBD
TBD
TBD
TBD
TBD
TBD
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OBSOLETE
OBSOLETE
SSOP
SSOP
DL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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